^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * @File cthw20k2.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * @Brief
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This file contains the implementation of hardware access method for 20k2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * @Author Liu Chun
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * @Date May 14 2008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "cthw20k2.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "ct20k2reg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct hw20k2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* for i2c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) unsigned char dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) unsigned char addr_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) unsigned char data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) int mic_source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static u32 hw_read_20kx(struct hw *hw, u32 reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static void hw_write_20kx(struct hw *hw, u32 reg, u32 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * Type definition block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * The layout of control structures can be directly applied on 20k2 chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * SRC control block definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* SRC resource control block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SRCCTL_STATE 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SRCCTL_BM 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SRCCTL_RSR 0x00000030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SRCCTL_SF 0x000001C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SRCCTL_WR 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SRCCTL_PM 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SRCCTL_ROM 0x00001800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SRCCTL_VO 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SRCCTL_ST 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SRCCTL_IE 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SRCCTL_ILSZ 0x000F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SRCCTL_BP 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SRCCCR_CISZ 0x000007FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SRCCCR_CWA 0x001FF800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SRCCCR_D 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SRCCCR_RS 0x01C00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SRCCCR_NAL 0x3E000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SRCCCR_RA 0xC0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SRCCA_CA 0x0FFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SRCCA_RS 0xE0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SRCSA_SA 0x0FFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SRCLA_LA 0x0FFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Mixer Parameter Ring ram Low and Hight register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * Fixed-point value in 8.24 format for parameter channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MPRLH_PITCH 0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* SRC resource register dirty flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) union src_dirty {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u16 ctl:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u16 ccr:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u16 sa:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u16 la:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u16 ca:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u16 mpr:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u16 czbfs:1; /* Clear Z-Buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u16 rsv:9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) } bf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct src_rsc_ctrl_blk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned int ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int ccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned int ca;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned int sa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) unsigned int la;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned int mpr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) union src_dirty dirty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* SRC manager control block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) union src_mgr_dirty {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u16 enb0:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u16 enb1:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u16 enb2:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u16 enb3:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u16 enb4:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u16 enb5:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u16 enb6:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u16 enb7:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u16 enbsa:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u16 rsv:7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) } bf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct src_mgr_ctrl_blk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned int enbsa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) unsigned int enb[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) union src_mgr_dirty dirty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* SRCIMP manager control block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SRCAIM_ARC 0x00000FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SRCAIM_NXT 0x00FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SRCAIM_SRC 0xFF000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct srcimap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned int srcaim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* SRCIMP manager register dirty flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) union srcimp_mgr_dirty {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u16 srcimap:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u16 rsv:15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) } bf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct srcimp_mgr_ctrl_blk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct srcimap srcimap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) union srcimp_mgr_dirty dirty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * Function implementation block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int src_get_rsc_ctrl_blk(void **rblk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct src_rsc_ctrl_blk *blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) *rblk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) blk = kzalloc(sizeof(*blk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (!blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) *rblk = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static int src_put_rsc_ctrl_blk(void *blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) kfree(blk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int src_set_state(void *blk, unsigned int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct src_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) set_field(&ctl->ctl, SRCCTL_STATE, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ctl->dirty.bf.ctl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int src_set_bm(void *blk, unsigned int bm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct src_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) set_field(&ctl->ctl, SRCCTL_BM, bm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ctl->dirty.bf.ctl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int src_set_rsr(void *blk, unsigned int rsr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct src_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) set_field(&ctl->ctl, SRCCTL_RSR, rsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ctl->dirty.bf.ctl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int src_set_sf(void *blk, unsigned int sf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct src_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) set_field(&ctl->ctl, SRCCTL_SF, sf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ctl->dirty.bf.ctl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static int src_set_wr(void *blk, unsigned int wr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct src_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) set_field(&ctl->ctl, SRCCTL_WR, wr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) ctl->dirty.bf.ctl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static int src_set_pm(void *blk, unsigned int pm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct src_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) set_field(&ctl->ctl, SRCCTL_PM, pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ctl->dirty.bf.ctl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int src_set_rom(void *blk, unsigned int rom)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct src_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) set_field(&ctl->ctl, SRCCTL_ROM, rom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ctl->dirty.bf.ctl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static int src_set_vo(void *blk, unsigned int vo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct src_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) set_field(&ctl->ctl, SRCCTL_VO, vo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ctl->dirty.bf.ctl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static int src_set_st(void *blk, unsigned int st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct src_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) set_field(&ctl->ctl, SRCCTL_ST, st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ctl->dirty.bf.ctl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static int src_set_ie(void *blk, unsigned int ie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct src_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) set_field(&ctl->ctl, SRCCTL_IE, ie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ctl->dirty.bf.ctl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static int src_set_ilsz(void *blk, unsigned int ilsz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct src_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) set_field(&ctl->ctl, SRCCTL_ILSZ, ilsz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) ctl->dirty.bf.ctl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static int src_set_bp(void *blk, unsigned int bp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct src_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) set_field(&ctl->ctl, SRCCTL_BP, bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) ctl->dirty.bf.ctl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static int src_set_cisz(void *blk, unsigned int cisz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct src_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) set_field(&ctl->ccr, SRCCCR_CISZ, cisz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ctl->dirty.bf.ccr = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static int src_set_ca(void *blk, unsigned int ca)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct src_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) set_field(&ctl->ca, SRCCA_CA, ca);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ctl->dirty.bf.ca = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int src_set_sa(void *blk, unsigned int sa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct src_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) set_field(&ctl->sa, SRCSA_SA, sa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ctl->dirty.bf.sa = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static int src_set_la(void *blk, unsigned int la)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct src_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) set_field(&ctl->la, SRCLA_LA, la);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ctl->dirty.bf.la = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static int src_set_pitch(void *blk, unsigned int pitch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct src_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) set_field(&ctl->mpr, MPRLH_PITCH, pitch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ctl->dirty.bf.mpr = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static int src_set_clear_zbufs(void *blk, unsigned int clear)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ((struct src_rsc_ctrl_blk *)blk)->dirty.bf.czbfs = (clear ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static int src_set_dirty(void *blk, unsigned int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ((struct src_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static int src_set_dirty_all(void *blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ((struct src_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define AR_SLOT_SIZE 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define AR_SLOT_BLOCK_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define AR_PTS_PITCH 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define AR_PARAM_SRC_OFFSET 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static unsigned int src_param_pitch_mixer(unsigned int src_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return ((src_idx << 4) + AR_PTS_PITCH + AR_SLOT_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) - AR_PARAM_SRC_OFFSET) % AR_SLOT_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static int src_commit_write(struct hw *hw, unsigned int idx, void *blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct src_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (ctl->dirty.bf.czbfs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* Clear Z-Buffer registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) for (i = 0; i < 8; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) hw_write_20kx(hw, SRC_UPZ+idx*0x100+i*0x4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) for (i = 0; i < 4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) hw_write_20kx(hw, SRC_DN0Z+idx*0x100+i*0x4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) for (i = 0; i < 8; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) hw_write_20kx(hw, SRC_DN1Z+idx*0x100+i*0x4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ctl->dirty.bf.czbfs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (ctl->dirty.bf.mpr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* Take the parameter mixer resource in the same group as that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * the idx src is in for simplicity. Unlike src, all conjugate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * parameter mixer resources must be programmed for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * corresponding conjugate src resources. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) unsigned int pm_idx = src_param_pitch_mixer(idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) hw_write_20kx(hw, MIXER_PRING_LO_HI+4*pm_idx, ctl->mpr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) hw_write_20kx(hw, MIXER_PMOPLO+8*pm_idx, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) hw_write_20kx(hw, MIXER_PMOPHI+8*pm_idx, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ctl->dirty.bf.mpr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (ctl->dirty.bf.sa) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) hw_write_20kx(hw, SRC_SA+idx*0x100, ctl->sa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ctl->dirty.bf.sa = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (ctl->dirty.bf.la) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) hw_write_20kx(hw, SRC_LA+idx*0x100, ctl->la);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ctl->dirty.bf.la = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (ctl->dirty.bf.ca) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) hw_write_20kx(hw, SRC_CA+idx*0x100, ctl->ca);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ctl->dirty.bf.ca = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* Write srccf register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) hw_write_20kx(hw, SRC_CF+idx*0x100, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (ctl->dirty.bf.ccr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) hw_write_20kx(hw, SRC_CCR+idx*0x100, ctl->ccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) ctl->dirty.bf.ccr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (ctl->dirty.bf.ctl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) hw_write_20kx(hw, SRC_CTL+idx*0x100, ctl->ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ctl->dirty.bf.ctl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static int src_get_ca(struct hw *hw, unsigned int idx, void *blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct src_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) ctl->ca = hw_read_20kx(hw, SRC_CA+idx*0x100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) ctl->dirty.bf.ca = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return get_field(ctl->ca, SRCCA_CA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static unsigned int src_get_dirty(void *blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return ((struct src_rsc_ctrl_blk *)blk)->dirty.data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static unsigned int src_dirty_conj_mask(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static int src_mgr_enbs_src(void *blk, unsigned int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) ((struct src_mgr_ctrl_blk *)blk)->enbsa |= (0x1 << ((idx%128)/4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ((struct src_mgr_ctrl_blk *)blk)->dirty.bf.enbsa = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static int src_mgr_enb_src(void *blk, unsigned int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static int src_mgr_dsb_src(void *blk, unsigned int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] &= ~(0x1 << (idx%32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static int src_mgr_commit_write(struct hw *hw, void *blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct src_mgr_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) unsigned int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (ctl->dirty.bf.enbsa) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ret = hw_read_20kx(hw, SRC_ENBSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) } while (ret & 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) hw_write_20kx(hw, SRC_ENBSA, ctl->enbsa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) ctl->dirty.bf.enbsa = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if ((ctl->dirty.data & (0x1 << i))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) hw_write_20kx(hw, SRC_ENB+(i*0x100), ctl->enb[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ctl->dirty.data &= ~(0x1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static int src_mgr_get_ctrl_blk(void **rblk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct src_mgr_ctrl_blk *blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) *rblk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) blk = kzalloc(sizeof(*blk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (!blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) *rblk = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static int src_mgr_put_ctrl_blk(void *blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) kfree(blk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static int srcimp_mgr_get_ctrl_blk(void **rblk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct srcimp_mgr_ctrl_blk *blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) *rblk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) blk = kzalloc(sizeof(*blk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (!blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) *rblk = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static int srcimp_mgr_put_ctrl_blk(void *blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) kfree(blk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static int srcimp_mgr_set_imaparc(void *blk, unsigned int slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct srcimp_mgr_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) set_field(&ctl->srcimap.srcaim, SRCAIM_ARC, slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) ctl->dirty.bf.srcimap = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static int srcimp_mgr_set_imapuser(void *blk, unsigned int user)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct srcimp_mgr_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) set_field(&ctl->srcimap.srcaim, SRCAIM_SRC, user);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) ctl->dirty.bf.srcimap = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static int srcimp_mgr_set_imapnxt(void *blk, unsigned int next)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct srcimp_mgr_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) set_field(&ctl->srcimap.srcaim, SRCAIM_NXT, next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) ctl->dirty.bf.srcimap = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static int srcimp_mgr_set_imapaddr(void *blk, unsigned int addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) ((struct srcimp_mgr_ctrl_blk *)blk)->srcimap.idx = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) ((struct srcimp_mgr_ctrl_blk *)blk)->dirty.bf.srcimap = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static int srcimp_mgr_commit_write(struct hw *hw, void *blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct srcimp_mgr_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (ctl->dirty.bf.srcimap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) hw_write_20kx(hw, SRC_IMAP+ctl->srcimap.idx*0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ctl->srcimap.srcaim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ctl->dirty.bf.srcimap = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * AMIXER control block definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define AMOPLO_M 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define AMOPLO_IV 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define AMOPLO_X 0x0003FFF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define AMOPLO_Y 0xFFFC0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define AMOPHI_SADR 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define AMOPHI_SE 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* AMIXER resource register dirty flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) union amixer_dirty {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) u16 amoplo:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) u16 amophi:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) u16 rsv:14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) } bf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) u16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* AMIXER resource control block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct amixer_rsc_ctrl_blk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) unsigned int amoplo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) unsigned int amophi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) union amixer_dirty dirty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static int amixer_set_mode(void *blk, unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct amixer_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) set_field(&ctl->amoplo, AMOPLO_M, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) ctl->dirty.bf.amoplo = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static int amixer_set_iv(void *blk, unsigned int iv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) struct amixer_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) set_field(&ctl->amoplo, AMOPLO_IV, iv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) ctl->dirty.bf.amoplo = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static int amixer_set_x(void *blk, unsigned int x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) struct amixer_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) set_field(&ctl->amoplo, AMOPLO_X, x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) ctl->dirty.bf.amoplo = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static int amixer_set_y(void *blk, unsigned int y)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) struct amixer_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) set_field(&ctl->amoplo, AMOPLO_Y, y);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) ctl->dirty.bf.amoplo = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static int amixer_set_sadr(void *blk, unsigned int sadr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) struct amixer_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) set_field(&ctl->amophi, AMOPHI_SADR, sadr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) ctl->dirty.bf.amophi = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static int amixer_set_se(void *blk, unsigned int se)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) struct amixer_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) set_field(&ctl->amophi, AMOPHI_SE, se);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) ctl->dirty.bf.amophi = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static int amixer_set_dirty(void *blk, unsigned int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static int amixer_set_dirty_all(void *blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) static int amixer_commit_write(struct hw *hw, unsigned int idx, void *blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) struct amixer_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (ctl->dirty.bf.amoplo || ctl->dirty.bf.amophi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) hw_write_20kx(hw, MIXER_AMOPLO+idx*8, ctl->amoplo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) ctl->dirty.bf.amoplo = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) hw_write_20kx(hw, MIXER_AMOPHI+idx*8, ctl->amophi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) ctl->dirty.bf.amophi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static int amixer_get_y(void *blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) struct amixer_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return get_field(ctl->amoplo, AMOPLO_Y);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) static unsigned int amixer_get_dirty(void *blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static int amixer_rsc_get_ctrl_blk(void **rblk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) struct amixer_rsc_ctrl_blk *blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) *rblk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) blk = kzalloc(sizeof(*blk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (!blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) *rblk = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static int amixer_rsc_put_ctrl_blk(void *blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) kfree(blk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static int amixer_mgr_get_ctrl_blk(void **rblk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) *rblk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) static int amixer_mgr_put_ctrl_blk(void *blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) * DAIO control block definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /* Receiver Sample Rate Tracker Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define SRTCTL_SRCO 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define SRTCTL_SRCM 0x0000FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define SRTCTL_RSR 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define SRTCTL_DRAT 0x00300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define SRTCTL_EC 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define SRTCTL_ET 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /* DAIO Receiver register dirty flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) union dai_dirty {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) u16 srt:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) u16 rsv:15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) } bf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) u16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) /* DAIO Receiver control block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct dai_ctrl_blk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) unsigned int srt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) union dai_dirty dirty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /* Audio Input Mapper RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define AIM_ARC 0x00000FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define AIM_NXT 0x007F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) struct daoimap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) unsigned int aim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) /* Audio Transmitter Control and Status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define ATXCTL_EN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define ATXCTL_MODE 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define ATXCTL_CD 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define ATXCTL_RAW 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define ATXCTL_MT 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define ATXCTL_NUC 0x00003000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define ATXCTL_BEN 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define ATXCTL_BMUX 0x00700000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define ATXCTL_B24 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define ATXCTL_CPF 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define ATXCTL_RIV 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define ATXCTL_LIV 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define ATXCTL_RSAT 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define ATXCTL_LSAT 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /* XDIF Transmitter register dirty flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) union dao_dirty {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) u16 atxcsl:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) u16 rsv:15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) } bf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) u16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /* XDIF Transmitter control block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) struct dao_ctrl_blk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /* XDIF Transmitter Channel Status Low Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) unsigned int atxcsl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) union dao_dirty dirty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) /* Audio Receiver Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define ARXCTL_EN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) /* DAIO manager register dirty flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) union daio_mgr_dirty {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) u32 atxctl:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) u32 arxctl:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) u32 daoimap:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) u32 rsv:15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) } bf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) /* DAIO manager control block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) struct daio_mgr_ctrl_blk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) struct daoimap daoimap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) unsigned int txctl[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) unsigned int rxctl[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) union daio_mgr_dirty dirty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static int dai_srt_set_srco(void *blk, unsigned int src)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) struct dai_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) set_field(&ctl->srt, SRTCTL_SRCO, src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) ctl->dirty.bf.srt = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) static int dai_srt_set_srcm(void *blk, unsigned int src)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) struct dai_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) set_field(&ctl->srt, SRTCTL_SRCM, src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) ctl->dirty.bf.srt = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) static int dai_srt_set_rsr(void *blk, unsigned int rsr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) struct dai_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) set_field(&ctl->srt, SRTCTL_RSR, rsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) ctl->dirty.bf.srt = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) static int dai_srt_set_drat(void *blk, unsigned int drat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) struct dai_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) set_field(&ctl->srt, SRTCTL_DRAT, drat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) ctl->dirty.bf.srt = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) static int dai_srt_set_ec(void *blk, unsigned int ec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) struct dai_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) set_field(&ctl->srt, SRTCTL_EC, ec ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) ctl->dirty.bf.srt = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static int dai_srt_set_et(void *blk, unsigned int et)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) struct dai_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) set_field(&ctl->srt, SRTCTL_ET, et ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) ctl->dirty.bf.srt = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static int dai_commit_write(struct hw *hw, unsigned int idx, void *blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) struct dai_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (ctl->dirty.bf.srt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) hw_write_20kx(hw, AUDIO_IO_RX_SRT_CTL+0x40*idx, ctl->srt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) ctl->dirty.bf.srt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) static int dai_get_ctrl_blk(void **rblk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) struct dai_ctrl_blk *blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) *rblk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) blk = kzalloc(sizeof(*blk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (!blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) *rblk = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) static int dai_put_ctrl_blk(void *blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) kfree(blk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) static int dao_set_spos(void *blk, unsigned int spos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) ((struct dao_ctrl_blk *)blk)->atxcsl = spos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) ((struct dao_ctrl_blk *)blk)->dirty.bf.atxcsl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) static int dao_commit_write(struct hw *hw, unsigned int idx, void *blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) struct dao_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if (ctl->dirty.bf.atxcsl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) if (idx < 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) /* S/PDIF SPOSx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_L+0x40*idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) ctl->atxcsl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) ctl->dirty.bf.atxcsl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) static int dao_get_spos(void *blk, unsigned int *spos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) *spos = ((struct dao_ctrl_blk *)blk)->atxcsl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) static int dao_get_ctrl_blk(void **rblk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) struct dao_ctrl_blk *blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) *rblk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) blk = kzalloc(sizeof(*blk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) if (!blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) *rblk = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) static int dao_put_ctrl_blk(void *blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) kfree(blk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) static int daio_mgr_enb_dai(void *blk, unsigned int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) struct daio_mgr_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) set_field(&ctl->rxctl[idx], ARXCTL_EN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) ctl->dirty.bf.arxctl |= (0x1 << idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) static int daio_mgr_dsb_dai(void *blk, unsigned int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) struct daio_mgr_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) set_field(&ctl->rxctl[idx], ARXCTL_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) ctl->dirty.bf.arxctl |= (0x1 << idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) static int daio_mgr_enb_dao(void *blk, unsigned int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) struct daio_mgr_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) set_field(&ctl->txctl[idx], ATXCTL_EN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) ctl->dirty.bf.atxctl |= (0x1 << idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) static int daio_mgr_dsb_dao(void *blk, unsigned int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) struct daio_mgr_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) set_field(&ctl->txctl[idx], ATXCTL_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) ctl->dirty.bf.atxctl |= (0x1 << idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) static int daio_mgr_dao_init(void *blk, unsigned int idx, unsigned int conf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) struct daio_mgr_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (idx < 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) /* S/PDIF output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) switch ((conf & 0xf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) set_field(&ctl->txctl[idx], ATXCTL_NUC, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) set_field(&ctl->txctl[idx], ATXCTL_NUC, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) set_field(&ctl->txctl[idx], ATXCTL_NUC, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) set_field(&ctl->txctl[idx], ATXCTL_NUC, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) /* CDIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) set_field(&ctl->txctl[idx], ATXCTL_CD, (!(conf & 0x7)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) /* Non-audio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) set_field(&ctl->txctl[idx], ATXCTL_LIV, (conf >> 4) & 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) /* Non-audio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) set_field(&ctl->txctl[idx], ATXCTL_RIV, (conf >> 4) & 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) set_field(&ctl->txctl[idx], ATXCTL_RAW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) ((conf >> 3) & 0x1) ? 0 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) ctl->dirty.bf.atxctl |= (0x1 << idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) /* I2S output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) /*idx %= 4; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) static int daio_mgr_set_imaparc(void *blk, unsigned int slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) struct daio_mgr_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) set_field(&ctl->daoimap.aim, AIM_ARC, slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) ctl->dirty.bf.daoimap = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) static int daio_mgr_set_imapnxt(void *blk, unsigned int next)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) struct daio_mgr_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) set_field(&ctl->daoimap.aim, AIM_NXT, next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) ctl->dirty.bf.daoimap = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) static int daio_mgr_set_imapaddr(void *blk, unsigned int addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) ((struct daio_mgr_ctrl_blk *)blk)->daoimap.idx = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) ((struct daio_mgr_ctrl_blk *)blk)->dirty.bf.daoimap = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) static int daio_mgr_commit_write(struct hw *hw, void *blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) struct daio_mgr_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) unsigned int data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) if ((ctl->dirty.bf.atxctl & (0x1 << i))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) data = ctl->txctl[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) hw_write_20kx(hw, (AUDIO_IO_TX_CTL+(0x40*i)), data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) ctl->dirty.bf.atxctl &= ~(0x1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) if ((ctl->dirty.bf.arxctl & (0x1 << i))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) data = ctl->rxctl[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) hw_write_20kx(hw, (AUDIO_IO_RX_CTL+(0x40*i)), data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) ctl->dirty.bf.arxctl &= ~(0x1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) if (ctl->dirty.bf.daoimap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) hw_write_20kx(hw, AUDIO_IO_AIM+ctl->daoimap.idx*4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) ctl->daoimap.aim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) ctl->dirty.bf.daoimap = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) static int daio_mgr_get_ctrl_blk(struct hw *hw, void **rblk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) struct daio_mgr_ctrl_blk *blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) *rblk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) blk = kzalloc(sizeof(*blk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if (!blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) blk->txctl[i] = hw_read_20kx(hw, AUDIO_IO_TX_CTL+(0x40*i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) blk->rxctl[i] = hw_read_20kx(hw, AUDIO_IO_RX_CTL+(0x40*i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) *rblk = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) static int daio_mgr_put_ctrl_blk(void *blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) kfree(blk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) /* Timer interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) static int set_timer_irq(struct hw *hw, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) hw_write_20kx(hw, GIE, enable ? IT_INT : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) static int set_timer_tick(struct hw *hw, unsigned int ticks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) if (ticks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) ticks |= TIMR_IE | TIMR_IP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) hw_write_20kx(hw, TIMR, ticks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) static unsigned int get_wc(struct hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) return hw_read_20kx(hw, WC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) /* Card hardware initialization block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) struct dac_conf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) unsigned int msr; /* master sample rate in rsrs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) struct adc_conf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) unsigned int msr; /* master sample rate in rsrs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) unsigned char input; /* the input source of ADC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) unsigned char mic20db; /* boost mic by 20db if input is microphone */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) struct daio_conf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) unsigned int msr; /* master sample rate in rsrs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) struct trn_conf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) unsigned long vm_pgt_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) static int hw_daio_init(struct hw *hw, const struct daio_conf *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) /* Program I2S with proper sample rate and enable the correct I2S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) * channel. ED(0/8/16/24): Enable all I2S/I2X master clock output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) if (1 == info->msr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) hw_write_20kx(hw, AUDIO_IO_MCLK, 0x01010101);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x01010101);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) } else if (2 == info->msr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) if (hw->model != CTSB1270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) hw_write_20kx(hw, AUDIO_IO_MCLK, 0x11111111);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) /* PCM4220 on Titanium HD is different. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) hw_write_20kx(hw, AUDIO_IO_MCLK, 0x11011111);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) /* Specify all playing 96khz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) * EA [0] - Enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) * RTA [4:5] - 96kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) * EB [8] - Enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) * RTB [12:13] - 96kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) * EC [16] - Enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) * RTC [20:21] - 96kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) * ED [24] - Enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) * RTD [28:29] - 96kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x11111111);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) } else if ((4 == info->msr) && (hw->model == CTSB1270)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) hw_write_20kx(hw, AUDIO_IO_MCLK, 0x21011111);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x21212121);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) dev_alert(hw->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) "ERROR!!! Invalid sampling rate!!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (i <= 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) /* This comment looks wrong since loop is over 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) /* channels and emu20k2 supports 4 spdif IOs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) /* 1st 3 channels are SPDIFs (SB0960) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) if (i == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) data = 0x1001001;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) data = 0x1000001;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) hw_write_20kx(hw, (AUDIO_IO_TX_CTL+(0x40*i)), data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) hw_write_20kx(hw, (AUDIO_IO_RX_CTL+(0x40*i)), data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) /* Initialize the SPDIF Out Channel status registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) * The value specified here is based on the typical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) * values provided in the specification, namely: Clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) * Accuracy of 1000ppm, Sample Rate of 48KHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) * unspecified source number, Generation status = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) * Category code = 0x12 (Digital Signal Mixer),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) * Mode = 0, Emph = 0, Copy Permitted, AN = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) * (indicating that we're transmitting digital audio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) * and the Professional Use bit is 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_L+(0x40*i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) 0x02109204); /* Default to 48kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_H+(0x40*i), 0x0B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) /* Again, loop is over 4 channels not 5. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) /* Next 5 channels are I2S (SB0960) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) data = 0x11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) hw_write_20kx(hw, AUDIO_IO_RX_CTL+(0x40*i), data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) if (2 == info->msr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) /* Four channels per sample period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) data |= 0x1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) } else if (4 == info->msr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) /* FIXME: check this against the chip spec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) data |= 0x2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) hw_write_20kx(hw, AUDIO_IO_TX_CTL+(0x40*i), data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) /* TRANSPORT operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) static int hw_trn_init(struct hw *hw, const struct trn_conf *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) u32 vmctl, data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) u32 ptp_phys_low, ptp_phys_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) /* Set up device page table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) if ((~0UL) == info->vm_pgt_phys) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) dev_alert(hw->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) "Wrong device page table page address!!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) vmctl = 0x80000C0F; /* 32-bit, 4k-size page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) ptp_phys_low = (u32)info->vm_pgt_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) ptp_phys_high = upper_32_bits(info->vm_pgt_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) if (sizeof(void *) == 8) /* 64bit address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) vmctl |= (3 << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) /* Write page table physical address to all PTPAL registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) for (i = 0; i < 64; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) hw_write_20kx(hw, VMEM_PTPAL+(16*i), ptp_phys_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) hw_write_20kx(hw, VMEM_PTPAH+(16*i), ptp_phys_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) /* Enable virtual memory transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) hw_write_20kx(hw, VMEM_CTL, vmctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) /* Enable transport bus master and queueing of request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) hw_write_20kx(hw, TRANSPORT_CTL, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) hw_write_20kx(hw, TRANSPORT_INT, 0x200c01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) /* Enable transport ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) data = hw_read_20kx(hw, TRANSPORT_ENB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) hw_write_20kx(hw, TRANSPORT_ENB, (data | 0x03));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) /* Card initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) #define GCTL_AIE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) #define GCTL_UAA 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) #define GCTL_DPC 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) #define GCTL_DBP 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) #define GCTL_ABP 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) #define GCTL_TBP 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) #define GCTL_SBP 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) #define GCTL_FBP 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) #define GCTL_ME 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) #define GCTL_AID 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) #define PLLCTL_SRC 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) #define PLLCTL_SPE 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) #define PLLCTL_RD 0x000000F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) #define PLLCTL_FD 0x0001FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) #define PLLCTL_OD 0x00060000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) #define PLLCTL_B 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) #define PLLCTL_AS 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) #define PLLCTL_LF 0x03E00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) #define PLLCTL_SPS 0x1C000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) #define PLLCTL_AD 0x60000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) #define PLLSTAT_CCS 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) #define PLLSTAT_SPL 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) #define PLLSTAT_CRD 0x000000F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) #define PLLSTAT_CFD 0x0001FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) #define PLLSTAT_SL 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) #define PLLSTAT_FAS 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) #define PLLSTAT_B 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) #define PLLSTAT_PD 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) #define PLLSTAT_OCA 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) #define PLLSTAT_NCA 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) static int hw_pll_init(struct hw *hw, unsigned int rsr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) unsigned int pllenb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) unsigned int pllctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) unsigned int pllstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) pllenb = 0xB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) hw_write_20kx(hw, PLL_ENB, pllenb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) pllctl = 0x20C00000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) set_field(&pllctl, PLLCTL_B, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) set_field(&pllctl, PLLCTL_FD, 48000 == rsr ? 16 - 4 : 147 - 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) set_field(&pllctl, PLLCTL_RD, 48000 == rsr ? 1 - 1 : 10 - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) hw_write_20kx(hw, PLL_CTL, pllctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) msleep(40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) pllctl = hw_read_20kx(hw, PLL_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) set_field(&pllctl, PLLCTL_FD, 48000 == rsr ? 16 - 2 : 147 - 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) hw_write_20kx(hw, PLL_CTL, pllctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) msleep(40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) for (i = 0; i < 1000; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) pllstat = hw_read_20kx(hw, PLL_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) if (get_field(pllstat, PLLSTAT_PD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) if (get_field(pllstat, PLLSTAT_B) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) get_field(pllctl, PLLCTL_B))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) if (get_field(pllstat, PLLSTAT_CCS) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) get_field(pllctl, PLLCTL_SRC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) if (get_field(pllstat, PLLSTAT_CRD) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) get_field(pllctl, PLLCTL_RD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) if (get_field(pllstat, PLLSTAT_CFD) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) get_field(pllctl, PLLCTL_FD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) if (i >= 1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) dev_alert(hw->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) "PLL initialization failed!!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) static int hw_auto_init(struct hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) unsigned int gctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) set_field(&gctl, GCTL_AIE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) set_field(&gctl, GCTL_AIE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) for (i = 0; i < 400000; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) if (get_field(gctl, GCTL_AID))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) if (!get_field(gctl, GCTL_AID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) dev_alert(hw->card->dev, "Card Auto-init failed!!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) /* DAC operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) #define CS4382_MC1 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) #define CS4382_MC2 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) #define CS4382_MC3 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) #define CS4382_FC 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) #define CS4382_IC 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) #define CS4382_XC1 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) #define CS4382_VCA1 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) #define CS4382_VCB1 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) #define CS4382_XC2 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) #define CS4382_VCA2 0xA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) #define CS4382_VCB2 0xB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) #define CS4382_XC3 0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) #define CS4382_VCA3 0xD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) #define CS4382_VCB3 0xE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) #define CS4382_XC4 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) #define CS4382_VCA4 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) #define CS4382_VCB4 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) #define CS4382_CREV 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) /* I2C status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) #define STATE_LOCKED 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) #define STATE_UNLOCKED 0xAA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) #define DATA_READY 0x800000 /* Used with I2C_IF_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) #define DATA_ABORT 0x10000 /* Used with I2C_IF_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) #define I2C_STATUS_DCM 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) #define I2C_STATUS_BC 0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) #define I2C_STATUS_APD 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) #define I2C_STATUS_AB 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) #define I2C_STATUS_DR 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) #define I2C_ADDRESS_PTAD 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) #define I2C_ADDRESS_SLAD 0x007F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) struct regs_cs4382 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) u32 mode_control_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) u32 mode_control_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) u32 mode_control_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) u32 filter_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) u32 invert_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) u32 mix_control_P1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) u32 vol_control_A1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) u32 vol_control_B1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) u32 mix_control_P2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) u32 vol_control_A2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) u32 vol_control_B2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) u32 mix_control_P3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) u32 vol_control_A3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) u32 vol_control_B3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) u32 mix_control_P4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) u32 vol_control_A4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) u32 vol_control_B4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) static int hw20k2_i2c_unlock_full_access(struct hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) u8 UnlockKeySequence_FLASH_FULLACCESS_MODE[2] = {0xB3, 0xD4};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) /* Send keys for forced BIOS mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) hw_write_20kx(hw, I2C_IF_WLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) UnlockKeySequence_FLASH_FULLACCESS_MODE[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) hw_write_20kx(hw, I2C_IF_WLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) UnlockKeySequence_FLASH_FULLACCESS_MODE[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) /* Check whether the chip is unlocked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) if (hw_read_20kx(hw, I2C_IF_WLOCK) == STATE_UNLOCKED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) static int hw20k2_i2c_lock_chip(struct hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) /* Write twice */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) hw_write_20kx(hw, I2C_IF_WLOCK, STATE_LOCKED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) hw_write_20kx(hw, I2C_IF_WLOCK, STATE_LOCKED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) if (hw_read_20kx(hw, I2C_IF_WLOCK) == STATE_LOCKED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) static int hw20k2_i2c_init(struct hw *hw, u8 dev_id, u8 addr_size, u8 data_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) struct hw20k2 *hw20k2 = (struct hw20k2 *)hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) unsigned int i2c_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) unsigned int i2c_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) err = hw20k2_i2c_unlock_full_access(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) hw20k2->addr_size = addr_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) hw20k2->data_size = data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) hw20k2->dev_id = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) i2c_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) set_field(&i2c_addr, I2C_ADDRESS_SLAD, dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) hw_write_20kx(hw, I2C_IF_ADDRESS, i2c_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) i2c_status = hw_read_20kx(hw, I2C_IF_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) set_field(&i2c_status, I2C_STATUS_DCM, 1); /* Direct control mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) hw_write_20kx(hw, I2C_IF_STATUS, i2c_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) static int hw20k2_i2c_uninit(struct hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) unsigned int i2c_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) unsigned int i2c_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) i2c_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) set_field(&i2c_addr, I2C_ADDRESS_SLAD, 0x57); /* I2C id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) hw_write_20kx(hw, I2C_IF_ADDRESS, i2c_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) i2c_status = hw_read_20kx(hw, I2C_IF_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) set_field(&i2c_status, I2C_STATUS_DCM, 0); /* I2C mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) hw_write_20kx(hw, I2C_IF_STATUS, i2c_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) return hw20k2_i2c_lock_chip(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) static int hw20k2_i2c_wait_data_ready(struct hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) int i = 0x400000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) unsigned int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) ret = hw_read_20kx(hw, I2C_IF_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) } while ((!(ret & DATA_READY)) && --i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) static int hw20k2_i2c_read(struct hw *hw, u16 addr, u32 *datap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) struct hw20k2 *hw20k2 = (struct hw20k2 *)hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) unsigned int i2c_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) i2c_status = hw_read_20kx(hw, I2C_IF_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) set_field(&i2c_status, I2C_STATUS_BC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) (4 == hw20k2->addr_size) ? 0 : hw20k2->addr_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) hw_write_20kx(hw, I2C_IF_STATUS, i2c_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) if (!hw20k2_i2c_wait_data_ready(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) hw_write_20kx(hw, I2C_IF_WDATA, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) if (!hw20k2_i2c_wait_data_ready(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) /* Force a read operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) hw_write_20kx(hw, I2C_IF_RDATA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) if (!hw20k2_i2c_wait_data_ready(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) *datap = hw_read_20kx(hw, I2C_IF_RDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) static int hw20k2_i2c_write(struct hw *hw, u16 addr, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) struct hw20k2 *hw20k2 = (struct hw20k2 *)hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) unsigned int i2c_data = (data << (hw20k2->addr_size * 8)) | addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) unsigned int i2c_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) i2c_status = hw_read_20kx(hw, I2C_IF_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) set_field(&i2c_status, I2C_STATUS_BC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) (4 == (hw20k2->addr_size + hw20k2->data_size)) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) 0 : (hw20k2->addr_size + hw20k2->data_size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) hw_write_20kx(hw, I2C_IF_STATUS, i2c_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) hw20k2_i2c_wait_data_ready(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) /* Dummy write to trigger the write operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) hw_write_20kx(hw, I2C_IF_WDATA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) hw20k2_i2c_wait_data_ready(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) /* This is the real data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) hw_write_20kx(hw, I2C_IF_WDATA, i2c_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) hw20k2_i2c_wait_data_ready(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) static void hw_dac_stop(struct hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) data = hw_read_20kx(hw, GPIO_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) data &= 0xFFFFFFFD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) hw_write_20kx(hw, GPIO_DATA, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) usleep_range(10000, 11000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) static void hw_dac_start(struct hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) data = hw_read_20kx(hw, GPIO_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) data |= 0x2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) hw_write_20kx(hw, GPIO_DATA, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) static void hw_dac_reset(struct hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) hw_dac_stop(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) hw_dac_start(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) static int hw_dac_init(struct hw *hw, const struct dac_conf *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) struct regs_cs4382 cs_read = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) struct regs_cs4382 cs_def = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) .mode_control_1 = 0x00000001, /* Mode Control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) .mode_control_2 = 0x00000000, /* Mode Control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) .mode_control_3 = 0x00000084, /* Mode Control 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) .filter_control = 0x00000000, /* Filter Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) .invert_control = 0x00000000, /* Invert Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) .mix_control_P1 = 0x00000024, /* Mixing Control Pair 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) .vol_control_A1 = 0x00000000, /* Vol Control A1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) .vol_control_B1 = 0x00000000, /* Vol Control B1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) .mix_control_P2 = 0x00000024, /* Mixing Control Pair 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) .vol_control_A2 = 0x00000000, /* Vol Control A2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) .vol_control_B2 = 0x00000000, /* Vol Control B2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) .mix_control_P3 = 0x00000024, /* Mixing Control Pair 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) .vol_control_A3 = 0x00000000, /* Vol Control A3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) .vol_control_B3 = 0x00000000, /* Vol Control B3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) .mix_control_P4 = 0x00000024, /* Mixing Control Pair 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) .vol_control_A4 = 0x00000000, /* Vol Control A4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) .vol_control_B4 = 0x00000000 /* Vol Control B4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) if (hw->model == CTSB1270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) hw_dac_stop(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) data = hw_read_20kx(hw, GPIO_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) data &= ~0x0600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) if (1 == info->msr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) data |= 0x0000; /* Single Speed Mode 0-50kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) else if (2 == info->msr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) data |= 0x0200; /* Double Speed Mode 50-100kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) data |= 0x0600; /* Quad Speed Mode 100-200kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) hw_write_20kx(hw, GPIO_DATA, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) hw_dac_start(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) /* Set DAC reset bit as output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) data = hw_read_20kx(hw, GPIO_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) data |= 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) hw_write_20kx(hw, GPIO_CTRL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) err = hw20k2_i2c_init(hw, 0x18, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) goto End;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) /* Reset DAC twice just in-case the chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) * didn't initialized properly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) hw_dac_reset(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) hw_dac_reset(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) if (hw20k2_i2c_read(hw, CS4382_MC1, &cs_read.mode_control_1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) if (hw20k2_i2c_read(hw, CS4382_MC2, &cs_read.mode_control_2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) if (hw20k2_i2c_read(hw, CS4382_MC3, &cs_read.mode_control_3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) if (hw20k2_i2c_read(hw, CS4382_FC, &cs_read.filter_control))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) if (hw20k2_i2c_read(hw, CS4382_IC, &cs_read.invert_control))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) if (hw20k2_i2c_read(hw, CS4382_XC1, &cs_read.mix_control_P1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) if (hw20k2_i2c_read(hw, CS4382_VCA1, &cs_read.vol_control_A1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) if (hw20k2_i2c_read(hw, CS4382_VCB1, &cs_read.vol_control_B1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) if (hw20k2_i2c_read(hw, CS4382_XC2, &cs_read.mix_control_P2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) if (hw20k2_i2c_read(hw, CS4382_VCA2, &cs_read.vol_control_A2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) if (hw20k2_i2c_read(hw, CS4382_VCB2, &cs_read.vol_control_B2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) if (hw20k2_i2c_read(hw, CS4382_XC3, &cs_read.mix_control_P3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) if (hw20k2_i2c_read(hw, CS4382_VCA3, &cs_read.vol_control_A3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) if (hw20k2_i2c_read(hw, CS4382_VCB3, &cs_read.vol_control_B3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) if (hw20k2_i2c_read(hw, CS4382_XC4, &cs_read.mix_control_P4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) if (hw20k2_i2c_read(hw, CS4382_VCA4, &cs_read.vol_control_A4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) if (hw20k2_i2c_read(hw, CS4382_VCB4, &cs_read.vol_control_B4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) if (memcmp(&cs_read, &cs_def, sizeof(cs_read)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) if (i >= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) goto End;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) /* Note: Every I2C write must have some delay.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) * This is not a requirement but the delay works here... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) hw20k2_i2c_write(hw, CS4382_MC1, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) hw20k2_i2c_write(hw, CS4382_MC2, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) if (1 == info->msr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) hw20k2_i2c_write(hw, CS4382_XC1, 0x24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) hw20k2_i2c_write(hw, CS4382_XC2, 0x24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) hw20k2_i2c_write(hw, CS4382_XC3, 0x24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) hw20k2_i2c_write(hw, CS4382_XC4, 0x24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) } else if (2 == info->msr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) hw20k2_i2c_write(hw, CS4382_XC1, 0x25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) hw20k2_i2c_write(hw, CS4382_XC2, 0x25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) hw20k2_i2c_write(hw, CS4382_XC3, 0x25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) hw20k2_i2c_write(hw, CS4382_XC4, 0x25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) hw20k2_i2c_write(hw, CS4382_XC1, 0x26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) hw20k2_i2c_write(hw, CS4382_XC2, 0x26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) hw20k2_i2c_write(hw, CS4382_XC3, 0x26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) hw20k2_i2c_write(hw, CS4382_XC4, 0x26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) End:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) hw20k2_i2c_uninit(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) /* ADC operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) #define MAKE_WM8775_ADDR(addr, data) (u32)(((addr<<1)&0xFE)|((data>>8)&0x1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) #define MAKE_WM8775_DATA(data) (u32)(data&0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) #define WM8775_IC 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) #define WM8775_MMC 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) #define WM8775_AADCL 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) #define WM8775_AADCR 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) #define WM8775_ADCMC 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) #define WM8775_RESET 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) static int hw_is_adc_input_selected(struct hw *hw, enum ADCSRC type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) if (hw->model == CTSB1270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) /* Titanium HD has two ADC chips, one for line in and one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) /* for MIC. We don't need to switch the ADC input. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) data = hw_read_20kx(hw, GPIO_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) case ADC_MICIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) data = (data & (0x1 << 14)) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) case ADC_LINEIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) data = (data & (0x1 << 14)) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) #define MIC_BOOST_0DB 0xCF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) #define MIC_BOOST_STEPS_PER_DB 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) static void hw_wm8775_input_select(struct hw *hw, u8 input, s8 gain_in_db)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) u32 adcmc, gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) if (input > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) input = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) adcmc = ((u32)1 << input) | 0x100; /* Link L+R gain... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, adcmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) MAKE_WM8775_DATA(adcmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) if (gain_in_db < -103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) gain_in_db = -103;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) if (gain_in_db > 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) gain_in_db = 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) gain = gain_in_db * MIC_BOOST_STEPS_PER_DB + MIC_BOOST_0DB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCL, gain),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) MAKE_WM8775_DATA(gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) /* ...so there should be no need for the following. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCR, gain),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) MAKE_WM8775_DATA(gain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) static int hw_adc_input_select(struct hw *hw, enum ADCSRC type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) data = hw_read_20kx(hw, GPIO_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) case ADC_MICIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) data |= (0x1 << 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) hw_write_20kx(hw, GPIO_DATA, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) hw_wm8775_input_select(hw, 0, 20); /* Mic, 20dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) case ADC_LINEIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) data &= ~(0x1 << 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) hw_write_20kx(hw, GPIO_DATA, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) hw_wm8775_input_select(hw, 1, 0); /* Line-in, 0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) static int hw_adc_init(struct hw *hw, const struct adc_conf *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) u32 data, ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) /* Set ADC reset bit as output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) data = hw_read_20kx(hw, GPIO_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) data |= (0x1 << 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) hw_write_20kx(hw, GPIO_CTRL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) /* Initialize I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) err = hw20k2_i2c_init(hw, 0x1A, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) dev_alert(hw->card->dev, "Failure to acquire I2C!!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) /* Reset the ADC (reset is active low). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) data = hw_read_20kx(hw, GPIO_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) data &= ~(0x1 << 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) hw_write_20kx(hw, GPIO_DATA, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) if (hw->model == CTSB1270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) /* Set up the PCM4220 ADC on Titanium HD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) data &= ~0x0C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) if (1 == info->msr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) data |= 0x00; /* Single Speed Mode 32-50kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) else if (2 == info->msr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) data |= 0x08; /* Double Speed Mode 50-108kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) data |= 0x04; /* Quad Speed Mode 108kHz-216kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) hw_write_20kx(hw, GPIO_DATA, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) usleep_range(10000, 11000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) /* Return the ADC to normal operation. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) data |= (0x1 << 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) hw_write_20kx(hw, GPIO_DATA, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) /* I2C write to register offset 0x0B to set ADC LRCLK polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) /* invert bit, interface format to I2S, word length to 24-bit, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) /* enable ADC high pass filter. Fixes bug 5323? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_IC, 0x26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) MAKE_WM8775_DATA(0x26));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) /* Set the master mode (256fs) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) if (1 == info->msr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) /* slave mode, 128x oversampling 256fs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) MAKE_WM8775_DATA(0x02));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) } else if ((2 == info->msr) || (4 == info->msr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) /* slave mode, 64x oversampling, 256fs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x0A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) MAKE_WM8775_DATA(0x0A));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) dev_alert(hw->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) "Invalid master sampling rate (msr %d)!!!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) info->msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) if (hw->model != CTSB1270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) /* Configure GPIO bit 14 change to line-in/mic-in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) ctl = hw_read_20kx(hw, GPIO_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) ctl |= 0x1 << 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) hw_write_20kx(hw, GPIO_CTRL, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) hw_adc_input_select(hw, ADC_LINEIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) hw_wm8775_input_select(hw, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) hw20k2_i2c_uninit(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) static struct capabilities hw_capabilities(struct hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) struct capabilities cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) cap.digit_io_switch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) cap.dedicated_mic = hw->model == CTSB1270;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) cap.output_switch = hw->model == CTSB1270;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) cap.mic_source_switch = hw->model == CTSB1270;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) return cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) static int hw_output_switch_get(struct hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) u32 data = hw_read_20kx(hw, GPIO_EXT_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) switch (data & 0x30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) case 0x00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) case 0x10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) case 0x20:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) return 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) static int hw_output_switch_put(struct hw *hw, int position)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) if (position == hw_output_switch_get(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) /* Mute line and headphones (intended for anti-pop). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) data = hw_read_20kx(hw, GPIO_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) data |= (0x03 << 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) hw_write_20kx(hw, GPIO_DATA, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) data = hw_read_20kx(hw, GPIO_EXT_DATA) & ~0x30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) switch (position) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) data |= 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) data |= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) hw_write_20kx(hw, GPIO_EXT_DATA, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) /* Unmute line and headphones. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) data = hw_read_20kx(hw, GPIO_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) data &= ~(0x03 << 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) hw_write_20kx(hw, GPIO_DATA, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) static int hw_mic_source_switch_get(struct hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) struct hw20k2 *hw20k2 = (struct hw20k2 *)hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) return hw20k2->mic_source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) static int hw_mic_source_switch_put(struct hw *hw, int position)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) struct hw20k2 *hw20k2 = (struct hw20k2 *)hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) if (position == hw20k2->mic_source)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) switch (position) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) hw_wm8775_input_select(hw, 0, 0); /* Mic, 0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) hw_wm8775_input_select(hw, 1, 0); /* FP Mic, 0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) hw_wm8775_input_select(hw, 3, 0); /* Aux Ext, 0dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) hw20k2->mic_source = position;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) static irqreturn_t ct_20k2_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) struct hw *hw = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) status = hw_read_20kx(hw, GIP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) if (!status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) if (hw->irq_callback)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) hw->irq_callback(hw->irq_callback_data, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) hw_write_20kx(hw, GIP, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) static int hw_card_start(struct hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) struct pci_dev *pci = hw->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) unsigned int gctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) const unsigned int dma_bits = BITS_PER_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) err = pci_enable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) /* Set DMA transfer mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) if (!hw->io_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) err = pci_request_regions(pci, "XFi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) goto error1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) hw->io_base = pci_resource_start(hw->pci, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) hw->mem_base = ioremap(hw->io_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) pci_resource_len(hw->pci, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) if (!hw->mem_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) err = -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) goto error2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) /* Switch to 20k2 mode from UAA mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) set_field(&gctl, GCTL_UAA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) if (hw->irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) err = request_irq(pci->irq, ct_20k2_interrupt, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) KBUILD_MODNAME, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) dev_err(hw->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) "XFi: Cannot get irq %d\n", pci->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) goto error2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) hw->irq = pci->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) hw->card->sync_irq = hw->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) pci_set_master(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) /*error3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) iounmap((void *)hw->mem_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) hw->mem_base = (unsigned long)NULL;*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) error2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) pci_release_regions(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) hw->io_base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) error1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) static int hw_card_stop(struct hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) unsigned int data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) /* disable transport bus master and queueing of request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) hw_write_20kx(hw, TRANSPORT_CTL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) /* disable pll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) data = hw_read_20kx(hw, PLL_ENB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) hw_write_20kx(hw, PLL_ENB, (data & (~0x07)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) /* TODO: Disable interrupt and so on... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) static int hw_card_shutdown(struct hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) if (hw->irq >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) free_irq(hw->irq, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) hw->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) iounmap(hw->mem_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) hw->mem_base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) if (hw->io_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) pci_release_regions(hw->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) hw->io_base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) pci_disable_device(hw->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) static int hw_card_init(struct hw *hw, struct card_conf *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) unsigned int gctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) u32 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) struct dac_conf dac_info = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) struct adc_conf adc_info = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) struct daio_conf daio_info = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) struct trn_conf trn_info = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) /* Get PCI io port/memory base address and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) * do 20kx core switch if needed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) err = hw_card_start(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) /* PLL init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) err = hw_pll_init(hw, info->rsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) /* kick off auto-init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) err = hw_auto_init(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) set_field(&gctl, GCTL_DBP, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) set_field(&gctl, GCTL_TBP, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) set_field(&gctl, GCTL_FBP, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) set_field(&gctl, GCTL_DPC, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) /* Reset all global pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) hw_write_20kx(hw, GIE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) /* Reset all SRC pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) hw_write_20kx(hw, SRC_IP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) if (hw->model != CTSB1270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) /* TODO: detect the card ID and configure GPIO accordingly. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) /* Configures GPIO (0xD802 0x98028) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) /*hw_write_20kx(hw, GPIO_CTRL, 0x7F07);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) /* Configures GPIO (SB0880) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) /*hw_write_20kx(hw, GPIO_CTRL, 0xFF07);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) hw_write_20kx(hw, GPIO_CTRL, 0xD802);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) hw_write_20kx(hw, GPIO_CTRL, 0x9E5F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) /* Enable audio ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) hw_write_20kx(hw, MIXER_AR_ENABLE, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) trn_info.vm_pgt_phys = info->vm_pgt_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) err = hw_trn_init(hw, &trn_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) daio_info.msr = info->msr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) err = hw_daio_init(hw, &daio_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) dac_info.msr = info->msr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) err = hw_dac_init(hw, &dac_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) adc_info.msr = info->msr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) adc_info.input = ADC_LINEIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) adc_info.mic20db = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) err = hw_adc_init(hw, &adc_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) data = hw_read_20kx(hw, SRC_MCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) data |= 0x1; /* Enables input from the audio ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) hw_write_20kx(hw, SRC_MCTL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) static int hw_suspend(struct hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) hw_card_stop(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) static int hw_resume(struct hw *hw, struct card_conf *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) /* Re-initialize card hardware. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) return hw_card_init(hw, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) static u32 hw_read_20kx(struct hw *hw, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) return readl(hw->mem_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) static void hw_write_20kx(struct hw *hw, u32 reg, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) writel(data, hw->mem_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) static const struct hw ct20k2_preset = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) .irq = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) .card_init = hw_card_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) .card_stop = hw_card_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) .pll_init = hw_pll_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) .is_adc_source_selected = hw_is_adc_input_selected,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) .select_adc_source = hw_adc_input_select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) .capabilities = hw_capabilities,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) .output_switch_get = hw_output_switch_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) .output_switch_put = hw_output_switch_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) .mic_source_switch_get = hw_mic_source_switch_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) .mic_source_switch_put = hw_mic_source_switch_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) .suspend = hw_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) .resume = hw_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) .src_rsc_get_ctrl_blk = src_get_rsc_ctrl_blk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) .src_rsc_put_ctrl_blk = src_put_rsc_ctrl_blk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) .src_mgr_get_ctrl_blk = src_mgr_get_ctrl_blk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) .src_mgr_put_ctrl_blk = src_mgr_put_ctrl_blk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) .src_set_state = src_set_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) .src_set_bm = src_set_bm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) .src_set_rsr = src_set_rsr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) .src_set_sf = src_set_sf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) .src_set_wr = src_set_wr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) .src_set_pm = src_set_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) .src_set_rom = src_set_rom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) .src_set_vo = src_set_vo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) .src_set_st = src_set_st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) .src_set_ie = src_set_ie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) .src_set_ilsz = src_set_ilsz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) .src_set_bp = src_set_bp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) .src_set_cisz = src_set_cisz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) .src_set_ca = src_set_ca,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) .src_set_sa = src_set_sa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) .src_set_la = src_set_la,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) .src_set_pitch = src_set_pitch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) .src_set_dirty = src_set_dirty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) .src_set_clear_zbufs = src_set_clear_zbufs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) .src_set_dirty_all = src_set_dirty_all,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) .src_commit_write = src_commit_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) .src_get_ca = src_get_ca,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) .src_get_dirty = src_get_dirty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) .src_dirty_conj_mask = src_dirty_conj_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) .src_mgr_enbs_src = src_mgr_enbs_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) .src_mgr_enb_src = src_mgr_enb_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) .src_mgr_dsb_src = src_mgr_dsb_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) .src_mgr_commit_write = src_mgr_commit_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) .srcimp_mgr_get_ctrl_blk = srcimp_mgr_get_ctrl_blk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) .srcimp_mgr_put_ctrl_blk = srcimp_mgr_put_ctrl_blk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) .srcimp_mgr_set_imaparc = srcimp_mgr_set_imaparc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) .srcimp_mgr_set_imapuser = srcimp_mgr_set_imapuser,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) .srcimp_mgr_set_imapnxt = srcimp_mgr_set_imapnxt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) .srcimp_mgr_set_imapaddr = srcimp_mgr_set_imapaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) .srcimp_mgr_commit_write = srcimp_mgr_commit_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) .amixer_rsc_get_ctrl_blk = amixer_rsc_get_ctrl_blk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) .amixer_rsc_put_ctrl_blk = amixer_rsc_put_ctrl_blk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) .amixer_mgr_get_ctrl_blk = amixer_mgr_get_ctrl_blk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) .amixer_mgr_put_ctrl_blk = amixer_mgr_put_ctrl_blk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) .amixer_set_mode = amixer_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) .amixer_set_iv = amixer_set_iv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) .amixer_set_x = amixer_set_x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) .amixer_set_y = amixer_set_y,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) .amixer_set_sadr = amixer_set_sadr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) .amixer_set_se = amixer_set_se,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) .amixer_set_dirty = amixer_set_dirty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) .amixer_set_dirty_all = amixer_set_dirty_all,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) .amixer_commit_write = amixer_commit_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) .amixer_get_y = amixer_get_y,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) .amixer_get_dirty = amixer_get_dirty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) .dai_get_ctrl_blk = dai_get_ctrl_blk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) .dai_put_ctrl_blk = dai_put_ctrl_blk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) .dai_srt_set_srco = dai_srt_set_srco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) .dai_srt_set_srcm = dai_srt_set_srcm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) .dai_srt_set_rsr = dai_srt_set_rsr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) .dai_srt_set_drat = dai_srt_set_drat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) .dai_srt_set_ec = dai_srt_set_ec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) .dai_srt_set_et = dai_srt_set_et,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) .dai_commit_write = dai_commit_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) .dao_get_ctrl_blk = dao_get_ctrl_blk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) .dao_put_ctrl_blk = dao_put_ctrl_blk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) .dao_set_spos = dao_set_spos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) .dao_commit_write = dao_commit_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) .dao_get_spos = dao_get_spos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) .daio_mgr_get_ctrl_blk = daio_mgr_get_ctrl_blk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) .daio_mgr_put_ctrl_blk = daio_mgr_put_ctrl_blk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) .daio_mgr_enb_dai = daio_mgr_enb_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) .daio_mgr_dsb_dai = daio_mgr_dsb_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) .daio_mgr_enb_dao = daio_mgr_enb_dao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) .daio_mgr_dsb_dao = daio_mgr_dsb_dao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) .daio_mgr_dao_init = daio_mgr_dao_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) .daio_mgr_set_imaparc = daio_mgr_set_imaparc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) .daio_mgr_set_imapnxt = daio_mgr_set_imapnxt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) .daio_mgr_set_imapaddr = daio_mgr_set_imapaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) .daio_mgr_commit_write = daio_mgr_commit_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) .set_timer_irq = set_timer_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) .set_timer_tick = set_timer_tick,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) .get_wc = get_wc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) int create_20k2_hw_obj(struct hw **rhw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) struct hw20k2 *hw20k2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) *rhw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) hw20k2 = kzalloc(sizeof(*hw20k2), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) if (!hw20k2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) hw20k2->hw = ct20k2_preset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) *rhw = &hw20k2->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) int destroy_20k2_hw_obj(struct hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) if (hw->io_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) hw_card_shutdown(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) kfree(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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