^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * @File cthw20k1.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * @Brief
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This file contains the implementation of hardware access methord for 20k1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * @Author Liu Chun
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * @Date Jun 24 2008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "cthw20k1.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "ct20k1reg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct hw20k1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) spinlock_t reg_20k1_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) spinlock_t reg_pci_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static u32 hw_read_20kx(struct hw *hw, u32 reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static void hw_write_20kx(struct hw *hw, u32 reg, u32 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static u32 hw_read_pci(struct hw *hw, u32 reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static void hw_write_pci(struct hw *hw, u32 reg, u32 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Type definition block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * The layout of control structures can be directly applied on 20k2 chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * SRC control block definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* SRC resource control block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SRCCTL_STATE 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SRCCTL_BM 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SRCCTL_RSR 0x00000030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SRCCTL_SF 0x000001C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SRCCTL_WR 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SRCCTL_PM 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SRCCTL_ROM 0x00001800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SRCCTL_VO 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SRCCTL_ST 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SRCCTL_IE 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SRCCTL_ILSZ 0x000F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SRCCTL_BP 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SRCCCR_CISZ 0x000007FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SRCCCR_CWA 0x001FF800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SRCCCR_D 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SRCCCR_RS 0x01C00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SRCCCR_NAL 0x3E000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SRCCCR_RA 0xC0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SRCCA_CA 0x03FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SRCCA_RS 0x1C000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SRCCA_NAL 0xE0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SRCSA_SA 0x03FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SRCLA_LA 0x03FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Mixer Parameter Ring ram Low and Hight register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * Fixed-point value in 8.24 format for parameter channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MPRLH_PITCH 0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* SRC resource register dirty flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) union src_dirty {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u16 ctl:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u16 ccr:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u16 sa:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u16 la:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u16 ca:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u16 mpr:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u16 czbfs:1; /* Clear Z-Buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u16 rsv:9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) } bf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct src_rsc_ctrl_blk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned int ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int ccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned int ca;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned int sa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) unsigned int la;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned int mpr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) union src_dirty dirty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* SRC manager control block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) union src_mgr_dirty {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u16 enb0:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u16 enb1:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u16 enb2:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u16 enb3:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u16 enb4:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u16 enb5:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u16 enb6:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u16 enb7:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u16 enbsa:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u16 rsv:7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) } bf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct src_mgr_ctrl_blk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned int enbsa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) unsigned int enb[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) union src_mgr_dirty dirty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* SRCIMP manager control block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SRCAIM_ARC 0x00000FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SRCAIM_NXT 0x00FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SRCAIM_SRC 0xFF000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct srcimap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned int srcaim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* SRCIMP manager register dirty flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) union srcimp_mgr_dirty {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u16 srcimap:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u16 rsv:15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) } bf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct srcimp_mgr_ctrl_blk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct srcimap srcimap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) union srcimp_mgr_dirty dirty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * Function implementation block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int src_get_rsc_ctrl_blk(void **rblk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct src_rsc_ctrl_blk *blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) *rblk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) blk = kzalloc(sizeof(*blk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (!blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) *rblk = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static int src_put_rsc_ctrl_blk(void *blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) kfree(blk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int src_set_state(void *blk, unsigned int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct src_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) set_field(&ctl->ctl, SRCCTL_STATE, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ctl->dirty.bf.ctl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int src_set_bm(void *blk, unsigned int bm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct src_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) set_field(&ctl->ctl, SRCCTL_BM, bm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ctl->dirty.bf.ctl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int src_set_rsr(void *blk, unsigned int rsr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct src_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) set_field(&ctl->ctl, SRCCTL_RSR, rsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ctl->dirty.bf.ctl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int src_set_sf(void *blk, unsigned int sf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct src_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) set_field(&ctl->ctl, SRCCTL_SF, sf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ctl->dirty.bf.ctl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static int src_set_wr(void *blk, unsigned int wr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct src_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) set_field(&ctl->ctl, SRCCTL_WR, wr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) ctl->dirty.bf.ctl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static int src_set_pm(void *blk, unsigned int pm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct src_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) set_field(&ctl->ctl, SRCCTL_PM, pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ctl->dirty.bf.ctl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int src_set_rom(void *blk, unsigned int rom)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct src_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) set_field(&ctl->ctl, SRCCTL_ROM, rom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ctl->dirty.bf.ctl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static int src_set_vo(void *blk, unsigned int vo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct src_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) set_field(&ctl->ctl, SRCCTL_VO, vo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ctl->dirty.bf.ctl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static int src_set_st(void *blk, unsigned int st)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct src_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) set_field(&ctl->ctl, SRCCTL_ST, st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ctl->dirty.bf.ctl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static int src_set_ie(void *blk, unsigned int ie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct src_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) set_field(&ctl->ctl, SRCCTL_IE, ie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ctl->dirty.bf.ctl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static int src_set_ilsz(void *blk, unsigned int ilsz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct src_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) set_field(&ctl->ctl, SRCCTL_ILSZ, ilsz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) ctl->dirty.bf.ctl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static int src_set_bp(void *blk, unsigned int bp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct src_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) set_field(&ctl->ctl, SRCCTL_BP, bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) ctl->dirty.bf.ctl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static int src_set_cisz(void *blk, unsigned int cisz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct src_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) set_field(&ctl->ccr, SRCCCR_CISZ, cisz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ctl->dirty.bf.ccr = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static int src_set_ca(void *blk, unsigned int ca)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct src_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) set_field(&ctl->ca, SRCCA_CA, ca);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ctl->dirty.bf.ca = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int src_set_sa(void *blk, unsigned int sa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct src_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) set_field(&ctl->sa, SRCSA_SA, sa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ctl->dirty.bf.sa = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static int src_set_la(void *blk, unsigned int la)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct src_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) set_field(&ctl->la, SRCLA_LA, la);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ctl->dirty.bf.la = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static int src_set_pitch(void *blk, unsigned int pitch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct src_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) set_field(&ctl->mpr, MPRLH_PITCH, pitch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ctl->dirty.bf.mpr = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static int src_set_clear_zbufs(void *blk, unsigned int clear)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ((struct src_rsc_ctrl_blk *)blk)->dirty.bf.czbfs = (clear ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static int src_set_dirty(void *blk, unsigned int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ((struct src_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static int src_set_dirty_all(void *blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ((struct src_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define AR_SLOT_SIZE 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define AR_SLOT_BLOCK_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define AR_PTS_PITCH 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define AR_PARAM_SRC_OFFSET 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static unsigned int src_param_pitch_mixer(unsigned int src_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return ((src_idx << 4) + AR_PTS_PITCH + AR_SLOT_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) - AR_PARAM_SRC_OFFSET) % AR_SLOT_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static int src_commit_write(struct hw *hw, unsigned int idx, void *blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct src_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (ctl->dirty.bf.czbfs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* Clear Z-Buffer registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) for (i = 0; i < 8; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) hw_write_20kx(hw, SRCUPZ+idx*0x100+i*0x4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) for (i = 0; i < 4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) hw_write_20kx(hw, SRCDN0Z+idx*0x100+i*0x4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) for (i = 0; i < 8; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) hw_write_20kx(hw, SRCDN1Z+idx*0x100+i*0x4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ctl->dirty.bf.czbfs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (ctl->dirty.bf.mpr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* Take the parameter mixer resource in the same group as that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * the idx src is in for simplicity. Unlike src, all conjugate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * parameter mixer resources must be programmed for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * corresponding conjugate src resources. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) unsigned int pm_idx = src_param_pitch_mixer(idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) hw_write_20kx(hw, PRING_LO_HI+4*pm_idx, ctl->mpr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) hw_write_20kx(hw, PMOPLO+8*pm_idx, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) hw_write_20kx(hw, PMOPHI+8*pm_idx, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ctl->dirty.bf.mpr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (ctl->dirty.bf.sa) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) hw_write_20kx(hw, SRCSA+idx*0x100, ctl->sa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ctl->dirty.bf.sa = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (ctl->dirty.bf.la) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) hw_write_20kx(hw, SRCLA+idx*0x100, ctl->la);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ctl->dirty.bf.la = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (ctl->dirty.bf.ca) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) hw_write_20kx(hw, SRCCA+idx*0x100, ctl->ca);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ctl->dirty.bf.ca = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* Write srccf register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) hw_write_20kx(hw, SRCCF+idx*0x100, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (ctl->dirty.bf.ccr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) hw_write_20kx(hw, SRCCCR+idx*0x100, ctl->ccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) ctl->dirty.bf.ccr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (ctl->dirty.bf.ctl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) hw_write_20kx(hw, SRCCTL+idx*0x100, ctl->ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ctl->dirty.bf.ctl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static int src_get_ca(struct hw *hw, unsigned int idx, void *blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct src_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) ctl->ca = hw_read_20kx(hw, SRCCA+idx*0x100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) ctl->dirty.bf.ca = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return get_field(ctl->ca, SRCCA_CA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static unsigned int src_get_dirty(void *blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return ((struct src_rsc_ctrl_blk *)blk)->dirty.data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static unsigned int src_dirty_conj_mask(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static int src_mgr_enbs_src(void *blk, unsigned int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) ((struct src_mgr_ctrl_blk *)blk)->enbsa = ~(0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ((struct src_mgr_ctrl_blk *)blk)->dirty.bf.enbsa = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static int src_mgr_enb_src(void *blk, unsigned int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static int src_mgr_dsb_src(void *blk, unsigned int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] &= ~(0x1 << (idx%32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static int src_mgr_commit_write(struct hw *hw, void *blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct src_mgr_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) unsigned int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (ctl->dirty.bf.enbsa) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ret = hw_read_20kx(hw, SRCENBSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) } while (ret & 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) hw_write_20kx(hw, SRCENBS, ctl->enbsa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) ctl->dirty.bf.enbsa = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if ((ctl->dirty.data & (0x1 << i))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) hw_write_20kx(hw, SRCENB+(i*0x100), ctl->enb[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ctl->dirty.data &= ~(0x1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static int src_mgr_get_ctrl_blk(void **rblk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct src_mgr_ctrl_blk *blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) *rblk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) blk = kzalloc(sizeof(*blk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (!blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) *rblk = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static int src_mgr_put_ctrl_blk(void *blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) kfree(blk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static int srcimp_mgr_get_ctrl_blk(void **rblk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct srcimp_mgr_ctrl_blk *blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) *rblk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) blk = kzalloc(sizeof(*blk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (!blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) *rblk = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static int srcimp_mgr_put_ctrl_blk(void *blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) kfree(blk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static int srcimp_mgr_set_imaparc(void *blk, unsigned int slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct srcimp_mgr_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) set_field(&ctl->srcimap.srcaim, SRCAIM_ARC, slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) ctl->dirty.bf.srcimap = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static int srcimp_mgr_set_imapuser(void *blk, unsigned int user)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct srcimp_mgr_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) set_field(&ctl->srcimap.srcaim, SRCAIM_SRC, user);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) ctl->dirty.bf.srcimap = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static int srcimp_mgr_set_imapnxt(void *blk, unsigned int next)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct srcimp_mgr_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) set_field(&ctl->srcimap.srcaim, SRCAIM_NXT, next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) ctl->dirty.bf.srcimap = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static int srcimp_mgr_set_imapaddr(void *blk, unsigned int addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct srcimp_mgr_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) ctl->srcimap.idx = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) ctl->dirty.bf.srcimap = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static int srcimp_mgr_commit_write(struct hw *hw, void *blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) struct srcimp_mgr_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (ctl->dirty.bf.srcimap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) hw_write_20kx(hw, SRCIMAP+ctl->srcimap.idx*0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) ctl->srcimap.srcaim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) ctl->dirty.bf.srcimap = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * AMIXER control block definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define AMOPLO_M 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define AMOPLO_X 0x0003FFF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define AMOPLO_Y 0xFFFC0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define AMOPHI_SADR 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define AMOPHI_SE 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /* AMIXER resource register dirty flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) union amixer_dirty {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) u16 amoplo:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) u16 amophi:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) u16 rsv:14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) } bf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) u16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /* AMIXER resource control block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct amixer_rsc_ctrl_blk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) unsigned int amoplo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) unsigned int amophi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) union amixer_dirty dirty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static int amixer_set_mode(void *blk, unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) struct amixer_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) set_field(&ctl->amoplo, AMOPLO_M, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) ctl->dirty.bf.amoplo = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static int amixer_set_iv(void *blk, unsigned int iv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) /* 20k1 amixer does not have this field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static int amixer_set_x(void *blk, unsigned int x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct amixer_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) set_field(&ctl->amoplo, AMOPLO_X, x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) ctl->dirty.bf.amoplo = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static int amixer_set_y(void *blk, unsigned int y)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct amixer_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) set_field(&ctl->amoplo, AMOPLO_Y, y);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) ctl->dirty.bf.amoplo = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static int amixer_set_sadr(void *blk, unsigned int sadr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) struct amixer_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) set_field(&ctl->amophi, AMOPHI_SADR, sadr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) ctl->dirty.bf.amophi = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static int amixer_set_se(void *blk, unsigned int se)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct amixer_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) set_field(&ctl->amophi, AMOPHI_SE, se);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) ctl->dirty.bf.amophi = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static int amixer_set_dirty(void *blk, unsigned int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static int amixer_set_dirty_all(void *blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static int amixer_commit_write(struct hw *hw, unsigned int idx, void *blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) struct amixer_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (ctl->dirty.bf.amoplo || ctl->dirty.bf.amophi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) hw_write_20kx(hw, AMOPLO+idx*8, ctl->amoplo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) ctl->dirty.bf.amoplo = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) hw_write_20kx(hw, AMOPHI+idx*8, ctl->amophi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) ctl->dirty.bf.amophi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) static int amixer_get_y(void *blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) struct amixer_rsc_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return get_field(ctl->amoplo, AMOPLO_Y);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static unsigned int amixer_get_dirty(void *blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static int amixer_rsc_get_ctrl_blk(void **rblk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct amixer_rsc_ctrl_blk *blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) *rblk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) blk = kzalloc(sizeof(*blk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (!blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) *rblk = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static int amixer_rsc_put_ctrl_blk(void *blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) kfree(blk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) static int amixer_mgr_get_ctrl_blk(void **rblk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) /*amixer_mgr_ctrl_blk_t *blk;*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) *rblk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /*blk = kzalloc(sizeof(*blk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (!blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) *rblk = blk;*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static int amixer_mgr_put_ctrl_blk(void *blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /*kfree((amixer_mgr_ctrl_blk_t *)blk);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) * DAIO control block definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /* Receiver Sample Rate Tracker Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define SRTCTL_SRCR 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define SRTCTL_SRCL 0x0000FF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define SRTCTL_RSR 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define SRTCTL_DRAT 0x000C0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define SRTCTL_RLE 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define SRTCTL_RLP 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define SRTCTL_EC 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define SRTCTL_ET 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) /* DAIO Receiver register dirty flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) union dai_dirty {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) u16 srtctl:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) u16 rsv:15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) } bf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) u16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /* DAIO Receiver control block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) struct dai_ctrl_blk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) unsigned int srtctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) union dai_dirty dirty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) /* S/PDIF Transmitter register dirty flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) union dao_dirty {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) u16 spos:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) u16 rsv:15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) } bf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) u16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) /* S/PDIF Transmitter control block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) struct dao_ctrl_blk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) unsigned int spos; /* S/PDIF Output Channel Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) union dao_dirty dirty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /* Audio Input Mapper RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define AIM_ARC 0x00000FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define AIM_NXT 0x007F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) struct daoimap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) unsigned int aim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /* I2S Transmitter/Receiver Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define I2SCTL_EA 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define I2SCTL_EI 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /* S/PDIF Transmitter Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #define SPOCTL_OE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #define SPOCTL_OS 0x0000000E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define SPOCTL_RIV 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #define SPOCTL_LIV 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define SPOCTL_SR 0x000000C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) /* S/PDIF Receiver Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define SPICTL_EN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define SPICTL_I24 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define SPICTL_IB 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define SPICTL_SM 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) #define SPICTL_VM 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) /* DAIO manager register dirty flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) union daio_mgr_dirty {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) u32 i2soctl:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) u32 i2sictl:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) u32 spoctl:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) u32 spictl:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) u32 daoimap:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) u32 rsv:15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) } bf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) /* DAIO manager control block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) struct daio_mgr_ctrl_blk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) unsigned int i2sctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) unsigned int spoctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) unsigned int spictl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) struct daoimap daoimap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) union daio_mgr_dirty dirty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static int dai_srt_set_srcr(void *blk, unsigned int src)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) struct dai_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) set_field(&ctl->srtctl, SRTCTL_SRCR, src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) ctl->dirty.bf.srtctl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) static int dai_srt_set_srcl(void *blk, unsigned int src)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) struct dai_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) set_field(&ctl->srtctl, SRTCTL_SRCL, src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) ctl->dirty.bf.srtctl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) static int dai_srt_set_rsr(void *blk, unsigned int rsr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) struct dai_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) set_field(&ctl->srtctl, SRTCTL_RSR, rsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) ctl->dirty.bf.srtctl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) static int dai_srt_set_drat(void *blk, unsigned int drat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) struct dai_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) set_field(&ctl->srtctl, SRTCTL_DRAT, drat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) ctl->dirty.bf.srtctl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static int dai_srt_set_ec(void *blk, unsigned int ec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) struct dai_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) set_field(&ctl->srtctl, SRTCTL_EC, ec ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) ctl->dirty.bf.srtctl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) static int dai_srt_set_et(void *blk, unsigned int et)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) struct dai_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) set_field(&ctl->srtctl, SRTCTL_ET, et ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) ctl->dirty.bf.srtctl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static int dai_commit_write(struct hw *hw, unsigned int idx, void *blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) struct dai_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (ctl->dirty.bf.srtctl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (idx < 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) /* S/PDIF SRTs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) hw_write_20kx(hw, SRTSCTL+0x4*idx, ctl->srtctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) /* I2S SRT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) hw_write_20kx(hw, SRTICTL, ctl->srtctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) ctl->dirty.bf.srtctl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) static int dai_get_ctrl_blk(void **rblk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) struct dai_ctrl_blk *blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) *rblk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) blk = kzalloc(sizeof(*blk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (!blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) *rblk = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) static int dai_put_ctrl_blk(void *blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) kfree(blk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) static int dao_set_spos(void *blk, unsigned int spos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) ((struct dao_ctrl_blk *)blk)->spos = spos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) ((struct dao_ctrl_blk *)blk)->dirty.bf.spos = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) static int dao_commit_write(struct hw *hw, unsigned int idx, void *blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) struct dao_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) if (ctl->dirty.bf.spos) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) if (idx < 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) /* S/PDIF SPOSx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) hw_write_20kx(hw, SPOS+0x4*idx, ctl->spos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) ctl->dirty.bf.spos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) static int dao_get_spos(void *blk, unsigned int *spos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) *spos = ((struct dao_ctrl_blk *)blk)->spos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) static int dao_get_ctrl_blk(void **rblk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) struct dao_ctrl_blk *blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) *rblk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) blk = kzalloc(sizeof(*blk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (!blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) *rblk = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) static int dao_put_ctrl_blk(void *blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) kfree(blk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) static int daio_mgr_enb_dai(void *blk, unsigned int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) struct daio_mgr_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) if (idx < 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) /* S/PDIF input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) set_field(&ctl->spictl, SPICTL_EN << (idx*8), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) ctl->dirty.bf.spictl |= (0x1 << idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /* I2S input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) idx %= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) set_field(&ctl->i2sctl, I2SCTL_EI << (idx*8), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) ctl->dirty.bf.i2sictl |= (0x1 << idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) static int daio_mgr_dsb_dai(void *blk, unsigned int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) struct daio_mgr_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if (idx < 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) /* S/PDIF input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) set_field(&ctl->spictl, SPICTL_EN << (idx*8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) ctl->dirty.bf.spictl |= (0x1 << idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) /* I2S input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) idx %= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) set_field(&ctl->i2sctl, I2SCTL_EI << (idx*8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) ctl->dirty.bf.i2sictl |= (0x1 << idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) static int daio_mgr_enb_dao(void *blk, unsigned int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) struct daio_mgr_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) if (idx < 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) /* S/PDIF output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) set_field(&ctl->spoctl, SPOCTL_OE << (idx*8), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) ctl->dirty.bf.spoctl |= (0x1 << idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) /* I2S output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) idx %= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) set_field(&ctl->i2sctl, I2SCTL_EA << (idx*8), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) ctl->dirty.bf.i2soctl |= (0x1 << idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) static int daio_mgr_dsb_dao(void *blk, unsigned int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) struct daio_mgr_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) if (idx < 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) /* S/PDIF output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) set_field(&ctl->spoctl, SPOCTL_OE << (idx*8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) ctl->dirty.bf.spoctl |= (0x1 << idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) /* I2S output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) idx %= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) set_field(&ctl->i2sctl, I2SCTL_EA << (idx*8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) ctl->dirty.bf.i2soctl |= (0x1 << idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) static int daio_mgr_dao_init(void *blk, unsigned int idx, unsigned int conf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) struct daio_mgr_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (idx < 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) /* S/PDIF output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) switch ((conf & 0x7)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) break; /* CDIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) set_field(&ctl->spoctl, SPOCTL_LIV << (idx*8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) (conf >> 4) & 0x1); /* Non-audio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) set_field(&ctl->spoctl, SPOCTL_RIV << (idx*8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) (conf >> 4) & 0x1); /* Non-audio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) set_field(&ctl->spoctl, SPOCTL_OS << (idx*8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) ((conf >> 3) & 0x1) ? 2 : 2); /* Raw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) ctl->dirty.bf.spoctl |= (0x1 << idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) /* I2S output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) /*idx %= 4; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) static int daio_mgr_set_imaparc(void *blk, unsigned int slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) struct daio_mgr_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) set_field(&ctl->daoimap.aim, AIM_ARC, slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) ctl->dirty.bf.daoimap = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) static int daio_mgr_set_imapnxt(void *blk, unsigned int next)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) struct daio_mgr_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) set_field(&ctl->daoimap.aim, AIM_NXT, next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) ctl->dirty.bf.daoimap = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) static int daio_mgr_set_imapaddr(void *blk, unsigned int addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) struct daio_mgr_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) ctl->daoimap.idx = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) ctl->dirty.bf.daoimap = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) static int daio_mgr_commit_write(struct hw *hw, void *blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) struct daio_mgr_ctrl_blk *ctl = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) if (ctl->dirty.bf.i2sictl || ctl->dirty.bf.i2soctl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) if ((ctl->dirty.bf.i2sictl & (0x1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) ctl->dirty.bf.i2sictl &= ~(0x1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) if ((ctl->dirty.bf.i2soctl & (0x1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) ctl->dirty.bf.i2soctl &= ~(0x1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) hw_write_20kx(hw, I2SCTL, ctl->i2sctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) if (ctl->dirty.bf.spoctl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) if ((ctl->dirty.bf.spoctl & (0x1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) ctl->dirty.bf.spoctl &= ~(0x1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) hw_write_20kx(hw, SPOCTL, ctl->spoctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) if (ctl->dirty.bf.spictl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if ((ctl->dirty.bf.spictl & (0x1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) ctl->dirty.bf.spictl &= ~(0x1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) hw_write_20kx(hw, SPICTL, ctl->spictl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) if (ctl->dirty.bf.daoimap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) hw_write_20kx(hw, DAOIMAP+ctl->daoimap.idx*4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) ctl->daoimap.aim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) ctl->dirty.bf.daoimap = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) static int daio_mgr_get_ctrl_blk(struct hw *hw, void **rblk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) struct daio_mgr_ctrl_blk *blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) *rblk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) blk = kzalloc(sizeof(*blk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) if (!blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) blk->i2sctl = hw_read_20kx(hw, I2SCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) blk->spoctl = hw_read_20kx(hw, SPOCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) blk->spictl = hw_read_20kx(hw, SPICTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) *rblk = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) static int daio_mgr_put_ctrl_blk(void *blk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) kfree(blk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) /* Timer interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) static int set_timer_irq(struct hw *hw, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) hw_write_20kx(hw, GIE, enable ? IT_INT : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) static int set_timer_tick(struct hw *hw, unsigned int ticks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) if (ticks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) ticks |= TIMR_IE | TIMR_IP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) hw_write_20kx(hw, TIMR, ticks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) static unsigned int get_wc(struct hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) return hw_read_20kx(hw, WC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) /* Card hardware initialization block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) struct dac_conf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) unsigned int msr; /* master sample rate in rsrs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) struct adc_conf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) unsigned int msr; /* master sample rate in rsrs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) unsigned char input; /* the input source of ADC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) unsigned char mic20db; /* boost mic by 20db if input is microphone */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) struct daio_conf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) unsigned int msr; /* master sample rate in rsrs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) struct trn_conf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) unsigned long vm_pgt_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) static int hw_daio_init(struct hw *hw, const struct daio_conf *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) u32 i2sorg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) u32 spdorg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) /* Read I2S CTL. Keep original value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) /*i2sorg = hw_read_20kx(hw, I2SCTL);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) i2sorg = 0x94040404; /* enable all audio out and I2S-D input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) /* Program I2S with proper master sample rate and enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) * the correct I2S channel. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) i2sorg &= 0xfffffffc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) /* Enable S/PDIF-out-A in fixed 24-bit data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) * format and default to 48kHz. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) /* Disable all before doing any changes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) hw_write_20kx(hw, SPOCTL, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) spdorg = 0x05;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) switch (info->msr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) i2sorg |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) spdorg |= (0x0 << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) i2sorg |= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) spdorg |= (0x1 << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) i2sorg |= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) spdorg |= (0x2 << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) i2sorg |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) hw_write_20kx(hw, I2SCTL, i2sorg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) hw_write_20kx(hw, SPOCTL, spdorg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) /* Enable S/PDIF-in-A in fixed 24-bit data format. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) /* Disable all before doing any changes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) hw_write_20kx(hw, SPICTL, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) spdorg = 0x0a0a0a0a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) hw_write_20kx(hw, SPICTL, spdorg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) /* TRANSPORT operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) static int hw_trn_init(struct hw *hw, const struct trn_conf *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) u32 trnctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) u32 ptp_phys_low, ptp_phys_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) /* Set up device page table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) if ((~0UL) == info->vm_pgt_phys) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) dev_err(hw->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) "Wrong device page table page address!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) trnctl = 0x13; /* 32-bit, 4k-size page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) ptp_phys_low = (u32)info->vm_pgt_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) ptp_phys_high = upper_32_bits(info->vm_pgt_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) if (sizeof(void *) == 8) /* 64bit address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) trnctl |= (1 << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) #if 0 /* Only 4k h/w pages for simplicitiy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) #if PAGE_SIZE == 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) trnctl |= (1<<5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) hw_write_20kx(hw, PTPALX, ptp_phys_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) hw_write_20kx(hw, PTPAHX, ptp_phys_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) hw_write_20kx(hw, TRNCTL, trnctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) hw_write_20kx(hw, TRNIS, 0x200c01); /* really needed? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) /* Card initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) #define GCTL_EAC 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) #define GCTL_EAI 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) #define GCTL_BEP 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) #define GCTL_BES 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) #define GCTL_DSP 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) #define GCTL_DBP 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) #define GCTL_ABP 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) #define GCTL_TBP 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) #define GCTL_SBP 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) #define GCTL_FBP 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) #define GCTL_XA 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) #define GCTL_ET 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) #define GCTL_PR 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) #define GCTL_MRL 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) #define GCTL_SDE 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) #define GCTL_SDI 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) #define GCTL_SM 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) #define GCTL_SR 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) #define GCTL_SD 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) #define GCTL_SE 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) #define GCTL_AID 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) static int hw_pll_init(struct hw *hw, unsigned int rsr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) unsigned int pllctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) pllctl = (48000 == rsr) ? 0x1480a001 : 0x1480a731;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) if (hw_read_20kx(hw, PLLCTL) == pllctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) hw_write_20kx(hw, PLLCTL, pllctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) msleep(40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) if (i >= 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) dev_alert(hw->card->dev, "PLL initialization failed!!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) static int hw_auto_init(struct hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) unsigned int gctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) gctl = hw_read_20kx(hw, GCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) set_field(&gctl, GCTL_EAI, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) hw_write_20kx(hw, GCTL, gctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) set_field(&gctl, GCTL_EAI, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) hw_write_20kx(hw, GCTL, gctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) for (i = 0; i < 400000; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) gctl = hw_read_20kx(hw, GCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) if (get_field(gctl, GCTL_AID))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) if (!get_field(gctl, GCTL_AID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) dev_alert(hw->card->dev, "Card Auto-init failed!!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) static int i2c_unlock(struct hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) hw_write_pci(hw, 0xcc, 0x8c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) hw_write_pci(hw, 0xcc, 0x0e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) hw_write_pci(hw, 0xcc, 0xee);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) hw_write_pci(hw, 0xcc, 0xaa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) static void i2c_lock(struct hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) hw_write_pci(hw, 0xcc, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) static void i2c_write(struct hw *hw, u32 device, u32 addr, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) unsigned int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) ret = hw_read_pci(hw, 0xEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) } while (!(ret & 0x800000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) hw_write_pci(hw, 0xE0, device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) hw_write_pci(hw, 0xE4, (data << 8) | (addr & 0xff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) /* DAC operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) static int hw_reset_dac(struct hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) u16 gpioorg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) unsigned int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) if (i2c_unlock(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) ret = hw_read_pci(hw, 0xEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) } while (!(ret & 0x800000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) hw_write_pci(hw, 0xEC, 0x05); /* write to i2c status control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) /* To be effective, need to reset the DAC twice. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) /* set gpio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) gpioorg = (u16)hw_read_20kx(hw, GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) gpioorg &= 0xfffd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) hw_write_20kx(hw, GPIO, gpioorg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) hw_write_20kx(hw, GPIO, gpioorg | 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) i2c_write(hw, 0x00180080, 0x01, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) i2c_write(hw, 0x00180080, 0x02, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) i2c_lock(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) static int hw_dac_init(struct hw *hw, const struct dac_conf *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) u16 gpioorg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) unsigned int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) if (hw->model == CTSB055X) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) /* SB055x, unmute outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) gpioorg = (u16)hw_read_20kx(hw, GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) gpioorg &= 0xffbf; /* set GPIO6 to low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) gpioorg |= 2; /* set GPIO1 to high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) hw_write_20kx(hw, GPIO, gpioorg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) /* mute outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) gpioorg = (u16)hw_read_20kx(hw, GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) gpioorg &= 0xffbf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) hw_write_20kx(hw, GPIO, gpioorg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) hw_reset_dac(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) if (i2c_unlock(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) hw_write_pci(hw, 0xEC, 0x05); /* write to i2c status control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) ret = hw_read_pci(hw, 0xEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) } while (!(ret & 0x800000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) switch (info->msr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) data = 0x24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) data = 0x25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) data = 0x26;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) data = 0x24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) i2c_write(hw, 0x00180080, 0x06, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) i2c_write(hw, 0x00180080, 0x09, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) i2c_write(hw, 0x00180080, 0x0c, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) i2c_write(hw, 0x00180080, 0x0f, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) i2c_lock(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) /* unmute outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) gpioorg = (u16)hw_read_20kx(hw, GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) gpioorg = gpioorg | 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) hw_write_20kx(hw, GPIO, gpioorg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) /* ADC operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) static int is_adc_input_selected_SB055x(struct hw *hw, enum ADCSRC type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) static int is_adc_input_selected_SBx(struct hw *hw, enum ADCSRC type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) data = hw_read_20kx(hw, GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) case ADC_MICIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) data = ((data & (0x1<<7)) && (data & (0x1<<8)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) case ADC_LINEIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) data = (!(data & (0x1<<7)) && (data & (0x1<<8)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) case ADC_NONE: /* Digital I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) data = (!(data & (0x1<<8)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) static int is_adc_input_selected_hendrix(struct hw *hw, enum ADCSRC type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) data = hw_read_20kx(hw, GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) case ADC_MICIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) data = (data & (0x1 << 7)) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) case ADC_LINEIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) data = (data & (0x1 << 7)) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) static int hw_is_adc_input_selected(struct hw *hw, enum ADCSRC type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) switch (hw->model) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) case CTSB055X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) return is_adc_input_selected_SB055x(hw, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) case CTSB073X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) return is_adc_input_selected_hendrix(hw, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) case CTUAA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) return is_adc_input_selected_hendrix(hw, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) return is_adc_input_selected_SBx(hw, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) adc_input_select_SB055x(struct hw *hw, enum ADCSRC type, unsigned char boost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) * check and set the following GPIO bits accordingly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) * ADC_Gain = GPIO2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) * DRM_off = GPIO3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) * Mic_Pwr_on = GPIO7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) * Digital_IO_Sel = GPIO8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) * Mic_Sw = GPIO9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) * Aux/MicLine_Sw = GPIO12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) data = hw_read_20kx(hw, GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) data &= 0xec73;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) case ADC_MICIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) data |= (0x1<<7) | (0x1<<8) | (0x1<<9) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) data |= boost ? (0x1<<2) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) case ADC_LINEIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) data |= (0x1<<8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) case ADC_AUX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) data |= (0x1<<8) | (0x1<<12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) case ADC_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) data |= (0x1<<12); /* set to digital */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) hw_write_20kx(hw, GPIO, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) adc_input_select_SBx(struct hw *hw, enum ADCSRC type, unsigned char boost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) u32 i2c_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) unsigned int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) if (i2c_unlock(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) ret = hw_read_pci(hw, 0xEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) } while (!(ret & 0x800000)); /* i2c ready poll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) /* set i2c access mode as Direct Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) hw_write_pci(hw, 0xEC, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) data = hw_read_20kx(hw, GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) case ADC_MICIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) data |= ((0x1 << 7) | (0x1 << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) i2c_data = 0x1; /* Mic-in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) case ADC_LINEIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) data &= ~(0x1 << 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) data |= (0x1 << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) i2c_data = 0x2; /* Line-in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) case ADC_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) data &= ~(0x1 << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) i2c_data = 0x0; /* set to Digital */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) i2c_lock(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) hw_write_20kx(hw, GPIO, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) i2c_write(hw, 0x001a0080, 0x2a, i2c_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) if (boost) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) i2c_write(hw, 0x001a0080, 0x1c, 0xe7); /* +12dB boost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) i2c_write(hw, 0x001a0080, 0x1e, 0xe7); /* +12dB boost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) i2c_write(hw, 0x001a0080, 0x1c, 0xcf); /* No boost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) i2c_write(hw, 0x001a0080, 0x1e, 0xcf); /* No boost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) i2c_lock(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) adc_input_select_hendrix(struct hw *hw, enum ADCSRC type, unsigned char boost)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) u32 i2c_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) unsigned int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) if (i2c_unlock(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) ret = hw_read_pci(hw, 0xEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) } while (!(ret & 0x800000)); /* i2c ready poll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) /* set i2c access mode as Direct Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) hw_write_pci(hw, 0xEC, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) data = hw_read_20kx(hw, GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) case ADC_MICIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) data |= (0x1 << 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) i2c_data = 0x1; /* Mic-in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) case ADC_LINEIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) data &= ~(0x1 << 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) i2c_data = 0x2; /* Line-in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) i2c_lock(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) hw_write_20kx(hw, GPIO, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) i2c_write(hw, 0x001a0080, 0x2a, i2c_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) if (boost) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) i2c_write(hw, 0x001a0080, 0x1c, 0xe7); /* +12dB boost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) i2c_write(hw, 0x001a0080, 0x1e, 0xe7); /* +12dB boost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) i2c_write(hw, 0x001a0080, 0x1c, 0xcf); /* No boost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) i2c_write(hw, 0x001a0080, 0x1e, 0xcf); /* No boost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) i2c_lock(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) static int hw_adc_input_select(struct hw *hw, enum ADCSRC type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) int state = type == ADC_MICIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) switch (hw->model) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) case CTSB055X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) return adc_input_select_SB055x(hw, type, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) case CTSB073X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) return adc_input_select_hendrix(hw, type, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) case CTUAA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) return adc_input_select_hendrix(hw, type, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) return adc_input_select_SBx(hw, type, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) static int adc_init_SB055x(struct hw *hw, int input, int mic20db)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) return adc_input_select_SB055x(hw, input, mic20db);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) static int adc_init_SBx(struct hw *hw, int input, int mic20db)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) u16 gpioorg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) u16 input_source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) u32 adcdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) unsigned int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) input_source = 0x100; /* default to analog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) switch (input) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) case ADC_MICIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) adcdata = 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) input_source = 0x180; /* set GPIO7 to select Mic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) case ADC_LINEIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) adcdata = 0x2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) case ADC_VIDEO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) adcdata = 0x4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) case ADC_AUX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) adcdata = 0x8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) case ADC_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) adcdata = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) input_source = 0x0; /* set to Digital */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) adcdata = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) if (i2c_unlock(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) ret = hw_read_pci(hw, 0xEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) } while (!(ret & 0x800000)); /* i2c ready poll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) hw_write_pci(hw, 0xEC, 0x05); /* write to i2c status control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) i2c_write(hw, 0x001a0080, 0x0e, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) i2c_write(hw, 0x001a0080, 0x18, 0x0a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) i2c_write(hw, 0x001a0080, 0x28, 0x86);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) i2c_write(hw, 0x001a0080, 0x2a, adcdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) if (mic20db) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) i2c_write(hw, 0x001a0080, 0x1c, 0xf7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) i2c_write(hw, 0x001a0080, 0x1e, 0xf7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) i2c_write(hw, 0x001a0080, 0x1c, 0xcf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) i2c_write(hw, 0x001a0080, 0x1e, 0xcf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) if (!(hw_read_20kx(hw, ID0) & 0x100))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) i2c_write(hw, 0x001a0080, 0x16, 0x26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) i2c_lock(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) gpioorg = (u16)hw_read_20kx(hw, GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) gpioorg &= 0xfe7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) gpioorg |= input_source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) hw_write_20kx(hw, GPIO, gpioorg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) static int hw_adc_init(struct hw *hw, const struct adc_conf *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) if (hw->model == CTSB055X)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) return adc_init_SB055x(hw, info->input, info->mic20db);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) return adc_init_SBx(hw, info->input, info->mic20db);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) static struct capabilities hw_capabilities(struct hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) struct capabilities cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) /* SB073x and Vista compatible cards have no digit IO switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) cap.digit_io_switch = !(hw->model == CTSB073X || hw->model == CTUAA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) cap.dedicated_mic = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) cap.output_switch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) cap.mic_source_switch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) return cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) #define CTLBITS(a, b, c, d) (((a) << 24) | ((b) << 16) | ((c) << 8) | (d))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) #define UAA_CFG_PWRSTATUS 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) #define UAA_CFG_SPACE_FLAG 0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) #define UAA_CORE_CHANGE 0x3FFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) static int uaa_to_xfi(struct pci_dev *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) unsigned int bar0, bar1, bar2, bar3, bar4, bar5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) unsigned int cmd, irq, cl_size, l_timer, pwr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) unsigned int is_uaa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) unsigned int data[4] = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) unsigned int io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) void __iomem *mem_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) const u32 CTLX = CTLBITS('C', 'T', 'L', 'X');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) const u32 CTL_ = CTLBITS('C', 'T', 'L', '-');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) const u32 CTLF = CTLBITS('C', 'T', 'L', 'F');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) const u32 CTLi = CTLBITS('C', 'T', 'L', 'i');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) const u32 CTLA = CTLBITS('C', 'T', 'L', 'A');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) const u32 CTLZ = CTLBITS('C', 'T', 'L', 'Z');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) const u32 CTLL = CTLBITS('C', 'T', 'L', 'L');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) /* By default, Hendrix card UAA Bar0 should be using memory... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) io_base = pci_resource_start(pci, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) mem_base = ioremap(io_base, pci_resource_len(pci, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) if (!mem_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) /* Read current mode from Mode Change Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) for (i = 0; i < 4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) data[i] = readl(mem_base + UAA_CORE_CHANGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) /* Determine current mode... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) if (data[0] == CTLA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) is_uaa = ((data[1] == CTLZ && data[2] == CTLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) && data[3] == CTLA) || (data[1] == CTLA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) && data[2] == CTLZ && data[3] == CTLL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) } else if (data[0] == CTLZ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) is_uaa = (data[1] == CTLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) && data[2] == CTLA && data[3] == CTLA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) } else if (data[0] == CTLL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) is_uaa = (data[1] == CTLA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) && data[2] == CTLA && data[3] == CTLZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) is_uaa = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) if (!is_uaa) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) /* Not in UAA mode currently. Return directly. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) iounmap(mem_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) pci_read_config_dword(pci, PCI_BASE_ADDRESS_0, &bar0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) pci_read_config_dword(pci, PCI_BASE_ADDRESS_1, &bar1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) pci_read_config_dword(pci, PCI_BASE_ADDRESS_2, &bar2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) pci_read_config_dword(pci, PCI_BASE_ADDRESS_3, &bar3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) pci_read_config_dword(pci, PCI_BASE_ADDRESS_4, &bar4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) pci_read_config_dword(pci, PCI_BASE_ADDRESS_5, &bar5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) pci_read_config_dword(pci, PCI_INTERRUPT_LINE, &irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) pci_read_config_dword(pci, PCI_CACHE_LINE_SIZE, &cl_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) pci_read_config_dword(pci, PCI_LATENCY_TIMER, &l_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) pci_read_config_dword(pci, UAA_CFG_PWRSTATUS, &pwr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) pci_read_config_dword(pci, PCI_COMMAND, &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) /* Set up X-Fi core PCI configuration space. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) /* Switch to X-Fi config space with BAR0 exposed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) pci_write_config_dword(pci, UAA_CFG_SPACE_FLAG, 0x87654321);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) /* Copy UAA's BAR5 into X-Fi BAR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) pci_write_config_dword(pci, PCI_BASE_ADDRESS_0, bar5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) /* Switch to X-Fi config space without BAR0 exposed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) pci_write_config_dword(pci, UAA_CFG_SPACE_FLAG, 0x12345678);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, bar1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) pci_write_config_dword(pci, PCI_BASE_ADDRESS_2, bar2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) pci_write_config_dword(pci, PCI_BASE_ADDRESS_3, bar3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) pci_write_config_dword(pci, PCI_BASE_ADDRESS_4, bar4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) pci_write_config_dword(pci, PCI_INTERRUPT_LINE, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) pci_write_config_dword(pci, PCI_CACHE_LINE_SIZE, cl_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) pci_write_config_dword(pci, PCI_LATENCY_TIMER, l_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) pci_write_config_dword(pci, UAA_CFG_PWRSTATUS, pwr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) pci_write_config_dword(pci, PCI_COMMAND, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) /* Switch to X-Fi mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) writel(CTLX, (mem_base + UAA_CORE_CHANGE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) writel(CTL_, (mem_base + UAA_CORE_CHANGE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) writel(CTLF, (mem_base + UAA_CORE_CHANGE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) writel(CTLi, (mem_base + UAA_CORE_CHANGE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) iounmap(mem_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) static irqreturn_t ct_20k1_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) struct hw *hw = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) status = hw_read_20kx(hw, GIP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) if (!status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) if (hw->irq_callback)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) hw->irq_callback(hw->irq_callback_data, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) hw_write_20kx(hw, GIP, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) static int hw_card_start(struct hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) struct pci_dev *pci = hw->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) const unsigned int dma_bits = BITS_PER_LONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) err = pci_enable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) /* Set DMA transfer mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) if (!hw->io_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) err = pci_request_regions(pci, "XFi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) goto error1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) if (hw->model == CTUAA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) hw->io_base = pci_resource_start(pci, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) hw->io_base = pci_resource_start(pci, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) /* Switch to X-Fi mode from UAA mode if neeeded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) if (hw->model == CTUAA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) err = uaa_to_xfi(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) goto error2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) if (hw->irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) err = request_irq(pci->irq, ct_20k1_interrupt, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) KBUILD_MODNAME, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) dev_err(hw->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) "XFi: Cannot get irq %d\n", pci->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) goto error2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) hw->irq = pci->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) hw->card->sync_irq = hw->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) pci_set_master(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) error2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) pci_release_regions(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) hw->io_base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) error1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) static int hw_card_stop(struct hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) unsigned int data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) /* disable transport bus master and queueing of request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) hw_write_20kx(hw, TRNCTL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) /* disable pll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) data = hw_read_20kx(hw, PLLCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) hw_write_20kx(hw, PLLCTL, (data & (~(0x0F<<12))));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) static int hw_card_shutdown(struct hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) if (hw->irq >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) free_irq(hw->irq, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) hw->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) iounmap(hw->mem_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) hw->mem_base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) if (hw->io_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) pci_release_regions(hw->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) hw->io_base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) pci_disable_device(hw->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) static int hw_card_init(struct hw *hw, struct card_conf *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) unsigned int gctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) struct dac_conf dac_info = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) struct adc_conf adc_info = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) struct daio_conf daio_info = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) struct trn_conf trn_info = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) /* Get PCI io port base address and do Hendrix switch if needed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) err = hw_card_start(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) /* PLL init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) err = hw_pll_init(hw, info->rsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) /* kick off auto-init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) err = hw_auto_init(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) /* Enable audio ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) gctl = hw_read_20kx(hw, GCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) set_field(&gctl, GCTL_EAC, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) set_field(&gctl, GCTL_DBP, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) set_field(&gctl, GCTL_TBP, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) set_field(&gctl, GCTL_FBP, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) set_field(&gctl, GCTL_ET, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) hw_write_20kx(hw, GCTL, gctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) /* Reset all global pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) hw_write_20kx(hw, GIE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) /* Reset all SRC pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) hw_write_20kx(hw, SRCIP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) msleep(30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) /* Detect the card ID and configure GPIO accordingly. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) switch (hw->model) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) case CTSB055X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) hw_write_20kx(hw, GPIOCTL, 0x13fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) case CTSB073X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) hw_write_20kx(hw, GPIOCTL, 0x00e6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) case CTUAA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) hw_write_20kx(hw, GPIOCTL, 0x00c2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) hw_write_20kx(hw, GPIOCTL, 0x01e6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) trn_info.vm_pgt_phys = info->vm_pgt_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) err = hw_trn_init(hw, &trn_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) daio_info.msr = info->msr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) err = hw_daio_init(hw, &daio_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) dac_info.msr = info->msr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) err = hw_dac_init(hw, &dac_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) adc_info.msr = info->msr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) adc_info.input = ADC_LINEIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) adc_info.mic20db = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) err = hw_adc_init(hw, &adc_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) data = hw_read_20kx(hw, SRCMCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) data |= 0x1; /* Enables input from the audio ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) hw_write_20kx(hw, SRCMCTL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) static int hw_suspend(struct hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) struct pci_dev *pci = hw->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) hw_card_stop(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) if (hw->model == CTUAA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) /* Switch to UAA config space. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) pci_write_config_dword(pci, UAA_CFG_SPACE_FLAG, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) static int hw_resume(struct hw *hw, struct card_conf *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) /* Re-initialize card hardware. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) return hw_card_init(hw, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) static u32 hw_read_20kx(struct hw *hw, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) spin_lock_irqsave(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) outl(reg, hw->io_base + 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) value = inl(hw->io_base + 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) spin_unlock_irqrestore(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) static void hw_write_20kx(struct hw *hw, u32 reg, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) spin_lock_irqsave(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) outl(reg, hw->io_base + 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) outl(data, hw->io_base + 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) spin_unlock_irqrestore(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) static u32 hw_read_pci(struct hw *hw, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) spin_lock_irqsave(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) outl(reg, hw->io_base + 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) value = inl(hw->io_base + 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) spin_unlock_irqrestore(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) static void hw_write_pci(struct hw *hw, u32 reg, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) spin_lock_irqsave(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) outl(reg, hw->io_base + 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) outl(data, hw->io_base + 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) spin_unlock_irqrestore(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) static const struct hw ct20k1_preset = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) .irq = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) .card_init = hw_card_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) .card_stop = hw_card_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) .pll_init = hw_pll_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) .is_adc_source_selected = hw_is_adc_input_selected,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) .select_adc_source = hw_adc_input_select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) .capabilities = hw_capabilities,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) .suspend = hw_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) .resume = hw_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) .src_rsc_get_ctrl_blk = src_get_rsc_ctrl_blk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) .src_rsc_put_ctrl_blk = src_put_rsc_ctrl_blk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) .src_mgr_get_ctrl_blk = src_mgr_get_ctrl_blk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) .src_mgr_put_ctrl_blk = src_mgr_put_ctrl_blk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) .src_set_state = src_set_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) .src_set_bm = src_set_bm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) .src_set_rsr = src_set_rsr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) .src_set_sf = src_set_sf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) .src_set_wr = src_set_wr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) .src_set_pm = src_set_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) .src_set_rom = src_set_rom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) .src_set_vo = src_set_vo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) .src_set_st = src_set_st,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) .src_set_ie = src_set_ie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) .src_set_ilsz = src_set_ilsz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) .src_set_bp = src_set_bp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) .src_set_cisz = src_set_cisz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) .src_set_ca = src_set_ca,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) .src_set_sa = src_set_sa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) .src_set_la = src_set_la,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) .src_set_pitch = src_set_pitch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) .src_set_dirty = src_set_dirty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) .src_set_clear_zbufs = src_set_clear_zbufs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) .src_set_dirty_all = src_set_dirty_all,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) .src_commit_write = src_commit_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) .src_get_ca = src_get_ca,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) .src_get_dirty = src_get_dirty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) .src_dirty_conj_mask = src_dirty_conj_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) .src_mgr_enbs_src = src_mgr_enbs_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) .src_mgr_enb_src = src_mgr_enb_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) .src_mgr_dsb_src = src_mgr_dsb_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) .src_mgr_commit_write = src_mgr_commit_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) .srcimp_mgr_get_ctrl_blk = srcimp_mgr_get_ctrl_blk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) .srcimp_mgr_put_ctrl_blk = srcimp_mgr_put_ctrl_blk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) .srcimp_mgr_set_imaparc = srcimp_mgr_set_imaparc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) .srcimp_mgr_set_imapuser = srcimp_mgr_set_imapuser,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) .srcimp_mgr_set_imapnxt = srcimp_mgr_set_imapnxt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) .srcimp_mgr_set_imapaddr = srcimp_mgr_set_imapaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) .srcimp_mgr_commit_write = srcimp_mgr_commit_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) .amixer_rsc_get_ctrl_blk = amixer_rsc_get_ctrl_blk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) .amixer_rsc_put_ctrl_blk = amixer_rsc_put_ctrl_blk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) .amixer_mgr_get_ctrl_blk = amixer_mgr_get_ctrl_blk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) .amixer_mgr_put_ctrl_blk = amixer_mgr_put_ctrl_blk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) .amixer_set_mode = amixer_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) .amixer_set_iv = amixer_set_iv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) .amixer_set_x = amixer_set_x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) .amixer_set_y = amixer_set_y,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) .amixer_set_sadr = amixer_set_sadr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) .amixer_set_se = amixer_set_se,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) .amixer_set_dirty = amixer_set_dirty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) .amixer_set_dirty_all = amixer_set_dirty_all,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) .amixer_commit_write = amixer_commit_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) .amixer_get_y = amixer_get_y,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) .amixer_get_dirty = amixer_get_dirty,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) .dai_get_ctrl_blk = dai_get_ctrl_blk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) .dai_put_ctrl_blk = dai_put_ctrl_blk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) .dai_srt_set_srco = dai_srt_set_srcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) .dai_srt_set_srcm = dai_srt_set_srcl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) .dai_srt_set_rsr = dai_srt_set_rsr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) .dai_srt_set_drat = dai_srt_set_drat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) .dai_srt_set_ec = dai_srt_set_ec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) .dai_srt_set_et = dai_srt_set_et,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) .dai_commit_write = dai_commit_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) .dao_get_ctrl_blk = dao_get_ctrl_blk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) .dao_put_ctrl_blk = dao_put_ctrl_blk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) .dao_set_spos = dao_set_spos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) .dao_commit_write = dao_commit_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) .dao_get_spos = dao_get_spos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) .daio_mgr_get_ctrl_blk = daio_mgr_get_ctrl_blk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) .daio_mgr_put_ctrl_blk = daio_mgr_put_ctrl_blk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) .daio_mgr_enb_dai = daio_mgr_enb_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) .daio_mgr_dsb_dai = daio_mgr_dsb_dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) .daio_mgr_enb_dao = daio_mgr_enb_dao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) .daio_mgr_dsb_dao = daio_mgr_dsb_dao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) .daio_mgr_dao_init = daio_mgr_dao_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) .daio_mgr_set_imaparc = daio_mgr_set_imaparc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) .daio_mgr_set_imapnxt = daio_mgr_set_imapnxt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) .daio_mgr_set_imapaddr = daio_mgr_set_imapaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) .daio_mgr_commit_write = daio_mgr_commit_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) .set_timer_irq = set_timer_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) .set_timer_tick = set_timer_tick,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) .get_wc = get_wc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) int create_20k1_hw_obj(struct hw **rhw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) struct hw20k1 *hw20k1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) *rhw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) hw20k1 = kzalloc(sizeof(*hw20k1), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) if (!hw20k1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) spin_lock_init(&hw20k1->reg_20k1_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) spin_lock_init(&hw20k1->reg_pci_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) hw20k1->hw = ct20k1_preset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) *rhw = &hw20k1->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) int destroy_20k1_hw_obj(struct hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) if (hw->io_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) hw_card_shutdown(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) kfree(container_of(hw, struct hw20k1, hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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