^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _20K2REGISTERS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _20K2REGISTERS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* Timer Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define WC 0x1b7000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define TIMR 0x1b7004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) # define TIMR_IE (1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) # define TIMR_IP (1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define GIP 0x1b7010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define GIE 0x1b7014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* I2C Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define I2C_IF_ADDRESS 0x1B9000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define I2C_IF_WDATA 0x1B9004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define I2C_IF_RDATA 0x1B9008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define I2C_IF_STATUS 0x1B900C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define I2C_IF_WLOCK 0x1B9010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Global Control Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define GLOBAL_CNTL_GCTL 0x1B7090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* PLL Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PLL_CTL 0x1B7080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PLL_STAT 0x1B7084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PLL_ENB 0x1B7088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* SRC Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SRC_CTL 0x1A0000 /* 0x1A0000 + (256 * Chn) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SRC_CCR 0x1A0004 /* 0x1A0004 + (256 * Chn) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SRC_IMAP 0x1A0008 /* 0x1A0008 + (256 * Chn) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SRC_CA 0x1A0010 /* 0x1A0010 + (256 * Chn) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SRC_CF 0x1A0014 /* 0x1A0014 + (256 * Chn) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SRC_SA 0x1A0018 /* 0x1A0018 + (256 * Chn) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SRC_LA 0x1A001C /* 0x1A001C + (256 * Chn) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SRC_CTLSWR 0x1A0020 /* 0x1A0020 + (256 * Chn) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SRC_CD 0x1A0080 /* 0x1A0080 + (256 * Chn) + (4 * Regn) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SRC_MCTL 0x1A012C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SRC_IP 0x1A102C /* 0x1A102C + (256 * Regn) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SRC_ENB 0x1A282C /* 0x1A282C + (256 * Regn) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SRC_ENBSTAT 0x1A202C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SRC_ENBSA 0x1A232C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SRC_DN0Z 0x1A0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SRC_DN1Z 0x1A0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SRC_UPZ 0x1A0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* GPIO Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GPIO_DATA 0x1B7020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define GPIO_CTRL 0x1B7024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define GPIO_EXT_DATA 0x1B70A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Virtual memory registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define VMEM_PTPAL 0x1C6300 /* 0x1C6300 + (16 * Chn) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define VMEM_PTPAH 0x1C6304 /* 0x1C6304 + (16 * Chn) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define VMEM_CTL 0x1C7000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Transport Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define TRANSPORT_ENB 0x1B6000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TRANSPORT_CTL 0x1B6004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TRANSPORT_INT 0x1B6008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* Audio IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define AUDIO_IO_AIM 0x1B5000 /* 0x1B5000 + (0x04 * Chn) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define AUDIO_IO_TX_CTL 0x1B5400 /* 0x1B5400 + (0x40 * Chn) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define AUDIO_IO_TX_CSTAT_L 0x1B5408 /* 0x1B5408 + (0x40 * Chn) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define AUDIO_IO_TX_CSTAT_H 0x1B540C /* 0x1B540C + (0x40 * Chn) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define AUDIO_IO_RX_CTL 0x1B5410 /* 0x1B5410 + (0x40 * Chn) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define AUDIO_IO_RX_SRT_CTL 0x1B5420 /* 0x1B5420 + (0x40 * Chn) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define AUDIO_IO_MCLK 0x1B5600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define AUDIO_IO_TX_BLRCLK 0x1B5604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define AUDIO_IO_RX_BLRCLK 0x1B5608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* Mixer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MIXER_AMOPLO 0x130000 /* 0x130000 + (8 * Chn) [4095 : 0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MIXER_AMOPHI 0x130004 /* 0x130004 + (8 * Chn) [4095 : 0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MIXER_PRING_LO_HI 0x188000 /* 0x188000 + (4 * Chn) [4095 : 0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MIXER_PMOPLO 0x138000 /* 0x138000 + (8 * Chn) [4095 : 0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MIXER_PMOPHI 0x138004 /* 0x138004 + (8 * Chn) [4095 : 0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MIXER_AR_ENABLE 0x19000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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