^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * The driver for the Cirrus Logic's Sound Fusion CS46XX based soundcards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * 2002-07 Benny Sjostrand benny@hostmobility.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifdef CONFIG_SND_CS46XX_NEW_DSP /* hack ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef __DSP_SPOS_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define __DSP_SPOS_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define DSP_MAX_SYMBOLS 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define DSP_MAX_MODULES 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DSP_CODE_BYTE_SIZE 0x00007000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DSP_PARAMETER_BYTE_SIZE 0x00003000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DSP_SAMPLE_BYTE_SIZE 0x00003800UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DSP_PARAMETER_BYTE_OFFSET 0x00000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DSP_SAMPLE_BYTE_OFFSET 0x00010000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DSP_CODE_BYTE_OFFSET 0x00020000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define WIDE_INSTR_MASK 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define WIDE_LADD_INSTR_MASK 0x0380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* this instruction types
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) needs to be reallocated when load
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) code into DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) enum wide_opcode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) WIDE_FOR_BEGIN_LOOP = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) WIDE_FOR_BEGIN_LOOP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) WIDE_COND_GOTO_ADDR = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) WIDE_COND_GOTO_CALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) WIDE_TBEQ_COND_GOTO_ADDR = 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) WIDE_TBEQ_COND_CALL_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) WIDE_TBEQ_NCOND_GOTO_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) WIDE_TBEQ_NCOND_CALL_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) WIDE_TBEQ_COND_GOTO1_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) WIDE_TBEQ_COND_CALL1_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) WIDE_TBEQ_NCOND_GOTOI_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) WIDE_TBEQ_NCOND_CALL1_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* SAMPLE segment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define VARI_DECIMATE_BUF1 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define WRITE_BACK_BUF1 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CODEC_INPUT_BUF1 0x0500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PCM_READER_BUF1 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SRC_DELAY_BUF1 0x0680
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define VARI_DECIMATE_BUF0 0x0780
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SRC_OUTPUT_BUF1 0x07A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ASYNC_IP_OUTPUT_BUFFER1 0x0A00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OUTPUT_SNOOP_BUFFER 0x0B00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SPDIFI_IP_OUTPUT_BUFFER1 0x0E00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SPDIFO_IP_OUTPUT_BUFFER1 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MIX_SAMPLE_BUF1 0x1400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MIX_SAMPLE_BUF2 0x2E80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MIX_SAMPLE_BUF3 0x2F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MIX_SAMPLE_BUF4 0x2F80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MIX_SAMPLE_BUF5 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Task stack address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define HFG_STACK 0x066A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define FG_STACK 0x066E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define BG_STACK 0x068E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* SCB's addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SPOSCB_ADDR 0x070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define BG_TREE_SCB_ADDR 0x635
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define NULL_SCB_ADDR 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define TIMINGMASTER_SCB_ADDR 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CODECOUT_SCB_ADDR 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PCMREADER_SCB_ADDR 0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define WRITEBACK_SCB_ADDR 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CODECIN_SCB_ADDR 0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MASTERMIX_SCB_ADDR 0x090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SRCTASK_SCB_ADDR 0x0A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define VARIDECIMATE_SCB_ADDR 0x0B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PCMSERIALIN_SCB_ADDR 0x0C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define FG_TASK_HEADER_ADDR 0x600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define ASYNCTX_SCB_ADDR 0x0E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define ASYNCRX_SCB_ADDR 0x0F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SRCTASKII_SCB_ADDR 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define OUTPUTSNOOP_SCB_ADDR 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PCMSERIALINII_SCB_ADDR 0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SPIOWRITE_SCB_ADDR 0x130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define REAR_CODECOUT_SCB_ADDR 0x140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define OUTPUTSNOOPII_SCB_ADDR 0x150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PCMSERIALIN_PCM_SCB_ADDR 0x160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define RECORD_MIXER_SCB_ADDR 0x170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define REAR_MIXER_SCB_ADDR 0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CLFE_MIXER_SCB_ADDR 0x190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CLFE_CODEC_SCB_ADDR 0x1A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* hyperforground SCB's*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define HFG_TREE_SCB 0xBA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SPDIFI_SCB_INST 0xBB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SPDIFO_SCB_INST 0xBC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define WRITE_BACK_SPB 0x0D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define AsyncCIOFIFOPointer 0xd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SPDIFOFIFOPointer 0xd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SPDIFIFIFOPointer 0xd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define TCBData 0xb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define HFGFlags 0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define TCBContextBlk 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define AFGTxAccumPhi 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SCBsubListPtr 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SCBfuncEntryPtr 0xA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SRCCorPerGof 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SRCPhiIncr6Int26Frac 0xd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SCBVolumeCtrl 0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* conf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define UseASER1Input 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * The following defines are for the flags in the rsConfig01/23 registers of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * the SP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define RSCONFIG_MODULO_SIZE_MASK 0x0000000FL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define RSCONFIG_MODULO_16 0x00000001L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define RSCONFIG_MODULO_32 0x00000002L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define RSCONFIG_MODULO_64 0x00000003L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define RSCONFIG_MODULO_128 0x00000004L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define RSCONFIG_MODULO_256 0x00000005L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define RSCONFIG_MODULO_512 0x00000006L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define RSCONFIG_MODULO_1024 0x00000007L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define RSCONFIG_MODULO_4 0x00000008L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define RSCONFIG_MODULO_8 0x00000009L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define RSCONFIG_SAMPLE_SIZE_MASK 0x000000C0L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define RSCONFIG_SAMPLE_8MONO 0x00000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define RSCONFIG_SAMPLE_8STEREO 0x00000040L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define RSCONFIG_SAMPLE_16MONO 0x00000080L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define RSCONFIG_SAMPLE_16STEREO 0x000000C0L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define RSCONFIG_UNDERRUN_ZERO 0x00004000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define RSCONFIG_DMA_TO_HOST 0x00008000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define RSCONFIG_STREAM_NUM_MASK 0x00FF0000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define RSCONFIG_MAX_DMA_SIZE_MASK 0x1F000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define RSCONFIG_DMA_ENABLE 0x20000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define RSCONFIG_PRIORITY_MASK 0xC0000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define RSCONFIG_PRIORITY_HIGH 0x00000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define RSCONFIG_PRIORITY_MEDIUM_HIGH 0x40000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define RSCONFIG_PRIORITY_MEDIUM_LOW 0x80000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define RSCONFIG_PRIORITY_LOW 0xC0000000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define RSCONFIG_STREAM_NUM_SHIFT 16L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define RSCONFIG_MAX_DMA_SIZE_SHIFT 24L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* SP constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define FG_INTERVAL_TIMER_PERIOD 0x0051
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define BG_INTERVAL_TIMER_PERIOD 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* Only SP accessible registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SP_ASER_COUNTDOWN 0x8040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define SP_SPDOUT_FIFO 0x0108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define SP_SPDIN_MI_FIFO 0x01E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define SP_SPDIN_D_FIFO 0x01F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SP_SPDIN_STATUS 0x8048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define SP_SPDIN_CONTROL 0x8049
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SP_SPDIN_FIFOPTR 0x804A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define SP_SPDOUT_STATUS 0x804C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define SP_SPDOUT_CONTROL 0x804D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define SP_SPDOUT_CSUV 0x808E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static inline u8 _wrap_all_bits (u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u8 wrapped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* wrap all 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) wrapped =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ((val & 0x1 ) << 7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ((val & 0x2 ) << 5) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ((val & 0x4 ) << 3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ((val & 0x8 ) << 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ((val & 0x10) >> 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ((val & 0x20) >> 3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ((val & 0x40) >> 5) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ((val & 0x80) >> 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return wrapped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static inline void cs46xx_dsp_spos_update_scb (struct snd_cs46xx * chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct dsp_scb_descriptor * scb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* update nextSCB and subListPtr in SCB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) snd_cs46xx_poke(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) (scb->address + SCBsubListPtr) << 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) (scb->sub_list_ptr->address << 0x10) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) (scb->next_scb_ptr->address));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) scb->updated = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static inline void cs46xx_dsp_scb_set_volume (struct snd_cs46xx * chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct dsp_scb_descriptor * scb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u16 left, u16 right)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) unsigned int val = ((0xffff - left) << 16 | (0xffff - right));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) snd_cs46xx_poke(chip, (scb->address + SCBVolumeCtrl) << 2, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) snd_cs46xx_poke(chip, (scb->address + SCBVolumeCtrl + 1) << 2, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) scb->volume_set = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) scb->volume[0] = left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) scb->volume[1] = right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #endif /* __DSP_SPOS_H__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #endif /* CONFIG_SND_CS46XX_NEW_DSP */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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