^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * 2002-07 Benny Sjostrand benny@hostmobility.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/vmalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <sound/control.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <sound/info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <sound/asoundef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "cs46xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "cs46xx_lib.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "dsp_spos.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static int cs46xx_dsp_async_init (struct snd_cs46xx *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct dsp_scb_descriptor * fg_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static const enum wide_opcode wide_opcodes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) WIDE_FOR_BEGIN_LOOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) WIDE_FOR_BEGIN_LOOP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) WIDE_COND_GOTO_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) WIDE_COND_GOTO_CALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) WIDE_TBEQ_COND_GOTO_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) WIDE_TBEQ_COND_CALL_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) WIDE_TBEQ_NCOND_GOTO_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) WIDE_TBEQ_NCOND_CALL_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) WIDE_TBEQ_COND_GOTO1_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) WIDE_TBEQ_COND_CALL1_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) WIDE_TBEQ_NCOND_GOTOI_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) WIDE_TBEQ_NCOND_CALL1_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static int shadow_and_reallocate_code (struct snd_cs46xx * chip, u32 * data, u32 size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u32 overlay_begin_address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned int i = 0, j, nreallocated = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u32 hival,loval,address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u32 mop_operands,mop_type,wide_op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct dsp_spos_instance * ins = chip->dsp_spos_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (snd_BUG_ON(size %2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) while (i < size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) loval = data[i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) hival = data[i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (ins->code.offset > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) mop_operands = (hival >> 6) & 0x03fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) mop_type = mop_operands >> 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* check for wide type instruction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (mop_type == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) (mop_operands & WIDE_LADD_INSTR_MASK) == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) (mop_operands & WIDE_INSTR_MASK) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) wide_op = loval & 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) for (j = 0;j < ARRAY_SIZE(wide_opcodes); ++j) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (wide_opcodes[j] == wide_op) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* need to reallocate instruction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) address = (hival & 0x00FFF) << 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) address |= loval >> 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) "handle_wideop[1]: %05x:%05x addr %04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) hival, loval, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if ( !(address & 0x8000) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) address += (ins->code.offset / 2) - overlay_begin_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) "handle_wideop[1]: ROM symbol not reallocated\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) hival &= 0xFF000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) loval &= 0x07FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) hival |= ( (address >> 5) & 0x00FFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) loval |= ( (address << 15) & 0xF8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) address = (hival & 0x00FFF) << 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) address |= loval >> 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) "handle_wideop:[2] %05x:%05x addr %04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) hival, loval, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) nreallocated++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) } /* wide_opcodes[j] == wide_op */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) } /* for */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) } /* mod_type == 0 ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) } /* ins->code.offset > 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ins->code.data[ins->code.size++] = loval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ins->code.data[ins->code.size++] = hival;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) "dsp_spos: %d instructions reallocated\n", nreallocated);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return nreallocated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static struct dsp_segment_desc * get_segment_desc (struct dsp_module_desc * module, int seg_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) for (i = 0;i < module->nsegments; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (module->segments[i].segment_type == seg_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return (module->segments + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static int find_free_symbol_index (struct dsp_spos_instance * ins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int index = ins->symbol_table.nsymbols,i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) for (i = ins->symbol_table.highest_frag_index; i < ins->symbol_table.nsymbols; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (ins->symbol_table.symbols[i].deleted) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) index = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int add_symbols (struct snd_cs46xx * chip, struct dsp_module_desc * module)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct dsp_spos_instance * ins = chip->dsp_spos_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (module->symbol_table.nsymbols > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (!strcmp(module->symbol_table.symbols[0].symbol_name, "OVERLAYBEGINADDRESS") &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) module->symbol_table.symbols[0].symbol_type == SYMBOL_CONSTANT ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) module->overlay_begin_address = module->symbol_table.symbols[0].address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) for (i = 0;i < module->symbol_table.nsymbols; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (ins->symbol_table.nsymbols == (DSP_MAX_SYMBOLS - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) "dsp_spos: symbol table is full\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (cs46xx_dsp_lookup_symbol(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) module->symbol_table.symbols[i].symbol_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) module->symbol_table.symbols[i].symbol_type) == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ins->symbol_table.symbols[ins->symbol_table.nsymbols] = module->symbol_table.symbols[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ins->symbol_table.symbols[ins->symbol_table.nsymbols].address += ((ins->code.offset / 2) - module->overlay_begin_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ins->symbol_table.symbols[ins->symbol_table.nsymbols].module = module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ins->symbol_table.symbols[ins->symbol_table.nsymbols].deleted = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (ins->symbol_table.nsymbols > ins->symbol_table.highest_frag_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ins->symbol_table.highest_frag_index = ins->symbol_table.nsymbols;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ins->symbol_table.nsymbols++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) "dsp_spos: symbol <%s> duplicated, probably nothing wrong with that (Cirrus?)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) module->symbol_table.symbols[i].symbol_name); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static struct dsp_symbol_entry *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) add_symbol (struct snd_cs46xx * chip, char * symbol_name, u32 address, int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct dsp_spos_instance * ins = chip->dsp_spos_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct dsp_symbol_entry * symbol = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (ins->symbol_table.nsymbols == (DSP_MAX_SYMBOLS - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) dev_err(chip->card->dev, "dsp_spos: symbol table is full\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (cs46xx_dsp_lookup_symbol(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) symbol_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) type) != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) "dsp_spos: symbol <%s> duplicated\n", symbol_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) index = find_free_symbol_index (ins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) strcpy (ins->symbol_table.symbols[index].symbol_name, symbol_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ins->symbol_table.symbols[index].address = address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ins->symbol_table.symbols[index].symbol_type = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ins->symbol_table.symbols[index].module = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ins->symbol_table.symbols[index].deleted = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) symbol = (ins->symbol_table.symbols + index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (index > ins->symbol_table.highest_frag_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ins->symbol_table.highest_frag_index = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (index == ins->symbol_table.nsymbols)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) ins->symbol_table.nsymbols++; /* no frag. in list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return symbol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct dsp_spos_instance *cs46xx_dsp_spos_create (struct snd_cs46xx * chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct dsp_spos_instance * ins = kzalloc(sizeof(struct dsp_spos_instance), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (ins == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* better to use vmalloc for this big table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ins->symbol_table.symbols =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) vmalloc(array_size(DSP_MAX_SYMBOLS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) sizeof(struct dsp_symbol_entry)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ins->code.data = kmalloc(DSP_CODE_BYTE_SIZE, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ins->modules = kmalloc_array(DSP_MAX_MODULES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) sizeof(struct dsp_module_desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (!ins->symbol_table.symbols || !ins->code.data || !ins->modules) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) cs46xx_dsp_spos_destroy(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ins->symbol_table.nsymbols = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ins->symbol_table.highest_frag_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ins->code.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ins->code.size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ins->nscb = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ins->ntask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ins->nmodules = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* default SPDIF input sample rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) to 48000 khz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ins->spdif_in_sample_rate = 48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* maximize volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ins->dac_volume_right = 0x8000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) ins->dac_volume_left = 0x8000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) ins->spdif_input_volume_right = 0x8000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ins->spdif_input_volume_left = 0x8000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* set left and right validity bits and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) default channel status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) ins->spdif_csuv_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ins->spdif_csuv_stream =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* byte 0 */ ((unsigned int)_wrap_all_bits( (SNDRV_PCM_DEFAULT_CON_SPDIF & 0xff)) << 24) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* byte 1 */ ((unsigned int)_wrap_all_bits( ((SNDRV_PCM_DEFAULT_CON_SPDIF >> 8) & 0xff)) << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* byte 3 */ (unsigned int)_wrap_all_bits( (SNDRV_PCM_DEFAULT_CON_SPDIF >> 24) & 0xff) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* left and right validity bits */ (1 << 13) | (1 << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return ins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) kfree(ins->modules);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) kfree(ins->code.data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) vfree(ins->symbol_table.symbols);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) kfree(ins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) void cs46xx_dsp_spos_destroy (struct snd_cs46xx * chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct dsp_spos_instance * ins = chip->dsp_spos_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (snd_BUG_ON(!ins))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) mutex_lock(&chip->spos_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) for (i = 0; i < ins->nscb; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (ins->scbs[i].deleted) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) cs46xx_dsp_proc_free_scb_desc ( (ins->scbs + i) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) kfree(ins->scbs[i].data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) kfree(ins->code.data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) vfree(ins->symbol_table.symbols);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) kfree(ins->modules);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) kfree(ins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) mutex_unlock(&chip->spos_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static int dsp_load_parameter(struct snd_cs46xx *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct dsp_segment_desc *parameter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u32 doffset, dsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (!parameter) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) "dsp_spos: module got no parameter segment\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) doffset = (parameter->offset * 4 + DSP_PARAMETER_BYTE_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) dsize = parameter->size * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) "dsp_spos: downloading parameter data to chip (%08x-%08x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) doffset,doffset + dsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (snd_cs46xx_download (chip, parameter->data, doffset, dsize)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) "dsp_spos: failed to download parameter data to DSP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static int dsp_load_sample(struct snd_cs46xx *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct dsp_segment_desc *sample)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u32 doffset, dsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (!sample) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) "dsp_spos: module got no sample segment\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) doffset = (sample->offset * 4 + DSP_SAMPLE_BYTE_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) dsize = sample->size * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) "dsp_spos: downloading sample data to chip (%08x-%08x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) doffset,doffset + dsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (snd_cs46xx_download (chip,sample->data,doffset,dsize)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) "dsp_spos: failed to sample data to DSP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) int cs46xx_dsp_load_module (struct snd_cs46xx * chip, struct dsp_module_desc * module)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct dsp_spos_instance * ins = chip->dsp_spos_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct dsp_segment_desc * code = get_segment_desc (module,SEGTYPE_SP_PROGRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) u32 doffset, dsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (ins->nmodules == DSP_MAX_MODULES - 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) "dsp_spos: to many modules loaded into DSP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) "dsp_spos: loading module %s into DSP\n", module->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (ins->nmodules == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) dev_dbg(chip->card->dev, "dsp_spos: clearing parameter area\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) snd_cs46xx_clear_BA1(chip, DSP_PARAMETER_BYTE_OFFSET, DSP_PARAMETER_BYTE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) err = dsp_load_parameter(chip, get_segment_desc(module,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) SEGTYPE_SP_PARAMETER));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (ins->nmodules == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) dev_dbg(chip->card->dev, "dsp_spos: clearing sample area\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) snd_cs46xx_clear_BA1(chip, DSP_SAMPLE_BYTE_OFFSET, DSP_SAMPLE_BYTE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) err = dsp_load_sample(chip, get_segment_desc(module,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) SEGTYPE_SP_SAMPLE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (ins->nmodules == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) dev_dbg(chip->card->dev, "dsp_spos: clearing code area\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) snd_cs46xx_clear_BA1(chip, DSP_CODE_BYTE_OFFSET, DSP_CODE_BYTE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (code == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) "dsp_spos: module got no code segment\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (ins->code.offset + code->size > DSP_CODE_BYTE_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) "dsp_spos: no space available in DSP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) module->load_address = ins->code.offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) module->overlay_begin_address = 0x000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* if module has a code segment it must have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) symbol table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (snd_BUG_ON(!module->symbol_table.symbols))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (add_symbols(chip,module)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) "dsp_spos: failed to load symbol table\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) doffset = (code->offset * 4 + ins->code.offset * 4 + DSP_CODE_BYTE_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) dsize = code->size * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) "dsp_spos: downloading code to chip (%08x-%08x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) doffset,doffset + dsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) module->nfixups = shadow_and_reallocate_code(chip,code->data,code->size,module->overlay_begin_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (snd_cs46xx_download (chip,(ins->code.data + ins->code.offset),doffset,dsize)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) "dsp_spos: failed to download code to DSP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ins->code.offset += code->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* NOTE: module segments and symbol table must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) statically allocated. Case that module data is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) not generated by the ospparser */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) ins->modules[ins->nmodules] = *module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ins->nmodules++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct dsp_symbol_entry *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) cs46xx_dsp_lookup_symbol (struct snd_cs46xx * chip, char * symbol_name, int symbol_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct dsp_spos_instance * ins = chip->dsp_spos_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) for ( i = 0; i < ins->symbol_table.nsymbols; ++i ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (ins->symbol_table.symbols[i].deleted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (!strcmp(ins->symbol_table.symbols[i].symbol_name,symbol_name) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ins->symbol_table.symbols[i].symbol_type == symbol_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return (ins->symbol_table.symbols + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) dev_err(chip->card->dev, "dsp_spos: symbol <%s> type %02x not found\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) symbol_name,symbol_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #ifdef CONFIG_SND_PROC_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static struct dsp_symbol_entry *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) cs46xx_dsp_lookup_symbol_addr (struct snd_cs46xx * chip, u32 address, int symbol_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) struct dsp_spos_instance * ins = chip->dsp_spos_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) for ( i = 0; i < ins->symbol_table.nsymbols; ++i ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (ins->symbol_table.symbols[i].deleted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (ins->symbol_table.symbols[i].address == address &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) ins->symbol_table.symbols[i].symbol_type == symbol_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return (ins->symbol_table.symbols + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static void cs46xx_dsp_proc_symbol_table_read (struct snd_info_entry *entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct snd_info_buffer *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct snd_cs46xx *chip = entry->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct dsp_spos_instance * ins = chip->dsp_spos_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) snd_iprintf(buffer, "SYMBOLS:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) for ( i = 0; i < ins->symbol_table.nsymbols; ++i ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) char *module_str = "system";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (ins->symbol_table.symbols[i].deleted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (ins->symbol_table.symbols[i].module != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) module_str = ins->symbol_table.symbols[i].module->module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) snd_iprintf(buffer, "%04X <%02X> %s [%s]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) ins->symbol_table.symbols[i].address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) ins->symbol_table.symbols[i].symbol_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) ins->symbol_table.symbols[i].symbol_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) module_str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static void cs46xx_dsp_proc_modules_read (struct snd_info_entry *entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct snd_info_buffer *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct snd_cs46xx *chip = entry->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct dsp_spos_instance * ins = chip->dsp_spos_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) int i,j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) mutex_lock(&chip->spos_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) snd_iprintf(buffer, "MODULES:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) for ( i = 0; i < ins->nmodules; ++i ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) snd_iprintf(buffer, "\n%s:\n", ins->modules[i].module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) snd_iprintf(buffer, " %d symbols\n", ins->modules[i].symbol_table.nsymbols);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) snd_iprintf(buffer, " %d fixups\n", ins->modules[i].nfixups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) for (j = 0; j < ins->modules[i].nsegments; ++ j) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct dsp_segment_desc * desc = (ins->modules[i].segments + j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) snd_iprintf(buffer, " segment %02x offset %08x size %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) desc->segment_type,desc->offset, desc->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) mutex_unlock(&chip->spos_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static void cs46xx_dsp_proc_task_tree_read (struct snd_info_entry *entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) struct snd_info_buffer *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct snd_cs46xx *chip = entry->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct dsp_spos_instance * ins = chip->dsp_spos_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) int i, j, col;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) void __iomem *dst = chip->region.idx[1].remap_addr + DSP_PARAMETER_BYTE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) mutex_lock(&chip->spos_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) snd_iprintf(buffer, "TASK TREES:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) for ( i = 0; i < ins->ntask; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) snd_iprintf(buffer,"\n%04x %s:\n",ins->tasks[i].address,ins->tasks[i].task_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) for (col = 0,j = 0;j < ins->tasks[i].size; j++,col++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (col == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) snd_iprintf(buffer,"\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) col = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) val = readl(dst + (ins->tasks[i].address + j) * sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) snd_iprintf(buffer,"%08x ",val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) snd_iprintf(buffer,"\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) mutex_unlock(&chip->spos_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static void cs46xx_dsp_proc_scb_read (struct snd_info_entry *entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct snd_info_buffer *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct snd_cs46xx *chip = entry->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) struct dsp_spos_instance * ins = chip->dsp_spos_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) mutex_lock(&chip->spos_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) snd_iprintf(buffer, "SCB's:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) for ( i = 0; i < ins->nscb; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (ins->scbs[i].deleted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) snd_iprintf(buffer,"\n%04x %s:\n\n",ins->scbs[i].address,ins->scbs[i].scb_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (ins->scbs[i].parent_scb_ptr != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) snd_iprintf(buffer,"parent [%s:%04x] ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) ins->scbs[i].parent_scb_ptr->scb_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) ins->scbs[i].parent_scb_ptr->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) } else snd_iprintf(buffer,"parent [none] ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) snd_iprintf(buffer,"sub_list_ptr [%s:%04x]\nnext_scb_ptr [%s:%04x] task_entry [%s:%04x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) ins->scbs[i].sub_list_ptr->scb_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) ins->scbs[i].sub_list_ptr->address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) ins->scbs[i].next_scb_ptr->scb_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) ins->scbs[i].next_scb_ptr->address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) ins->scbs[i].task_entry->symbol_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) ins->scbs[i].task_entry->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) snd_iprintf(buffer,"\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) mutex_unlock(&chip->spos_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static void cs46xx_dsp_proc_parameter_dump_read (struct snd_info_entry *entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) struct snd_info_buffer *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct snd_cs46xx *chip = entry->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /*struct dsp_spos_instance * ins = chip->dsp_spos_instance; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) unsigned int i, col = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) void __iomem *dst = chip->region.idx[1].remap_addr + DSP_PARAMETER_BYTE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct dsp_symbol_entry * symbol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) for (i = 0;i < DSP_PARAMETER_BYTE_SIZE; i += sizeof(u32),col ++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (col == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) snd_iprintf(buffer,"\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) col = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if ( (symbol = cs46xx_dsp_lookup_symbol_addr (chip,i / sizeof(u32), SYMBOL_PARAMETER)) != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) col = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) snd_iprintf (buffer,"\n%s:\n",symbol->symbol_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (col == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) snd_iprintf(buffer, "%04X ", i / (unsigned int)sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) snd_iprintf(buffer,"%08X ",readl(dst + i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static void cs46xx_dsp_proc_sample_dump_read (struct snd_info_entry *entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) struct snd_info_buffer *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) struct snd_cs46xx *chip = entry->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) int i,col = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) void __iomem *dst = chip->region.idx[2].remap_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) snd_iprintf(buffer,"PCMREADER:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) for (i = PCM_READER_BUF1;i < PCM_READER_BUF1 + 0x30; i += sizeof(u32),col ++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (col == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) snd_iprintf(buffer,"\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) col = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (col == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) snd_iprintf(buffer, "%04X ",i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) snd_iprintf(buffer,"%08X ",readl(dst + i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) snd_iprintf(buffer,"\nMIX_SAMPLE_BUF1:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) col = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) for (i = MIX_SAMPLE_BUF1;i < MIX_SAMPLE_BUF1 + 0x40; i += sizeof(u32),col ++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (col == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) snd_iprintf(buffer,"\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) col = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (col == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) snd_iprintf(buffer, "%04X ",i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) snd_iprintf(buffer,"%08X ",readl(dst + i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) snd_iprintf(buffer,"\nSRC_TASK_SCB1:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) col = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) for (i = 0x2480 ; i < 0x2480 + 0x40 ; i += sizeof(u32),col ++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (col == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) snd_iprintf(buffer,"\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) col = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (col == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) snd_iprintf(buffer, "%04X ",i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) snd_iprintf(buffer,"%08X ",readl(dst + i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) snd_iprintf(buffer,"\nSPDIFO_BUFFER:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) col = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) for (i = SPDIFO_IP_OUTPUT_BUFFER1;i < SPDIFO_IP_OUTPUT_BUFFER1 + 0x30; i += sizeof(u32),col ++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (col == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) snd_iprintf(buffer,"\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) col = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (col == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) snd_iprintf(buffer, "%04X ",i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) snd_iprintf(buffer,"%08X ",readl(dst + i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) snd_iprintf(buffer,"\n...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) col = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) for (i = SPDIFO_IP_OUTPUT_BUFFER1+0xD0;i < SPDIFO_IP_OUTPUT_BUFFER1 + 0x110; i += sizeof(u32),col ++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (col == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) snd_iprintf(buffer,"\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) col = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (col == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) snd_iprintf(buffer, "%04X ",i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) snd_iprintf(buffer,"%08X ",readl(dst + i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) snd_iprintf(buffer,"\nOUTPUT_SNOOP:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) col = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) for (i = OUTPUT_SNOOP_BUFFER;i < OUTPUT_SNOOP_BUFFER + 0x40; i += sizeof(u32),col ++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (col == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) snd_iprintf(buffer,"\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) col = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (col == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) snd_iprintf(buffer, "%04X ",i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) snd_iprintf(buffer,"%08X ",readl(dst + i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) snd_iprintf(buffer,"\nCODEC_INPUT_BUF1: \n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) col = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) for (i = CODEC_INPUT_BUF1;i < CODEC_INPUT_BUF1 + 0x40; i += sizeof(u32),col ++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (col == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) snd_iprintf(buffer,"\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) col = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (col == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) snd_iprintf(buffer, "%04X ",i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) snd_iprintf(buffer,"%08X ",readl(dst + i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) snd_iprintf(buffer,"\nWRITE_BACK_BUF1: \n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) col = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) for (i = WRITE_BACK_BUF1;i < WRITE_BACK_BUF1 + 0x40; i += sizeof(u32),col ++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (col == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) snd_iprintf(buffer,"\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) col = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (col == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) snd_iprintf(buffer, "%04X ",i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) snd_iprintf(buffer,"%08X ",readl(dst + i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) snd_iprintf(buffer,"\nSPDIFI_IP_OUTPUT_BUFFER1: \n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) col = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) for (i = SPDIFI_IP_OUTPUT_BUFFER1;i < SPDIFI_IP_OUTPUT_BUFFER1 + 0x80; i += sizeof(u32),col ++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (col == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) snd_iprintf(buffer,"\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) col = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (col == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) snd_iprintf(buffer, "%04X ",i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) snd_iprintf(buffer,"%08X ",readl(dst + i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) snd_iprintf(buffer,"\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) int cs46xx_dsp_proc_init (struct snd_card *card, struct snd_cs46xx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) struct snd_info_entry *entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) struct dsp_spos_instance * ins = chip->dsp_spos_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) ins->snd_card = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) entry = snd_info_create_card_entry(card, "dsp", card->proc_root);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) entry->mode = S_IFDIR | 0555;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) ins->proc_dsp_dir = entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (!ins->proc_dsp_dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) entry = snd_info_create_card_entry(card, "spos_symbols",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) ins->proc_dsp_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) snd_info_set_text_ops(entry, chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) cs46xx_dsp_proc_symbol_table_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) entry = snd_info_create_card_entry(card, "spos_modules",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) ins->proc_dsp_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) snd_info_set_text_ops(entry, chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) cs46xx_dsp_proc_modules_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) entry = snd_info_create_card_entry(card, "parameter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) ins->proc_dsp_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) snd_info_set_text_ops(entry, chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) cs46xx_dsp_proc_parameter_dump_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) entry = snd_info_create_card_entry(card, "sample",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) ins->proc_dsp_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) snd_info_set_text_ops(entry, chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) cs46xx_dsp_proc_sample_dump_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) entry = snd_info_create_card_entry(card, "task_tree",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) ins->proc_dsp_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) if (entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) snd_info_set_text_ops(entry, chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) cs46xx_dsp_proc_task_tree_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) entry = snd_info_create_card_entry(card, "scb_info",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) ins->proc_dsp_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) snd_info_set_text_ops(entry, chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) cs46xx_dsp_proc_scb_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) mutex_lock(&chip->spos_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) /* register/update SCB's entries on proc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) for (i = 0; i < ins->nscb; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if (ins->scbs[i].deleted) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) cs46xx_dsp_proc_register_scb_desc (chip, (ins->scbs + i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) mutex_unlock(&chip->spos_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) int cs46xx_dsp_proc_done (struct snd_cs46xx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) struct dsp_spos_instance * ins = chip->dsp_spos_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) if (!ins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) mutex_lock(&chip->spos_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) for (i = 0; i < ins->nscb; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (ins->scbs[i].deleted) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) cs46xx_dsp_proc_free_scb_desc ( (ins->scbs + i) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) mutex_unlock(&chip->spos_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) snd_info_free_entry(ins->proc_dsp_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) ins->proc_dsp_dir = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) #endif /* CONFIG_SND_PROC_FS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static void _dsp_create_task_tree (struct snd_cs46xx *chip, u32 * task_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) u32 dest, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) void __iomem *spdst = chip->region.idx[1].remap_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) DSP_PARAMETER_BYTE_OFFSET + dest * sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) for (i = 0; i < size; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) dev_dbg(chip->card->dev, "addr %p, val %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) spdst, task_data[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) writel(task_data[i],spdst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) spdst += sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) static void _dsp_create_scb (struct snd_cs46xx *chip, u32 * scb_data, u32 dest)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) void __iomem *spdst = chip->region.idx[1].remap_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) DSP_PARAMETER_BYTE_OFFSET + dest * sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) for (i = 0; i < 0x10; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) dev_dbg(chip->card->dev, "addr %p, val %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) spdst, scb_data[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) writel(scb_data[i],spdst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) spdst += sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) static int find_free_scb_index (struct dsp_spos_instance * ins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) int index = ins->nscb, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) for (i = ins->scb_highest_frag_index; i < ins->nscb; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (ins->scbs[i].deleted) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) index = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) static struct dsp_scb_descriptor * _map_scb (struct snd_cs46xx *chip, char * name, u32 dest)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) struct dsp_spos_instance * ins = chip->dsp_spos_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) struct dsp_scb_descriptor * desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (ins->nscb == DSP_MAX_SCB_DESC - 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) "dsp_spos: got no place for other SCB\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) index = find_free_scb_index (ins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) memset(&ins->scbs[index], 0, sizeof(ins->scbs[index]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) strcpy(ins->scbs[index].scb_name, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) ins->scbs[index].address = dest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) ins->scbs[index].index = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) ins->scbs[index].ref_count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) desc = (ins->scbs + index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) ins->scbs[index].scb_symbol = add_symbol (chip, name, dest, SYMBOL_PARAMETER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if (index > ins->scb_highest_frag_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) ins->scb_highest_frag_index = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) if (index == ins->nscb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) ins->nscb++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) return desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) static struct dsp_task_descriptor *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) _map_task_tree (struct snd_cs46xx *chip, char * name, u32 dest, u32 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) struct dsp_spos_instance * ins = chip->dsp_spos_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) struct dsp_task_descriptor * desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (ins->ntask == DSP_MAX_TASK_DESC - 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) "dsp_spos: got no place for other TASK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if (name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) strcpy(ins->tasks[ins->ntask].task_name, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) strcpy(ins->tasks[ins->ntask].task_name, "(NULL)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) ins->tasks[ins->ntask].address = dest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) ins->tasks[ins->ntask].size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) /* quick find in list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) ins->tasks[ins->ntask].index = ins->ntask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) desc = (ins->tasks + ins->ntask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) ins->ntask++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) add_symbol (chip,name,dest,SYMBOL_PARAMETER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) return desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) #define SCB_BYTES (0x10 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) struct dsp_scb_descriptor *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) cs46xx_dsp_create_scb (struct snd_cs46xx *chip, char * name, u32 * scb_data, u32 dest)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) struct dsp_scb_descriptor * desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) /* copy the data for resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) scb_data = kmemdup(scb_data, SCB_BYTES, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if (!scb_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) desc = _map_scb (chip,name,dest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) if (desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) desc->data = scb_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) _dsp_create_scb(chip,scb_data,dest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) dev_err(chip->card->dev, "dsp_spos: failed to map SCB\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) kfree(scb_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) return desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) static struct dsp_task_descriptor *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) cs46xx_dsp_create_task_tree (struct snd_cs46xx *chip, char * name, u32 * task_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) u32 dest, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) struct dsp_task_descriptor * desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) desc = _map_task_tree (chip,name,dest,size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) if (desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) desc->data = task_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) _dsp_create_task_tree(chip,task_data,dest,size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) dev_err(chip->card->dev, "dsp_spos: failed to map TASK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) return desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) int cs46xx_dsp_scb_and_task_init (struct snd_cs46xx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) struct dsp_spos_instance * ins = chip->dsp_spos_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) struct dsp_symbol_entry * fg_task_tree_header_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) struct dsp_symbol_entry * task_tree_header_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) struct dsp_symbol_entry * task_tree_thread;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) struct dsp_symbol_entry * null_algorithm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) struct dsp_symbol_entry * magic_snoop_task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) struct dsp_scb_descriptor * timing_master_scb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) struct dsp_scb_descriptor * codec_out_scb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) struct dsp_scb_descriptor * codec_in_scb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) struct dsp_scb_descriptor * src_task_scb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) struct dsp_scb_descriptor * master_mix_scb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) struct dsp_scb_descriptor * rear_mix_scb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) struct dsp_scb_descriptor * record_mix_scb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) struct dsp_scb_descriptor * write_back_scb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) struct dsp_scb_descriptor * vari_decimate_scb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) struct dsp_scb_descriptor * rear_codec_out_scb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) struct dsp_scb_descriptor * clfe_codec_out_scb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) struct dsp_scb_descriptor * magic_snoop_scb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) int fifo_addr, fifo_span, valid_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) static const struct dsp_spos_control_block sposcb = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) /* 0 */ HFG_TREE_SCB,HFG_STACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) /* 1 */ SPOSCB_ADDR,BG_TREE_SCB_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) /* 2 */ DSP_SPOS_DC,0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) /* 3 */ DSP_SPOS_DC,DSP_SPOS_DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) /* 4 */ 0,0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) /* 5 */ DSP_SPOS_UU,0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) /* 6 */ FG_TASK_HEADER_ADDR,0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) /* 7 */ 0,0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) /* 8 */ DSP_SPOS_UU,DSP_SPOS_DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) /* 9 */ 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) /* A */ 0,HFG_FIRST_EXECUTE_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) /* B */ DSP_SPOS_UU,DSP_SPOS_UU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) /* C */ DSP_SPOS_DC_DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) /* D */ DSP_SPOS_DC_DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) /* E */ DSP_SPOS_DC_DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) /* F */ DSP_SPOS_DC_DC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) cs46xx_dsp_create_task_tree(chip, "sposCB", (u32 *)&sposcb, SPOSCB_ADDR, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) null_algorithm = cs46xx_dsp_lookup_symbol(chip, "NULLALGORITHM", SYMBOL_CODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) if (null_algorithm == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) "dsp_spos: symbol NULLALGORITHM not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) fg_task_tree_header_code = cs46xx_dsp_lookup_symbol(chip, "FGTASKTREEHEADERCODE", SYMBOL_CODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) if (fg_task_tree_header_code == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) "dsp_spos: symbol FGTASKTREEHEADERCODE not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) task_tree_header_code = cs46xx_dsp_lookup_symbol(chip, "TASKTREEHEADERCODE", SYMBOL_CODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) if (task_tree_header_code == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) "dsp_spos: symbol TASKTREEHEADERCODE not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) task_tree_thread = cs46xx_dsp_lookup_symbol(chip, "TASKTREETHREAD", SYMBOL_CODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) if (task_tree_thread == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) "dsp_spos: symbol TASKTREETHREAD not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) magic_snoop_task = cs46xx_dsp_lookup_symbol(chip, "MAGICSNOOPTASK", SYMBOL_CODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) if (magic_snoop_task == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) "dsp_spos: symbol MAGICSNOOPTASK not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) /* create the null SCB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) static struct dsp_generic_scb null_scb = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) { 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) { 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) NULL_SCB_ADDR, NULL_SCB_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) 0,0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) 0,0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) null_scb.entry_point = null_algorithm->address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) ins->the_null_scb = cs46xx_dsp_create_scb(chip, "nullSCB", (u32 *)&null_scb, NULL_SCB_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) ins->the_null_scb->task_entry = null_algorithm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) ins->the_null_scb->sub_list_ptr = ins->the_null_scb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) ins->the_null_scb->next_scb_ptr = ins->the_null_scb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) ins->the_null_scb->parent_scb_ptr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) cs46xx_dsp_proc_register_scb_desc (chip,ins->the_null_scb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) /* setup foreground task tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) static struct dsp_task_tree_control_block fg_task_tree_hdr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) { FG_TASK_HEADER_ADDR | (DSP_SPOS_DC << 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) DSP_SPOS_DC_DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) DSP_SPOS_DC_DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) 0x0000,DSP_SPOS_DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) DSP_SPOS_DC, DSP_SPOS_DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) DSP_SPOS_DC_DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) DSP_SPOS_DC_DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) DSP_SPOS_DC_DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) DSP_SPOS_DC,DSP_SPOS_DC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) BG_TREE_SCB_ADDR,TIMINGMASTER_SCB_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) FG_TASK_HEADER_ADDR + TCBData,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) 4,0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) 1,0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) 2,SPOSCB_ADDR + HFGFlags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) 0,0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) FG_TASK_HEADER_ADDR + TCBContextBlk,FG_STACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) DSP_SPOS_DC,0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) DSP_SPOS_DC,DSP_SPOS_DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) DSP_SPOS_DC,DSP_SPOS_DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) DSP_SPOS_DC,DSP_SPOS_DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) DSP_SPOS_DC,DSP_SPOS_DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) DSP_SPOS_UU,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) DSP_SPOS_DCDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) FG_INTERVAL_TIMER_PERIOD,DSP_SPOS_UU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) 0,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) fg_task_tree_hdr.links.entry_point = fg_task_tree_header_code->address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) fg_task_tree_hdr.context_blk.stack0 = task_tree_thread->address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) cs46xx_dsp_create_task_tree(chip,"FGtaskTreeHdr",(u32 *)&fg_task_tree_hdr,FG_TASK_HEADER_ADDR,0x35);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) /* setup foreground task tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) static struct dsp_task_tree_control_block bg_task_tree_hdr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) { DSP_SPOS_DC_DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) DSP_SPOS_DC_DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) DSP_SPOS_DC_DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) DSP_SPOS_DC, DSP_SPOS_DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) DSP_SPOS_DC, DSP_SPOS_DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) DSP_SPOS_DC_DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) DSP_SPOS_DC_DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) DSP_SPOS_DC_DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) DSP_SPOS_DC,DSP_SPOS_DC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) NULL_SCB_ADDR,NULL_SCB_ADDR, /* Set up the background to do nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) BG_TREE_SCB_ADDR + TCBData,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) 9999,0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) 0,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) 0,SPOSCB_ADDR + HFGFlags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) 0,0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) BG_TREE_SCB_ADDR + TCBContextBlk,BG_STACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) DSP_SPOS_DC,0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) DSP_SPOS_DC,DSP_SPOS_DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) DSP_SPOS_DC,DSP_SPOS_DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) DSP_SPOS_DC,DSP_SPOS_DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) DSP_SPOS_DC,DSP_SPOS_DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) DSP_SPOS_UU,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) DSP_SPOS_DCDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) DSP_SPOS_DCDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) BG_INTERVAL_TIMER_PERIOD,DSP_SPOS_UU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) 0,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) bg_task_tree_hdr.links.entry_point = task_tree_header_code->address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) bg_task_tree_hdr.context_blk.stack0 = task_tree_thread->address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) cs46xx_dsp_create_task_tree(chip,"BGtaskTreeHdr",(u32 *)&bg_task_tree_hdr,BG_TREE_SCB_ADDR,0x35);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) /* create timing master SCB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) timing_master_scb = cs46xx_dsp_create_timing_master_scb(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) /* create the CODEC output task */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) codec_out_scb = cs46xx_dsp_create_codec_out_scb(chip,"CodecOutSCB_I",0x0010,0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) MASTERMIX_SCB_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) CODECOUT_SCB_ADDR,timing_master_scb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) SCB_ON_PARENT_SUBLIST_SCB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) if (!codec_out_scb) goto _fail_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) /* create the master mix SCB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) master_mix_scb = cs46xx_dsp_create_mix_only_scb(chip,"MasterMixSCB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) MIX_SAMPLE_BUF1,MASTERMIX_SCB_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) codec_out_scb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) SCB_ON_PARENT_SUBLIST_SCB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) ins->master_mix_scb = master_mix_scb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) if (!master_mix_scb) goto _fail_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) /* create codec in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) codec_in_scb = cs46xx_dsp_create_codec_in_scb(chip,"CodecInSCB",0x0010,0x00A0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) CODEC_INPUT_BUF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) CODECIN_SCB_ADDR,codec_out_scb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) SCB_ON_PARENT_NEXT_SCB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) if (!codec_in_scb) goto _fail_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) ins->codec_in_scb = codec_in_scb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) /* create write back scb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) write_back_scb = cs46xx_dsp_create_mix_to_ostream_scb(chip,"WriteBackSCB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) WRITE_BACK_BUF1,WRITE_BACK_SPB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) WRITEBACK_SCB_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) timing_master_scb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) SCB_ON_PARENT_NEXT_SCB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) if (!write_back_scb) goto _fail_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) static struct dsp_mix2_ostream_spb mix2_ostream_spb = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) 0x00020000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) if (!cs46xx_dsp_create_task_tree(chip, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) (u32 *)&mix2_ostream_spb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) WRITE_BACK_SPB, 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) goto _fail_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) /* input sample converter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) vari_decimate_scb = cs46xx_dsp_create_vari_decimate_scb(chip,"VariDecimateSCB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) VARI_DECIMATE_BUF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) VARI_DECIMATE_BUF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) VARIDECIMATE_SCB_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) write_back_scb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) SCB_ON_PARENT_SUBLIST_SCB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) if (!vari_decimate_scb) goto _fail_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) /* create the record mixer SCB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) record_mix_scb = cs46xx_dsp_create_mix_only_scb(chip,"RecordMixerSCB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) MIX_SAMPLE_BUF2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) RECORD_MIXER_SCB_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) vari_decimate_scb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) SCB_ON_PARENT_SUBLIST_SCB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) ins->record_mixer_scb = record_mix_scb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) if (!record_mix_scb) goto _fail_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) if (snd_BUG_ON(chip->nr_ac97_codecs != 1 && chip->nr_ac97_codecs != 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) goto _fail_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) if (chip->nr_ac97_codecs == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) /* output on slot 5 and 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) on primary CODEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) fifo_addr = 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) fifo_span = 0x60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) /* enable slot 5 and 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) valid_slots |= ACOSV_SLV5 | ACOSV_SLV11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) /* output on slot 7 and 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) on secondary CODEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) fifo_addr = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) fifo_span = 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) /* enable slot 7 and 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) valid_slots |= ACOSV_SLV7 | ACOSV_SLV8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) /* create CODEC tasklet for rear speakers output*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) rear_codec_out_scb = cs46xx_dsp_create_codec_out_scb(chip,"CodecOutSCB_Rear",fifo_span,fifo_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) REAR_MIXER_SCB_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) REAR_CODECOUT_SCB_ADDR,codec_in_scb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) SCB_ON_PARENT_NEXT_SCB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) if (!rear_codec_out_scb) goto _fail_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) /* create the rear PCM channel mixer SCB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) rear_mix_scb = cs46xx_dsp_create_mix_only_scb(chip,"RearMixerSCB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) MIX_SAMPLE_BUF3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) REAR_MIXER_SCB_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) rear_codec_out_scb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) SCB_ON_PARENT_SUBLIST_SCB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) ins->rear_mix_scb = rear_mix_scb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) if (!rear_mix_scb) goto _fail_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) if (chip->nr_ac97_codecs == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) /* create CODEC tasklet for rear Center/LFE output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) slot 6 and 9 on secondary CODEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) clfe_codec_out_scb = cs46xx_dsp_create_codec_out_scb(chip,"CodecOutSCB_CLFE",0x0030,0x0030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) CLFE_MIXER_SCB_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) CLFE_CODEC_SCB_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) rear_codec_out_scb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) SCB_ON_PARENT_NEXT_SCB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) if (!clfe_codec_out_scb) goto _fail_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) /* create the rear PCM channel mixer SCB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) ins->center_lfe_mix_scb = cs46xx_dsp_create_mix_only_scb(chip,"CLFEMixerSCB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) MIX_SAMPLE_BUF4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) CLFE_MIXER_SCB_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) clfe_codec_out_scb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) SCB_ON_PARENT_SUBLIST_SCB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) if (!ins->center_lfe_mix_scb) goto _fail_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) /* enable slot 6 and 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) valid_slots |= ACOSV_SLV6 | ACOSV_SLV9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) clfe_codec_out_scb = rear_codec_out_scb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) ins->center_lfe_mix_scb = rear_mix_scb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) /* enable slots depending on CODEC configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) /* the magic snooper */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) magic_snoop_scb = cs46xx_dsp_create_magic_snoop_scb (chip,"MagicSnoopSCB_I",OUTPUTSNOOP_SCB_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) OUTPUT_SNOOP_BUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) codec_out_scb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) clfe_codec_out_scb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) SCB_ON_PARENT_NEXT_SCB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) if (!magic_snoop_scb) goto _fail_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) ins->ref_snoop_scb = magic_snoop_scb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) /* SP IO access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) if (!cs46xx_dsp_create_spio_write_scb(chip,"SPIOWriteSCB",SPIOWRITE_SCB_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) magic_snoop_scb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) SCB_ON_PARENT_NEXT_SCB))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) goto _fail_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) /* SPDIF input sampel rate converter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) src_task_scb = cs46xx_dsp_create_src_task_scb(chip,"SrcTaskSCB_SPDIFI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) ins->spdif_in_sample_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) SRC_OUTPUT_BUF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) SRC_DELAY_BUF1,SRCTASK_SCB_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) master_mix_scb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) SCB_ON_PARENT_SUBLIST_SCB,1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) if (!src_task_scb) goto _fail_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) cs46xx_src_unlink(chip,src_task_scb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) /* NOTE: when we now how to detect the SPDIF input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) sample rate we will use this SRC to adjust it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) ins->spdif_in_src = src_task_scb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) cs46xx_dsp_async_init(chip,timing_master_scb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) _fail_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) dev_err(chip->card->dev, "dsp_spos: failed to setup SCB's in DSP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) static int cs46xx_dsp_async_init (struct snd_cs46xx *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) struct dsp_scb_descriptor * fg_entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) struct dsp_spos_instance * ins = chip->dsp_spos_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) struct dsp_symbol_entry * s16_async_codec_input_task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) struct dsp_symbol_entry * spdifo_task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) struct dsp_symbol_entry * spdifi_task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) struct dsp_scb_descriptor * spdifi_scb_desc, * spdifo_scb_desc, * async_codec_scb_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) s16_async_codec_input_task = cs46xx_dsp_lookup_symbol(chip, "S16_ASYNCCODECINPUTTASK", SYMBOL_CODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) if (s16_async_codec_input_task == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) "dsp_spos: symbol S16_ASYNCCODECINPUTTASK not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) spdifo_task = cs46xx_dsp_lookup_symbol(chip, "SPDIFOTASK", SYMBOL_CODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) if (spdifo_task == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) "dsp_spos: symbol SPDIFOTASK not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) spdifi_task = cs46xx_dsp_lookup_symbol(chip, "SPDIFITASK", SYMBOL_CODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) if (spdifi_task == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) "dsp_spos: symbol SPDIFITASK not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) /* 0xBC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) struct dsp_spdifoscb spdifo_scb = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) /* 0 */ DSP_SPOS_UUUU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) /* 1 */ 0xb0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) /* 2 */ 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) /* 3 */ 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) /* 4 */ 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) /* NOTE: the SPDIF output task read samples in mono
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) format, the AsynchFGTxSCB task writes to buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) in stereo format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) /* 5 */ RSCONFIG_SAMPLE_16MONO + RSCONFIG_MODULO_256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) /* 6 */ ( SPDIFO_IP_OUTPUT_BUFFER1 << 0x10 ) | 0xFFFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) /* 7 */ 0,0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) /* 8 */ 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) /* 9 */ FG_TASK_HEADER_ADDR, NULL_SCB_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) /* A */ spdifo_task->address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) SPDIFO_SCB_INST + SPDIFOFIFOPointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) /* B */ 0x0040, /*DSP_SPOS_UUUU,*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) /* C */ 0x20ff, /*DSP_SPOS_UUUU,*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) /* D */ 0x804c,0, /* SPDIFOFIFOPointer:SPDIFOStatRegAddr; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) /* E */ 0x0108,0x0001, /* SPDIFOStMoFormat:SPDIFOFIFOBaseAddr; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) /* F */ DSP_SPOS_UUUU /* SPDIFOFree; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) /* 0xBB0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) struct dsp_spdifiscb spdifi_scb = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) /* 0 */ DSP_SPOS_UULO,DSP_SPOS_UUHI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) /* 1 */ 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) /* 2 */ 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) /* 3 */ 1,4000, /* SPDIFICountLimit SPDIFICount */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) /* 4 */ DSP_SPOS_UUUU, /* SPDIFIStatusData */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) /* 5 */ 0,DSP_SPOS_UUHI, /* StatusData, Free4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) /* 6 */ DSP_SPOS_UUUU, /* Free3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) /* 7 */ DSP_SPOS_UU,DSP_SPOS_DC, /* Free2 BitCount*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) /* 8 */ DSP_SPOS_UUUU, /* TempStatus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) /* 9 */ SPDIFO_SCB_INST, NULL_SCB_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) /* A */ spdifi_task->address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) SPDIFI_SCB_INST + SPDIFIFIFOPointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) /* NOTE: The SPDIF input task write the sample in mono
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) format from the HW FIFO, the AsynchFGRxSCB task reads
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) them in stereo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) /* B */ RSCONFIG_SAMPLE_16MONO + RSCONFIG_MODULO_128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) /* C */ (SPDIFI_IP_OUTPUT_BUFFER1 << 0x10) | 0xFFFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) /* D */ 0x8048,0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) /* E */ 0x01f0,0x0001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) /* F */ DSP_SPOS_UUUU /* SPDIN_STATUS monitor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) /* 0xBA0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) struct dsp_async_codec_input_scb async_codec_input_scb = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) /* 0 */ DSP_SPOS_UUUU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) /* 1 */ 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) /* 2 */ 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) /* 3 */ 1,4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) /* 4 */ 0x0118,0x0001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) /* 5 */ RSCONFIG_SAMPLE_16MONO + RSCONFIG_MODULO_64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) /* 6 */ (ASYNC_IP_OUTPUT_BUFFER1 << 0x10) | 0xFFFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) /* 7 */ DSP_SPOS_UU,0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) /* 8 */ DSP_SPOS_UUUU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) /* 9 */ SPDIFI_SCB_INST,NULL_SCB_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) /* A */ s16_async_codec_input_task->address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) HFG_TREE_SCB + AsyncCIOFIFOPointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) /* B */ RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) /* C */ (ASYNC_IP_OUTPUT_BUFFER1 << 0x10), /*(ASYNC_IP_OUTPUT_BUFFER1 << 0x10) | 0xFFFC,*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) #ifdef UseASER1Input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) /* short AsyncCIFIFOPointer:AsyncCIStatRegAddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) Init. 0000:8042: for ASER1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) 0000:8044: for ASER2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) /* D */ 0x8042,0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) /* short AsyncCIStMoFormat:AsyncCIFIFOBaseAddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) Init 1 stero:8050 ASER1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) Init 0 mono:8070 ASER2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) Init 1 Stereo : 0100 ASER1 (Set by script) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) /* E */ 0x0100,0x0001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) #ifdef UseASER2Input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) /* short AsyncCIFIFOPointer:AsyncCIStatRegAddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) Init. 0000:8042: for ASER1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) 0000:8044: for ASER2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) /* D */ 0x8044,0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) /* short AsyncCIStMoFormat:AsyncCIFIFOBaseAddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) Init 1 stero:8050 ASER1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) Init 0 mono:8070 ASER2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) Init 1 Stereo : 0100 ASER1 (Set by script) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) /* E */ 0x0110,0x0001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) /* short AsyncCIOutputBufModulo:AsyncCIFree;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) AsyncCIOutputBufModulo: The modulo size for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) the output buffer of this task */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) /* F */ 0, /* DSP_SPOS_UUUU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) spdifo_scb_desc = cs46xx_dsp_create_scb(chip,"SPDIFOSCB",(u32 *)&spdifo_scb,SPDIFO_SCB_INST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) if (snd_BUG_ON(!spdifo_scb_desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) spdifi_scb_desc = cs46xx_dsp_create_scb(chip,"SPDIFISCB",(u32 *)&spdifi_scb,SPDIFI_SCB_INST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) if (snd_BUG_ON(!spdifi_scb_desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) async_codec_scb_desc = cs46xx_dsp_create_scb(chip,"AsynCodecInputSCB",(u32 *)&async_codec_input_scb, HFG_TREE_SCB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) if (snd_BUG_ON(!async_codec_scb_desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) async_codec_scb_desc->parent_scb_ptr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) async_codec_scb_desc->next_scb_ptr = spdifi_scb_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) async_codec_scb_desc->sub_list_ptr = ins->the_null_scb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) async_codec_scb_desc->task_entry = s16_async_codec_input_task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) spdifi_scb_desc->parent_scb_ptr = async_codec_scb_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) spdifi_scb_desc->next_scb_ptr = spdifo_scb_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) spdifi_scb_desc->sub_list_ptr = ins->the_null_scb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) spdifi_scb_desc->task_entry = spdifi_task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) spdifo_scb_desc->parent_scb_ptr = spdifi_scb_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) spdifo_scb_desc->next_scb_ptr = fg_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) spdifo_scb_desc->sub_list_ptr = ins->the_null_scb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) spdifo_scb_desc->task_entry = spdifo_task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) /* this one is faked, as the parnet of SPDIFO task
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) is the FG task tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) fg_entry->parent_scb_ptr = spdifo_scb_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) /* for proc fs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) cs46xx_dsp_proc_register_scb_desc (chip,spdifo_scb_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) cs46xx_dsp_proc_register_scb_desc (chip,spdifi_scb_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) cs46xx_dsp_proc_register_scb_desc (chip,async_codec_scb_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) /* Async MASTER ENABLE, affects both SPDIF input and output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) snd_cs46xx_pokeBA0(chip, BA0_ASER_MASTER, 0x1 );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) static void cs46xx_dsp_disable_spdif_hw (struct snd_cs46xx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) struct dsp_spos_instance * ins = chip->dsp_spos_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) /* set SPDIF output FIFO slot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) snd_cs46xx_pokeBA0(chip, BA0_ASER_FADDR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) /* SPDIF output MASTER ENABLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) cs46xx_poke_via_dsp (chip,SP_SPDOUT_CONTROL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) /* right and left validate bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) /*cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV, ins->spdif_csuv_default);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) /* clear fifo pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) cs46xx_poke_via_dsp (chip,SP_SPDIN_FIFOPTR, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) /* monitor state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) ins->spdif_status_out &= ~DSP_SPDIF_STATUS_HW_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) int cs46xx_dsp_enable_spdif_hw (struct snd_cs46xx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) struct dsp_spos_instance * ins = chip->dsp_spos_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) /* if hw-ctrl already enabled, turn off to reset logic ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) cs46xx_dsp_disable_spdif_hw (chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) /* set SPDIF output FIFO slot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) snd_cs46xx_pokeBA0(chip, BA0_ASER_FADDR, ( 0x8000 | ((SP_SPDOUT_FIFO >> 4) << 4) ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) /* SPDIF output MASTER ENABLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) cs46xx_poke_via_dsp (chip,SP_SPDOUT_CONTROL, 0x80000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) /* right and left validate bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV, ins->spdif_csuv_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) /* monitor state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) ins->spdif_status_out |= DSP_SPDIF_STATUS_HW_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) int cs46xx_dsp_enable_spdif_in (struct snd_cs46xx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) struct dsp_spos_instance * ins = chip->dsp_spos_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) /* turn on amplifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) chip->active_ctrl(chip, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) chip->amplifier_ctrl(chip, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) if (snd_BUG_ON(ins->asynch_rx_scb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) if (snd_BUG_ON(!ins->spdif_in_src))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) mutex_lock(&chip->spos_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) if ( ! (ins->spdif_status_out & DSP_SPDIF_STATUS_INPUT_CTRL_ENABLED) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) /* time countdown enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) cs46xx_poke_via_dsp (chip,SP_ASER_COUNTDOWN, 0x80000005);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) /* NOTE: 80000005 value is just magic. With all values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) that I've tested this one seem to give the best result.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) Got no explication why. (Benny) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) /* SPDIF input MASTER ENABLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) cs46xx_poke_via_dsp (chip,SP_SPDIN_CONTROL, 0x800003ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) ins->spdif_status_out |= DSP_SPDIF_STATUS_INPUT_CTRL_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) /* create and start the asynchronous receiver SCB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) ins->asynch_rx_scb = cs46xx_dsp_create_asynch_fg_rx_scb(chip,"AsynchFGRxSCB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) ASYNCRX_SCB_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) SPDIFI_SCB_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) SPDIFI_IP_OUTPUT_BUFFER1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) ins->spdif_in_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) SCB_ON_PARENT_SUBLIST_SCB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) /* reset SPDIF input sample buffer pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) /*snd_cs46xx_poke (chip, (SPDIFI_SCB_INST + 0x0c) << 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) (SPDIFI_IP_OUTPUT_BUFFER1 << 0x10) | 0xFFFC);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) /* reset FIFO ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) /*cs46xx_poke_via_dsp (chip,SP_SPDIN_FIFOPTR, 0x0);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) cs46xx_src_link(chip,ins->spdif_in_src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) /* unmute SRC volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) cs46xx_dsp_scb_set_volume (chip,ins->spdif_in_src,0x7fff,0x7fff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) /* set SPDIF input sample rate and unmute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) NOTE: only 48khz support for SPDIF input this time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) /* cs46xx_dsp_set_src_sample_rate(chip,ins->spdif_in_src,48000); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) /* monitor state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) ins->spdif_status_in = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) mutex_unlock(&chip->spos_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) int cs46xx_dsp_disable_spdif_in (struct snd_cs46xx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) struct dsp_spos_instance * ins = chip->dsp_spos_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) if (snd_BUG_ON(!ins->asynch_rx_scb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) if (snd_BUG_ON(!ins->spdif_in_src))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) mutex_lock(&chip->spos_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) /* Remove the asynchronous receiver SCB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) cs46xx_dsp_remove_scb (chip,ins->asynch_rx_scb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) ins->asynch_rx_scb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) cs46xx_src_unlink(chip,ins->spdif_in_src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) /* monitor state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) ins->spdif_status_in = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) mutex_unlock(&chip->spos_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) /* restore amplifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) chip->active_ctrl(chip, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) chip->amplifier_ctrl(chip, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) int cs46xx_dsp_enable_pcm_capture (struct snd_cs46xx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) struct dsp_spos_instance * ins = chip->dsp_spos_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) if (snd_BUG_ON(ins->pcm_input))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) if (snd_BUG_ON(!ins->ref_snoop_scb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) mutex_lock(&chip->spos_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) ins->pcm_input = cs46xx_add_record_source(chip,ins->ref_snoop_scb,PCMSERIALIN_PCM_SCB_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) "PCMSerialInput_Wave");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) mutex_unlock(&chip->spos_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) int cs46xx_dsp_disable_pcm_capture (struct snd_cs46xx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) struct dsp_spos_instance * ins = chip->dsp_spos_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) if (snd_BUG_ON(!ins->pcm_input))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) mutex_lock(&chip->spos_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) cs46xx_dsp_remove_scb (chip,ins->pcm_input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) ins->pcm_input = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) mutex_unlock(&chip->spos_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) int cs46xx_dsp_enable_adc_capture (struct snd_cs46xx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) struct dsp_spos_instance * ins = chip->dsp_spos_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) if (snd_BUG_ON(ins->adc_input))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) if (snd_BUG_ON(!ins->codec_in_scb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) mutex_lock(&chip->spos_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) ins->adc_input = cs46xx_add_record_source(chip,ins->codec_in_scb,PCMSERIALIN_SCB_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) "PCMSerialInput_ADC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) mutex_unlock(&chip->spos_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) int cs46xx_dsp_disable_adc_capture (struct snd_cs46xx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) struct dsp_spos_instance * ins = chip->dsp_spos_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) if (snd_BUG_ON(!ins->adc_input))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) mutex_lock(&chip->spos_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) cs46xx_dsp_remove_scb (chip,ins->adc_input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) ins->adc_input = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) mutex_unlock(&chip->spos_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) int cs46xx_poke_via_dsp (struct snd_cs46xx *chip, u32 address, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) /* santiy check the parameters. (These numbers are not 100% correct. They are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) a rough guess from looking at the controller spec.) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) if (address < 0x8000 || address >= 0x9000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) /* initialize the SP_IO_WRITE SCB with the data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) temp = ( address << 16 ) | ( address & 0x0000FFFF); /* offset 0 <-- address2 : address1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) snd_cs46xx_poke(chip,( SPIOWRITE_SCB_ADDR << 2), temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) snd_cs46xx_poke(chip,((SPIOWRITE_SCB_ADDR + 1) << 2), data); /* offset 1 <-- data1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) snd_cs46xx_poke(chip,((SPIOWRITE_SCB_ADDR + 2) << 2), data); /* offset 1 <-- data2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) /* Poke this location to tell the task to start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) snd_cs46xx_poke(chip,((SPIOWRITE_SCB_ADDR + 6) << 2), SPIOWRITE_SCB_ADDR << 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) /* Verify that the task ran */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) for (i=0; i<25; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) udelay(125);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) temp = snd_cs46xx_peek(chip,((SPIOWRITE_SCB_ADDR + 6) << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) if (temp == 0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) if (i == 25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) "dsp_spos: SPIOWriteTask not responding\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) int cs46xx_dsp_set_dac_volume (struct snd_cs46xx * chip, u16 left, u16 right)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) struct dsp_spos_instance * ins = chip->dsp_spos_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) struct dsp_scb_descriptor * scb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) mutex_lock(&chip->spos_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) /* main output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) scb = ins->master_mix_scb->sub_list_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) while (scb != ins->the_null_scb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) cs46xx_dsp_scb_set_volume (chip,scb,left,right);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) scb = scb->next_scb_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) /* rear output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) scb = ins->rear_mix_scb->sub_list_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) while (scb != ins->the_null_scb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) cs46xx_dsp_scb_set_volume (chip,scb,left,right);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) scb = scb->next_scb_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) ins->dac_volume_left = left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) ins->dac_volume_right = right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) mutex_unlock(&chip->spos_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) int cs46xx_dsp_set_iec958_volume (struct snd_cs46xx * chip, u16 left, u16 right)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) struct dsp_spos_instance * ins = chip->dsp_spos_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) mutex_lock(&chip->spos_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) if (ins->asynch_rx_scb != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) cs46xx_dsp_scb_set_volume (chip,ins->asynch_rx_scb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) left,right);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) ins->spdif_input_volume_left = left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) ins->spdif_input_volume_right = right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) mutex_unlock(&chip->spos_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) int cs46xx_dsp_resume(struct snd_cs46xx * chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) struct dsp_spos_instance * ins = chip->dsp_spos_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) /* clear parameter, sample and code areas */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) snd_cs46xx_clear_BA1(chip, DSP_PARAMETER_BYTE_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) DSP_PARAMETER_BYTE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) snd_cs46xx_clear_BA1(chip, DSP_SAMPLE_BYTE_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) DSP_SAMPLE_BYTE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) snd_cs46xx_clear_BA1(chip, DSP_CODE_BYTE_OFFSET, DSP_CODE_BYTE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) for (i = 0; i < ins->nmodules; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) struct dsp_module_desc *module = &ins->modules[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) struct dsp_segment_desc *seg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) u32 doffset, dsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) seg = get_segment_desc(module, SEGTYPE_SP_PARAMETER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) err = dsp_load_parameter(chip, seg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) seg = get_segment_desc(module, SEGTYPE_SP_SAMPLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) err = dsp_load_sample(chip, seg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) seg = get_segment_desc(module, SEGTYPE_SP_PROGRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) if (!seg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) doffset = seg->offset * 4 + module->load_address * 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) + DSP_CODE_BYTE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) dsize = seg->size * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) err = snd_cs46xx_download(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) ins->code.data + module->load_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) doffset, dsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) for (i = 0; i < ins->ntask; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) struct dsp_task_descriptor *t = &ins->tasks[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) _dsp_create_task_tree(chip, t->data, t->address, t->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) for (i = 0; i < ins->nscb; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) struct dsp_scb_descriptor *s = &ins->scbs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) if (s->deleted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) _dsp_create_scb(chip, s->data, s->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) for (i = 0; i < ins->nscb; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) struct dsp_scb_descriptor *s = &ins->scbs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) if (s->deleted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) if (s->updated)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) cs46xx_dsp_spos_update_scb(chip, s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) if (s->volume_set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) cs46xx_dsp_scb_set_volume(chip, s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) s->volume[0], s->volume[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) if (ins->spdif_status_out & DSP_SPDIF_STATUS_HW_ENABLED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) cs46xx_dsp_enable_spdif_hw(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) snd_cs46xx_poke(chip, (ins->ref_snoop_scb->address + 2) << 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) (OUTPUT_SNOOP_BUFFER + 0x10) << 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) if (ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) cs46xx_poke_via_dsp(chip, SP_SPDOUT_CSUV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) ins->spdif_csuv_stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) if (chip->dsp_spos_instance->spdif_status_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) cs46xx_poke_via_dsp(chip, SP_ASER_COUNTDOWN, 0x80000005);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) cs46xx_poke_via_dsp(chip, SP_SPDIN_CONTROL, 0x800003ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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