Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  The driver for the Cirrus Logic's Sound Fusion CS46XX based soundcards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #ifndef __CS46XX_LIB_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define __CS46XX_LIB_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *  constants
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define CS46XX_BA0_SIZE		  0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define CS46XX_BA1_DATA0_SIZE 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define CS46XX_BA1_DATA1_SIZE 0x3800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define CS46XX_BA1_PRG_SIZE	  0x7000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define CS46XX_BA1_REG_SIZE	  0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #ifdef CONFIG_SND_CS46XX_NEW_DSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define CS46XX_MIN_PERIOD_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define CS46XX_MAX_PERIOD_SIZE 1024*1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define CS46XX_MIN_PERIOD_SIZE 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define CS46XX_MAX_PERIOD_SIZE 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define CS46XX_FRAGS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /* #define CS46XX_BUFFER_SIZE CS46XX_MAX_PERIOD_SIZE * CS46XX_FRAGS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define SCB_NO_PARENT             0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define SCB_ON_PARENT_NEXT_SCB    1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define SCB_ON_PARENT_SUBLIST_SCB 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) /* 3*1024 parameter, 3.5*1024 sample, 2*3.5*1024 code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define BA1_DWORD_SIZE		(13 * 1024 + 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define BA1_MEMORY_COUNT	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  *  common I/O routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) static inline void snd_cs46xx_poke(struct snd_cs46xx *chip, unsigned long reg, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	unsigned int bank = reg >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	unsigned int offset = reg & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	if (bank == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		printk(KERN_DEBUG "snd_cs46xx_poke: %04X - %08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		       reg >> 2,val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	writel(val, chip->region.idx[bank+1].remap_addr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) static inline unsigned int snd_cs46xx_peek(struct snd_cs46xx *chip, unsigned long reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	unsigned int bank = reg >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	unsigned int offset = reg & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	return readl(chip->region.idx[bank+1].remap_addr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) static inline void snd_cs46xx_pokeBA0(struct snd_cs46xx *chip, unsigned long offset, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	writel(val, chip->region.name.ba0.remap_addr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) static inline unsigned int snd_cs46xx_peekBA0(struct snd_cs46xx *chip, unsigned long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	return readl(chip->region.name.ba0.remap_addr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) struct dsp_spos_instance *cs46xx_dsp_spos_create (struct snd_cs46xx * chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) void cs46xx_dsp_spos_destroy (struct snd_cs46xx * chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) int cs46xx_dsp_load_module (struct snd_cs46xx * chip, struct dsp_module_desc * module);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) int cs46xx_dsp_resume(struct snd_cs46xx * chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) struct dsp_symbol_entry *cs46xx_dsp_lookup_symbol (struct snd_cs46xx * chip, char * symbol_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 						   int symbol_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #ifdef CONFIG_SND_PROC_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) int cs46xx_dsp_proc_init (struct snd_card *card, struct snd_cs46xx *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) int cs46xx_dsp_proc_done (struct snd_cs46xx *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define cs46xx_dsp_proc_init(card, chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define cs46xx_dsp_proc_done(chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) int cs46xx_dsp_scb_and_task_init (struct snd_cs46xx *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) int snd_cs46xx_download (struct snd_cs46xx *chip, u32 *src, unsigned long offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 			 unsigned long len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) int snd_cs46xx_clear_BA1(struct snd_cs46xx *chip, unsigned long offset, unsigned long len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) int cs46xx_dsp_enable_spdif_out (struct snd_cs46xx *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) int cs46xx_dsp_enable_spdif_hw (struct snd_cs46xx *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) int cs46xx_dsp_disable_spdif_out (struct snd_cs46xx *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) int cs46xx_dsp_enable_spdif_in (struct snd_cs46xx *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) int cs46xx_dsp_disable_spdif_in (struct snd_cs46xx *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) int cs46xx_dsp_enable_pcm_capture (struct snd_cs46xx *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int cs46xx_dsp_disable_pcm_capture (struct snd_cs46xx *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int cs46xx_dsp_enable_adc_capture (struct snd_cs46xx *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int cs46xx_dsp_disable_adc_capture (struct snd_cs46xx *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int cs46xx_poke_via_dsp (struct snd_cs46xx *chip, u32 address, u32 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct dsp_scb_descriptor * cs46xx_dsp_create_scb (struct snd_cs46xx *chip, char * name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 						   u32 * scb_data, u32 dest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #ifdef CONFIG_SND_PROC_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) void cs46xx_dsp_proc_free_scb_desc (struct dsp_scb_descriptor * scb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) void cs46xx_dsp_proc_register_scb_desc (struct snd_cs46xx *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 					struct dsp_scb_descriptor * scb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define cs46xx_dsp_proc_free_scb_desc(scb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define cs46xx_dsp_proc_register_scb_desc(chip, scb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct dsp_scb_descriptor * cs46xx_dsp_create_timing_master_scb (struct snd_cs46xx *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct dsp_scb_descriptor *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) cs46xx_dsp_create_codec_out_scb(struct snd_cs46xx * chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 				char * codec_name, u16 channel_disp, u16 fifo_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 				u16 child_scb_addr, u32 dest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 				struct dsp_scb_descriptor * parent_scb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 				int scb_child_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct dsp_scb_descriptor *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) cs46xx_dsp_create_codec_in_scb(struct snd_cs46xx * chip, char * codec_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			       u16 channel_disp, u16 fifo_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			       u16 sample_buffer_addr, u32 dest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 			       struct dsp_scb_descriptor * parent_scb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 			       int scb_child_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) void cs46xx_dsp_remove_scb (struct snd_cs46xx *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			    struct dsp_scb_descriptor * scb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct dsp_scb_descriptor *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) cs46xx_dsp_create_codec_in_scb(struct snd_cs46xx * chip, char * codec_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 			       u16 channel_disp, u16 fifo_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			       u16 sample_buffer_addr, u32 dest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			       struct dsp_scb_descriptor * parent_scb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			       int scb_child_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct dsp_scb_descriptor *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) cs46xx_dsp_create_src_task_scb(struct snd_cs46xx * chip, char * scb_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 			       int sample_rate, u16 src_buffer_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 			       u16 src_delay_buffer_addr, u32 dest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 			       struct dsp_scb_descriptor * parent_scb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 			       int scb_child_type, int pass_through);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct dsp_scb_descriptor *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) cs46xx_dsp_create_mix_only_scb(struct snd_cs46xx * chip, char * scb_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			       u16 mix_buffer_addr, u32 dest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 			       struct dsp_scb_descriptor * parent_scb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			       int scb_child_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct dsp_scb_descriptor *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) cs46xx_dsp_create_vari_decimate_scb(struct snd_cs46xx * chip, char * scb_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 				    u16 vari_buffer_addr0, u16 vari_buffer_addr1, u32 dest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 				    struct dsp_scb_descriptor * parent_scb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 				    int scb_child_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct dsp_scb_descriptor *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) cs46xx_dsp_create_asynch_fg_rx_scb(struct snd_cs46xx * chip, char * scb_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 				   u32 dest, u16 hfg_scb_address, u16 asynch_buffer_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 				   struct dsp_scb_descriptor * parent_scb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 				   int scb_child_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct dsp_scb_descriptor *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) cs46xx_dsp_create_spio_write_scb(struct snd_cs46xx * chip, char * scb_name, u32 dest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 				 struct dsp_scb_descriptor * parent_scb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 				 int scb_child_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct dsp_scb_descriptor *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) cs46xx_dsp_create_mix_to_ostream_scb(struct snd_cs46xx * chip, char * scb_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 				     u16 mix_buffer_addr, u16 writeback_spb, u32 dest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 				     struct dsp_scb_descriptor * parent_scb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 				     int scb_child_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct dsp_scb_descriptor *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) cs46xx_dsp_create_magic_snoop_scb(struct snd_cs46xx * chip, char * scb_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 				  u32 dest, u16 snoop_buffer_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 				  struct dsp_scb_descriptor * snoop_scb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 				  struct dsp_scb_descriptor * parent_scb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 				  int scb_child_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct dsp_pcm_channel_descriptor *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) cs46xx_dsp_create_pcm_channel (struct snd_cs46xx * chip, u32 sample_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 			       void * private_data, u32 hw_dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 			       int pcm_channel_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) void cs46xx_dsp_destroy_pcm_channel (struct snd_cs46xx * chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 				     struct dsp_pcm_channel_descriptor * pcm_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) int cs46xx_dsp_pcm_unlink (struct snd_cs46xx * chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			   struct dsp_pcm_channel_descriptor * pcm_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) int cs46xx_dsp_pcm_link (struct snd_cs46xx * chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 			 struct dsp_pcm_channel_descriptor * pcm_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct dsp_scb_descriptor *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) cs46xx_add_record_source (struct snd_cs46xx *chip, struct dsp_scb_descriptor * source,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 			  u16 addr, char * scb_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int cs46xx_src_unlink(struct snd_cs46xx *chip, struct dsp_scb_descriptor * src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int cs46xx_src_link(struct snd_cs46xx *chip, struct dsp_scb_descriptor * src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int cs46xx_iec958_pre_open (struct snd_cs46xx *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int cs46xx_iec958_post_close (struct snd_cs46xx *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) int cs46xx_dsp_pcm_channel_set_period (struct snd_cs46xx * chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 				       struct dsp_pcm_channel_descriptor * pcm_channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 				       int period_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int cs46xx_dsp_pcm_ostream_set_period (struct snd_cs46xx * chip, int period_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int cs46xx_dsp_set_dac_volume (struct snd_cs46xx * chip, u16 left, u16 right);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int cs46xx_dsp_set_iec958_volume (struct snd_cs46xx * chip, u16 left, u16 right);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #endif /* __CS46XX_LIB_H__ */