^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __SOUND_CS46XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __SOUND_CS46XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Cirrus Logic, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Definitions for Cirrus Logic CS46xx chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <sound/pcm-indirect.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <sound/rawmidi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <sound/ac97_codec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "cs46xx_dsp_spos.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Direct registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * The following define the offsets of the registers accessed via base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * register zero on the CS46xx part.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define BA0_HISR 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define BA0_HSR0 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define BA0_HICR 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define BA0_DMSR 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define BA0_HSAR 0x00000110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define BA0_HDAR 0x00000114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define BA0_HDMR 0x00000118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define BA0_HDCR 0x0000011C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define BA0_PFMC 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define BA0_PFCV1 0x00000204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define BA0_PFCV2 0x00000208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define BA0_PCICFG00 0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define BA0_PCICFG04 0x00000304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define BA0_PCICFG08 0x00000308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define BA0_PCICFG0C 0x0000030C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define BA0_PCICFG10 0x00000310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define BA0_PCICFG14 0x00000314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define BA0_PCICFG18 0x00000318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define BA0_PCICFG1C 0x0000031C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define BA0_PCICFG20 0x00000320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define BA0_PCICFG24 0x00000324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define BA0_PCICFG28 0x00000328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define BA0_PCICFG2C 0x0000032C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define BA0_PCICFG30 0x00000330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define BA0_PCICFG34 0x00000334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define BA0_PCICFG38 0x00000338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define BA0_PCICFG3C 0x0000033C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define BA0_CLKCR1 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define BA0_CLKCR2 0x00000404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define BA0_PLLM 0x00000408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define BA0_PLLCC 0x0000040C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define BA0_FRR 0x00000410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define BA0_CFL1 0x00000414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define BA0_CFL2 0x00000418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define BA0_SERMC1 0x00000420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define BA0_SERMC2 0x00000424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define BA0_SERC1 0x00000428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define BA0_SERC2 0x0000042C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define BA0_SERC3 0x00000430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define BA0_SERC4 0x00000434
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define BA0_SERC5 0x00000438
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define BA0_SERBSP 0x0000043C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define BA0_SERBST 0x00000440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define BA0_SERBCM 0x00000444
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define BA0_SERBAD 0x00000448
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define BA0_SERBCF 0x0000044C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define BA0_SERBWP 0x00000450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define BA0_SERBRP 0x00000454
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #ifndef NO_CS4612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define BA0_ASER_FADDR 0x00000458
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define BA0_ACCTL 0x00000460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define BA0_ACSTS 0x00000464
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define BA0_ACOSV 0x00000468
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define BA0_ACCAD 0x0000046C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define BA0_ACCDA 0x00000470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define BA0_ACISV 0x00000474
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define BA0_ACSAD 0x00000478
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define BA0_ACSDA 0x0000047C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define BA0_JSPT 0x00000480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define BA0_JSCTL 0x00000484
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define BA0_JSC1 0x00000488
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define BA0_JSC2 0x0000048C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define BA0_MIDCR 0x00000490
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define BA0_MIDSR 0x00000494
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define BA0_MIDWP 0x00000498
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define BA0_MIDRP 0x0000049C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define BA0_JSIO 0x000004A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #ifndef NO_CS4612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define BA0_ASER_MASTER 0x000004A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define BA0_CFGI 0x000004B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define BA0_SSVID 0x000004B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define BA0_GPIOR 0x000004B8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #ifndef NO_CS4612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define BA0_EGPIODR 0x000004BC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define BA0_EGPIOPTR 0x000004C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define BA0_EGPIOTR 0x000004C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define BA0_EGPIOWR 0x000004C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define BA0_EGPIOSR 0x000004CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define BA0_SERC6 0x000004D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define BA0_SERC7 0x000004D4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define BA0_SERACC 0x000004D8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define BA0_ACCTL2 0x000004E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define BA0_ACSTS2 0x000004E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define BA0_ACOSV2 0x000004E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define BA0_ACCAD2 0x000004EC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define BA0_ACCDA2 0x000004F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define BA0_ACISV2 0x000004F4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define BA0_ACSAD2 0x000004F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define BA0_ACSDA2 0x000004FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define BA0_IOTAC0 0x00000500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define BA0_IOTAC1 0x00000504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define BA0_IOTAC2 0x00000508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define BA0_IOTAC3 0x0000050C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define BA0_IOTAC4 0x00000510
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define BA0_IOTAC5 0x00000514
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define BA0_IOTAC6 0x00000518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define BA0_IOTAC7 0x0000051C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define BA0_IOTAC8 0x00000520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define BA0_IOTAC9 0x00000524
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define BA0_IOTAC10 0x00000528
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define BA0_IOTAC11 0x0000052C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define BA0_IOTFR0 0x00000540
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define BA0_IOTFR1 0x00000544
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define BA0_IOTFR2 0x00000548
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define BA0_IOTFR3 0x0000054C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define BA0_IOTFR4 0x00000550
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define BA0_IOTFR5 0x00000554
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define BA0_IOTFR6 0x00000558
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define BA0_IOTFR7 0x0000055C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define BA0_IOTFIFO 0x00000580
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define BA0_IOTRRD 0x00000584
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define BA0_IOTFP 0x00000588
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define BA0_IOTCR 0x0000058C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define BA0_DPCID 0x00000590
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define BA0_DPCIA 0x00000594
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define BA0_DPCIC 0x00000598
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define BA0_PCPCIR 0x00000600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define BA0_PCPCIG 0x00000604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define BA0_PCPCIEN 0x00000608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define BA0_EPCIPMC 0x00000610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * The following define the offsets of the registers and memories accessed via
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * base address register one on the CS46xx part.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define BA1_SP_DMEM0 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define BA1_SP_DMEM1 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define BA1_SP_PMEM 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define BA1_SP_REG 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define BA1_SPCR 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define BA1_DREG 0x00030004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define BA1_DSRWP 0x00030008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define BA1_TWPR 0x0003000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define BA1_SPWR 0x00030010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define BA1_SPIR 0x00030014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define BA1_FGR1 0x00030020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define BA1_SPCS 0x00030028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define BA1_SDSR 0x0003002C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define BA1_FRMT 0x00030030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define BA1_FRCC 0x00030034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define BA1_FRSC 0x00030038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define BA1_OMNI_MEM 0x000E0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * The following defines are for the flags in the host interrupt status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define HISR_VC_MASK 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define HISR_VC0 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define HISR_VC1 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define HISR_VC2 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define HISR_VC3 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define HISR_VC4 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define HISR_VC5 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define HISR_VC6 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define HISR_VC7 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define HISR_VC8 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define HISR_VC9 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define HISR_VC10 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define HISR_VC11 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define HISR_VC12 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define HISR_VC13 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define HISR_VC14 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define HISR_VC15 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define HISR_INT0 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define HISR_INT1 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define HISR_DMAI 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define HISR_FROVR 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define HISR_MIDI 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #ifdef NO_CS4612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define HISR_RESERVED 0x0FE00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define HISR_SBINT 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define HISR_RESERVED 0x0FC00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define HISR_H0P 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define HISR_INTENA 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * The following defines are for the flags in the host signal register 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define HSR0_VC_MASK 0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define HSR0_VC16 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define HSR0_VC17 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define HSR0_VC18 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define HSR0_VC19 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define HSR0_VC20 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define HSR0_VC21 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define HSR0_VC22 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define HSR0_VC23 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define HSR0_VC24 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define HSR0_VC25 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define HSR0_VC26 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define HSR0_VC27 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define HSR0_VC28 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define HSR0_VC29 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define HSR0_VC30 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define HSR0_VC31 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define HSR0_VC32 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define HSR0_VC33 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define HSR0_VC34 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define HSR0_VC35 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define HSR0_VC36 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define HSR0_VC37 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define HSR0_VC38 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define HSR0_VC39 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define HSR0_VC40 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define HSR0_VC41 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define HSR0_VC42 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define HSR0_VC43 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define HSR0_VC44 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define HSR0_VC45 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define HSR0_VC46 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define HSR0_VC47 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * The following defines are for the flags in the host interrupt control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define HICR_IEV 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define HICR_CHGM 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * The following defines are for the flags in the DMA status register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define DMSR_HP 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define DMSR_HR 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define DMSR_SP 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define DMSR_SR 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * The following defines are for the flags in the host DMA source address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define HSAR_HOST_ADDR_MASK 0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define HSAR_DSP_ADDR_MASK 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define HSAR_MEMID_MASK 0x000F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define HSAR_MEMID_SP_DMEM0 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define HSAR_MEMID_SP_DMEM1 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define HSAR_MEMID_SP_PMEM 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define HSAR_MEMID_SP_DEBUG 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define HSAR_MEMID_OMNI_MEM 0x000E0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define HSAR_END 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define HSAR_ERR 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * The following defines are for the flags in the host DMA destination address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define HDAR_HOST_ADDR_MASK 0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define HDAR_DSP_ADDR_MASK 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define HDAR_MEMID_MASK 0x000F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define HDAR_MEMID_SP_DMEM0 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define HDAR_MEMID_SP_DMEM1 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define HDAR_MEMID_SP_PMEM 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define HDAR_MEMID_SP_DEBUG 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define HDAR_MEMID_OMNI_MEM 0x000E0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define HDAR_END 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define HDAR_ERR 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * The following defines are for the flags in the host DMA control register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define HDMR_AC_MASK 0x0000F000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define HDMR_AC_8_16 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define HDMR_AC_M_S 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define HDMR_AC_B_L 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define HDMR_AC_S_U 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * The following defines are for the flags in the host DMA control register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define HDCR_COUNT_MASK 0x000003FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define HDCR_DONE 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define HDCR_OPT 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define HDCR_WBD 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define HDCR_WBS 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define HDCR_DMS_MASK 0x07000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define HDCR_DMS_LINEAR 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define HDCR_DMS_16_DWORDS 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define HDCR_DMS_32_DWORDS 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define HDCR_DMS_64_DWORDS 0x03000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define HDCR_DMS_128_DWORDS 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define HDCR_DMS_256_DWORDS 0x05000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define HDCR_DMS_512_DWORDS 0x06000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define HDCR_DMS_1024_DWORDS 0x07000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define HDCR_DH 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define HDCR_SMS_MASK 0x70000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define HDCR_SMS_LINEAR 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define HDCR_SMS_16_DWORDS 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define HDCR_SMS_32_DWORDS 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define HDCR_SMS_64_DWORDS 0x30000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define HDCR_SMS_128_DWORDS 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define HDCR_SMS_256_DWORDS 0x50000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define HDCR_SMS_512_DWORDS 0x60000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define HDCR_SMS_1024_DWORDS 0x70000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define HDCR_SH 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define HDCR_COUNT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * The following defines are for the flags in the performance monitor control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define PFMC_C1SS_MASK 0x0000001F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define PFMC_C1EV 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define PFMC_C1RS 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define PFMC_C2SS_MASK 0x001F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define PFMC_C2EV 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define PFMC_C2RS 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define PFMC_C1SS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define PFMC_C2SS_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define PFMC_BUS_GRANT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define PFMC_GRANT_AFTER_REQ 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define PFMC_TRANSACTION 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define PFMC_DWORD_TRANSFER 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define PFMC_SLAVE_READ 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define PFMC_SLAVE_WRITE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define PFMC_PREEMPTION 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define PFMC_DISCONNECT_RETRY 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define PFMC_INTERRUPT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define PFMC_BUS_OWNERSHIP 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define PFMC_TRANSACTION_LAG 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define PFMC_PCI_CLOCK 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define PFMC_SERIAL_CLOCK 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define PFMC_SP_CLOCK 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * The following defines are for the flags in the performance counter value 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define PFCV1_PC1V_MASK 0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define PFCV1_PC1V_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * The following defines are for the flags in the performance counter value 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define PFCV2_PC2V_MASK 0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define PFCV2_PC2V_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * The following defines are for the flags in the clock control register 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define CLKCR1_OSCS 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define CLKCR1_OSCP 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define CLKCR1_PLLSS_MASK 0x0000000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define CLKCR1_PLLSS_SERIAL 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define CLKCR1_PLLSS_CRYSTAL 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define CLKCR1_PLLSS_PCI 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define CLKCR1_PLLSS_RESERVED 0x0000000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define CLKCR1_PLLP 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define CLKCR1_SWCE 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define CLKCR1_PLLOS 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * The following defines are for the flags in the clock control register 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define CLKCR2_PDIVS_MASK 0x0000000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define CLKCR2_PDIVS_1 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define CLKCR2_PDIVS_2 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define CLKCR2_PDIVS_4 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define CLKCR2_PDIVS_7 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define CLKCR2_PDIVS_8 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define CLKCR2_PDIVS_16 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * The following defines are for the flags in the PLL multiplier register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define PLLM_MASK 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define PLLM_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * The following defines are for the flags in the PLL capacitor coefficient
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define PLLCC_CDR_MASK 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #ifndef NO_CS4610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define PLLCC_CDR_240_350_MHZ 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define PLLCC_CDR_184_265_MHZ 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define PLLCC_CDR_144_205_MHZ 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define PLLCC_CDR_111_160_MHZ 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define PLLCC_CDR_87_123_MHZ 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define PLLCC_CDR_67_96_MHZ 0x00000005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define PLLCC_CDR_52_74_MHZ 0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define PLLCC_CDR_45_58_MHZ 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #ifndef NO_CS4612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define PLLCC_CDR_271_398_MHZ 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define PLLCC_CDR_227_330_MHZ 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define PLLCC_CDR_167_239_MHZ 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define PLLCC_CDR_150_215_MHZ 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define PLLCC_CDR_107_154_MHZ 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define PLLCC_CDR_98_140_MHZ 0x00000005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define PLLCC_CDR_73_104_MHZ 0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define PLLCC_CDR_63_90_MHZ 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define PLLCC_LPF_MASK 0x000000F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #ifndef NO_CS4610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define PLLCC_LPF_23850_60000_KHZ 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define PLLCC_LPF_7960_26290_KHZ 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define PLLCC_LPF_4160_10980_KHZ 0x00000018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define PLLCC_LPF_1740_4580_KHZ 0x00000038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define PLLCC_LPF_724_1910_KHZ 0x00000078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define PLLCC_LPF_317_798_KHZ 0x000000F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #ifndef NO_CS4612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define PLLCC_LPF_25580_64530_KHZ 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define PLLCC_LPF_14360_37270_KHZ 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define PLLCC_LPF_6100_16020_KHZ 0x00000018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define PLLCC_LPF_2540_6690_KHZ 0x00000038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define PLLCC_LPF_1050_2780_KHZ 0x00000078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define PLLCC_LPF_450_1160_KHZ 0x000000F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * The following defines are for the flags in the feature reporting register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define FRR_FAB_MASK 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define FRR_MASK_MASK 0x0000001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #ifdef NO_CS4612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define FRR_CFOP_MASK 0x000000E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define FRR_CFOP_MASK 0x00000FE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define FRR_CFOP_NOT_DVD 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define FRR_CFOP_A3D 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define FRR_CFOP_128_PIN 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #ifndef NO_CS4612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define FRR_CFOP_CS4280 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define FRR_FAB_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define FRR_MASK_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define FRR_CFOP_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * The following defines are for the flags in the configuration load 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define CFL1_CLOCK_SOURCE_MASK 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define CFL1_CLOCK_SOURCE_CS423X 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define CFL1_CLOCK_SOURCE_AC97 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define CFL1_CLOCK_SOURCE_CRYSTAL 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define CFL1_CLOCK_SOURCE_DUAL_AC97 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define CFL1_VALID_DATA_MASK 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * The following defines are for the flags in the configuration load 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define CFL2_VALID_DATA_MASK 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * The following defines are for the flags in the serial port master control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * register 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define SERMC1_MSPE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define SERMC1_PTC_MASK 0x0000000E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define SERMC1_PTC_CS423X 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define SERMC1_PTC_AC97 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define SERMC1_PTC_DAC 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define SERMC1_PLB 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define SERMC1_XLB 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * The following defines are for the flags in the serial port master control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * register 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define SERMC2_LROE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define SERMC2_MCOE 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define SERMC2_MCDIV 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * The following defines are for the flags in the serial port 1 configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define SERC1_SO1EN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define SERC1_SO1F_MASK 0x0000000E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define SERC1_SO1F_CS423X 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define SERC1_SO1F_AC97 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define SERC1_SO1F_DAC 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define SERC1_SO1F_SPDIF 0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * The following defines are for the flags in the serial port 2 configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define SERC2_SI1EN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define SERC2_SI1F_MASK 0x0000000E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define SERC2_SI1F_CS423X 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define SERC2_SI1F_AC97 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define SERC2_SI1F_ADC 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define SERC2_SI1F_SPDIF 0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * The following defines are for the flags in the serial port 3 configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define SERC3_SO2EN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define SERC3_SO2F_MASK 0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define SERC3_SO2F_DAC 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define SERC3_SO2F_SPDIF 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * The following defines are for the flags in the serial port 4 configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define SERC4_SO3EN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define SERC4_SO3F_MASK 0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define SERC4_SO3F_DAC 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define SERC4_SO3F_SPDIF 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * The following defines are for the flags in the serial port 5 configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define SERC5_SI2EN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define SERC5_SI2F_MASK 0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define SERC5_SI2F_ADC 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define SERC5_SI2F_SPDIF 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * The following defines are for the flags in the serial port backdoor sample
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * pointer register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define SERBSP_FSP_MASK 0x0000000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define SERBSP_FSP_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * The following defines are for the flags in the serial port backdoor status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define SERBST_RRDY 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define SERBST_WBSY 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * The following defines are for the flags in the serial port backdoor command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define SERBCM_RDC 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define SERBCM_WRC 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * The following defines are for the flags in the serial port backdoor address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #ifdef NO_CS4612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define SERBAD_FAD_MASK 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define SERBAD_FAD_MASK 0x000001FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define SERBAD_FAD_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * The following defines are for the flags in the serial port backdoor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) * configuration register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define SERBCF_HBP 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * The following defines are for the flags in the serial port backdoor write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) * port register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define SERBWP_FWD_MASK 0x000FFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define SERBWP_FWD_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * The following defines are for the flags in the serial port backdoor read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * port register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define SERBRP_FRD_MASK 0x000FFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define SERBRP_FRD_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * The following defines are for the flags in the async FIFO address register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #ifndef NO_CS4612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define ASER_FADDR_A1_MASK 0x000001FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define ASER_FADDR_EN1 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define ASER_FADDR_A2_MASK 0x01FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define ASER_FADDR_EN2 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define ASER_FADDR_A1_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define ASER_FADDR_A2_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * The following defines are for the flags in the AC97 control register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define ACCTL_RSTN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define ACCTL_ESYN 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define ACCTL_VFRM 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define ACCTL_DCV 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define ACCTL_CRW 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define ACCTL_ASYN 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #ifndef NO_CS4612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define ACCTL_TC 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * The following defines are for the flags in the AC97 status register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define ACSTS_CRDY 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define ACSTS_VSTS 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #ifndef NO_CS4612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define ACSTS_WKUP 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * The following defines are for the flags in the AC97 output slot valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define ACOSV_SLV3 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define ACOSV_SLV4 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define ACOSV_SLV5 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define ACOSV_SLV6 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define ACOSV_SLV7 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define ACOSV_SLV8 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define ACOSV_SLV9 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define ACOSV_SLV10 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define ACOSV_SLV11 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define ACOSV_SLV12 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * The following defines are for the flags in the AC97 command address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define ACCAD_CI_MASK 0x0000007F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define ACCAD_CI_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) * The following defines are for the flags in the AC97 command data register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define ACCDA_CD_MASK 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define ACCDA_CD_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) * The following defines are for the flags in the AC97 input slot valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define ACISV_ISV3 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define ACISV_ISV4 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define ACISV_ISV5 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define ACISV_ISV6 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define ACISV_ISV7 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define ACISV_ISV8 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define ACISV_ISV9 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define ACISV_ISV10 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define ACISV_ISV11 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define ACISV_ISV12 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) * The following defines are for the flags in the AC97 status address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define ACSAD_SI_MASK 0x0000007F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define ACSAD_SI_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * The following defines are for the flags in the AC97 status data register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define ACSDA_SD_MASK 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define ACSDA_SD_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) * The following defines are for the flags in the joystick poll/trigger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define JSPT_CAX 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define JSPT_CAY 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define JSPT_CBX 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define JSPT_CBY 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define JSPT_BA1 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define JSPT_BA2 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define JSPT_BB1 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define JSPT_BB2 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * The following defines are for the flags in the joystick control register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define JSCTL_SP_MASK 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define JSCTL_SP_SLOW 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define JSCTL_SP_MEDIUM_SLOW 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define JSCTL_SP_MEDIUM_FAST 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define JSCTL_SP_FAST 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define JSCTL_ARE 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * The following defines are for the flags in the joystick coordinate pair 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * readback register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define JSC1_Y1V_MASK 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define JSC1_X1V_MASK 0xFFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define JSC1_Y1V_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define JSC1_X1V_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) * The following defines are for the flags in the joystick coordinate pair 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) * readback register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define JSC2_Y2V_MASK 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define JSC2_X2V_MASK 0xFFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define JSC2_Y2V_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define JSC2_X2V_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) * The following defines are for the flags in the MIDI control register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define MIDCR_TXE 0x00000001 /* Enable transmitting. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define MIDCR_RXE 0x00000002 /* Enable receiving. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define MIDCR_RIE 0x00000004 /* Interrupt upon tx ready. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define MIDCR_TIE 0x00000008 /* Interrupt upon rx ready. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define MIDCR_MLB 0x00000010 /* Enable midi loopback. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define MIDCR_MRST 0x00000020 /* Reset interface. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) * The following defines are for the flags in the MIDI status register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define MIDSR_TBF 0x00000001 /* Tx FIFO is full. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define MIDSR_RBE 0x00000002 /* Rx FIFO is empty. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) * The following defines are for the flags in the MIDI write port register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define MIDWP_MWD_MASK 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define MIDWP_MWD_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) * The following defines are for the flags in the MIDI read port register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define MIDRP_MRD_MASK 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define MIDRP_MRD_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) * The following defines are for the flags in the joystick GPIO register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define JSIO_DAX 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define JSIO_DAY 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define JSIO_DBX 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define JSIO_DBY 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define JSIO_AXOE 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define JSIO_AYOE 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define JSIO_BXOE 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define JSIO_BYOE 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) * The following defines are for the flags in the master async/sync serial
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * port enable register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #ifndef NO_CS4612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define ASER_MASTER_ME 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) * The following defines are for the flags in the configuration interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define CFGI_CLK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define CFGI_DOUT 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define CFGI_DIN_EEN 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #define CFGI_EELD 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) * The following defines are for the flags in the subsystem ID and vendor ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define SSVID_VID_MASK 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #define SSVID_SID_MASK 0xFFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define SSVID_VID_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define SSVID_SID_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) * The following defines are for the flags in the GPIO pin interface register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #define GPIOR_VOLDN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) #define GPIOR_VOLUP 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #define GPIOR_SI2D 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #define GPIOR_SI2OE 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) * The following defines are for the flags in the extended GPIO pin direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #ifndef NO_CS4612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #define EGPIODR_GPOE0 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #define EGPIODR_GPOE1 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #define EGPIODR_GPOE2 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) #define EGPIODR_GPOE3 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) #define EGPIODR_GPOE4 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #define EGPIODR_GPOE5 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #define EGPIODR_GPOE6 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #define EGPIODR_GPOE7 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define EGPIODR_GPOE8 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) * The following defines are for the flags in the extended GPIO pin polarity/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) * type register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #ifndef NO_CS4612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #define EGPIOPTR_GPPT0 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define EGPIOPTR_GPPT1 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define EGPIOPTR_GPPT2 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define EGPIOPTR_GPPT3 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define EGPIOPTR_GPPT4 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define EGPIOPTR_GPPT5 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define EGPIOPTR_GPPT6 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #define EGPIOPTR_GPPT7 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #define EGPIOPTR_GPPT8 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) * The following defines are for the flags in the extended GPIO pin sticky
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #ifndef NO_CS4612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define EGPIOTR_GPS0 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #define EGPIOTR_GPS1 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #define EGPIOTR_GPS2 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #define EGPIOTR_GPS3 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #define EGPIOTR_GPS4 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #define EGPIOTR_GPS5 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #define EGPIOTR_GPS6 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #define EGPIOTR_GPS7 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) #define EGPIOTR_GPS8 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) * The following defines are for the flags in the extended GPIO ping wakeup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) #ifndef NO_CS4612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) #define EGPIOWR_GPW0 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) #define EGPIOWR_GPW1 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #define EGPIOWR_GPW2 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #define EGPIOWR_GPW3 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) #define EGPIOWR_GPW4 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #define EGPIOWR_GPW5 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) #define EGPIOWR_GPW6 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #define EGPIOWR_GPW7 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) #define EGPIOWR_GPW8 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) * The following defines are for the flags in the extended GPIO pin status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #ifndef NO_CS4612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #define EGPIOSR_GPS0 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define EGPIOSR_GPS1 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #define EGPIOSR_GPS2 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #define EGPIOSR_GPS3 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #define EGPIOSR_GPS4 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #define EGPIOSR_GPS5 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #define EGPIOSR_GPS6 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) #define EGPIOSR_GPS7 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) #define EGPIOSR_GPS8 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) * The following defines are for the flags in the serial port 6 configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #ifndef NO_CS4612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #define SERC6_ASDO2EN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) * The following defines are for the flags in the serial port 7 configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) #ifndef NO_CS4612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) #define SERC7_ASDI2EN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #define SERC7_POSILB 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #define SERC7_SIPOLB 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #define SERC7_SOSILB 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) #define SERC7_SISOLB 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) * The following defines are for the flags in the serial port AC link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) * configuration register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) #ifndef NO_CS4612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #define SERACC_CHIP_TYPE_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) #define SERACC_CHIP_TYPE_1_03 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #define SERACC_CHIP_TYPE_2_0 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #define SERACC_TWO_CODECS 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) #define SERACC_MDM 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) #define SERACC_HSP 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) #define SERACC_ODT 0x00000010 /* only CS4630 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * The following defines are for the flags in the AC97 control register 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #ifndef NO_CS4612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) #define ACCTL2_RSTN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) #define ACCTL2_ESYN 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) #define ACCTL2_VFRM 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) #define ACCTL2_DCV 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #define ACCTL2_CRW 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) #define ACCTL2_ASYN 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) * The following defines are for the flags in the AC97 status register 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #ifndef NO_CS4612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) #define ACSTS2_CRDY 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) #define ACSTS2_VSTS 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) * The following defines are for the flags in the AC97 output slot valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) * register 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #ifndef NO_CS4612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) #define ACOSV2_SLV3 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) #define ACOSV2_SLV4 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #define ACOSV2_SLV5 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #define ACOSV2_SLV6 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) #define ACOSV2_SLV7 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #define ACOSV2_SLV8 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) #define ACOSV2_SLV9 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #define ACOSV2_SLV10 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) #define ACOSV2_SLV11 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) #define ACOSV2_SLV12 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) * The following defines are for the flags in the AC97 command address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) * register 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #ifndef NO_CS4612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) #define ACCAD2_CI_MASK 0x0000007F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) #define ACCAD2_CI_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) * The following defines are for the flags in the AC97 command data register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) * 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #ifndef NO_CS4612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) #define ACCDA2_CD_MASK 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) #define ACCDA2_CD_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) * The following defines are for the flags in the AC97 input slot valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) * register 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) #ifndef NO_CS4612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) #define ACISV2_ISV3 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) #define ACISV2_ISV4 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) #define ACISV2_ISV5 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) #define ACISV2_ISV6 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) #define ACISV2_ISV7 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) #define ACISV2_ISV8 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) #define ACISV2_ISV9 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) #define ACISV2_ISV10 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) #define ACISV2_ISV11 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) #define ACISV2_ISV12 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) * The following defines are for the flags in the AC97 status address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) * register 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) #ifndef NO_CS4612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) #define ACSAD2_SI_MASK 0x0000007F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) #define ACSAD2_SI_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) * The following defines are for the flags in the AC97 status data register 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) #ifndef NO_CS4612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) #define ACSDA2_SD_MASK 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) #define ACSDA2_SD_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) * The following defines are for the flags in the I/O trap address and control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) * registers (all 12).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) #ifndef NO_CS4612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) #define IOTAC_SA_MASK 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) #define IOTAC_MSK_MASK 0x000F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) #define IOTAC_IODC_MASK 0x06000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) #define IOTAC_IODC_16_BIT 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) #define IOTAC_IODC_10_BIT 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) #define IOTAC_IODC_12_BIT 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) #define IOTAC_WSPI 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) #define IOTAC_RSPI 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) #define IOTAC_WSE 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) #define IOTAC_WE 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) #define IOTAC_RE 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) #define IOTAC_SA_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) #define IOTAC_MSK_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) * The following defines are for the flags in the I/O trap fast read registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) * (all 8).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) #ifndef NO_CS4612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) #define IOTFR_D_MASK 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) #define IOTFR_A_MASK 0x000F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) #define IOTFR_R_MASK 0x0F000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) #define IOTFR_ALL 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) #define IOTFR_VL 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) #define IOTFR_D_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) #define IOTFR_A_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) #define IOTFR_R_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) * The following defines are for the flags in the I/O trap FIFO register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) #ifndef NO_CS4612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) #define IOTFIFO_BA_MASK 0x00003FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) #define IOTFIFO_S_MASK 0x00FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) #define IOTFIFO_OF 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) #define IOTFIFO_SPIOF 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) #define IOTFIFO_BA_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) #define IOTFIFO_S_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) * The following defines are for the flags in the I/O trap retry read data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) #ifndef NO_CS4612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) #define IOTRRD_D_MASK 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) #define IOTRRD_RDV 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) #define IOTRRD_D_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) * The following defines are for the flags in the I/O trap FIFO pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) #ifndef NO_CS4612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) #define IOTFP_CA_MASK 0x00003FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) #define IOTFP_PA_MASK 0x3FFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) #define IOTFP_CA_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) #define IOTFP_PA_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) * The following defines are for the flags in the I/O trap control register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) #ifndef NO_CS4612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) #define IOTCR_ITD 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) #define IOTCR_HRV 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) #define IOTCR_SRV 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) #define IOTCR_DTI 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) #define IOTCR_DFI 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) #define IOTCR_DDP 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) #define IOTCR_JTE 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) #define IOTCR_PPE 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) * The following defines are for the flags in the direct PCI data register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) #ifndef NO_CS4612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) #define DPCID_D_MASK 0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) #define DPCID_D_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) * The following defines are for the flags in the direct PCI address register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) #ifndef NO_CS4612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) #define DPCIA_A_MASK 0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) #define DPCIA_A_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) * The following defines are for the flags in the direct PCI command register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) #ifndef NO_CS4612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) #define DPCIC_C_MASK 0x0000000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) #define DPCIC_C_IOREAD 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) #define DPCIC_C_IOWRITE 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) #define DPCIC_BE_MASK 0x000000F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) * The following defines are for the flags in the PC/PCI request register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) #ifndef NO_CS4612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) #define PCPCIR_RDC_MASK 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) #define PCPCIR_C_MASK 0x00007000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) #define PCPCIR_REQ 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) #define PCPCIR_RDC_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) #define PCPCIR_C_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) * The following defines are for the flags in the PC/PCI grant register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) #ifndef NO_CS4612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) #define PCPCIG_GDC_MASK 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) #define PCPCIG_VL 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) #define PCPCIG_GDC_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) * The following defines are for the flags in the PC/PCI master enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) #ifndef NO_CS4612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) #define PCPCIEN_EN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) * The following defines are for the flags in the extended PCI power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) * management control register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) #ifndef NO_CS4612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) #define EPCIPMC_GWU 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) #define EPCIPMC_FSPC 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) * The following defines are for the flags in the SP control register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) #define SPCR_RUN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) #define SPCR_STPFR 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) #define SPCR_RUNFR 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) #define SPCR_TICK 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) #define SPCR_DRQEN 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) #define SPCR_RSTSP 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) #define SPCR_OREN 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) #ifndef NO_CS4612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) #define SPCR_PCIINT 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) #define SPCR_OINTD 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) #define SPCR_CRE 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) * The following defines are for the flags in the debug index register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) #define DREG_REGID_MASK 0x0000007F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) #define DREG_DEBUG 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) #define DREG_RGBK_MASK 0x00000700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) #define DREG_TRAP 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) #if !defined(NO_CS4612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) #if !defined(NO_CS4615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) #define DREG_TRAPX 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) #define DREG_REGID_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) #define DREG_RGBK_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) #define DREG_RGBK_REGID_MASK 0x0000077F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) #define DREG_REGID_R0 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) #define DREG_REGID_R1 0x00000011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) #define DREG_REGID_R2 0x00000012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) #define DREG_REGID_R3 0x00000013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) #define DREG_REGID_R4 0x00000014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) #define DREG_REGID_R5 0x00000015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) #define DREG_REGID_R6 0x00000016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) #define DREG_REGID_R7 0x00000017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) #define DREG_REGID_R8 0x00000018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) #define DREG_REGID_R9 0x00000019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) #define DREG_REGID_RA 0x0000001A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) #define DREG_REGID_RB 0x0000001B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) #define DREG_REGID_RC 0x0000001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) #define DREG_REGID_RD 0x0000001D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) #define DREG_REGID_RE 0x0000001E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) #define DREG_REGID_RF 0x0000001F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) #define DREG_REGID_RA_BUS_LOW 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) #define DREG_REGID_RA_BUS_HIGH 0x00000038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) #define DREG_REGID_YBUS_LOW 0x00000050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) #define DREG_REGID_YBUS_HIGH 0x00000058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) #define DREG_REGID_TRAP_0 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) #define DREG_REGID_TRAP_1 0x00000101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) #define DREG_REGID_TRAP_2 0x00000102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) #define DREG_REGID_TRAP_3 0x00000103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) #define DREG_REGID_TRAP_4 0x00000104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) #define DREG_REGID_TRAP_5 0x00000105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) #define DREG_REGID_TRAP_6 0x00000106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) #define DREG_REGID_TRAP_7 0x00000107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) #define DREG_REGID_INDIRECT_ADDRESS 0x0000010E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) #define DREG_REGID_TOP_OF_STACK 0x0000010F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) #if !defined(NO_CS4612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) #if !defined(NO_CS4615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) #define DREG_REGID_TRAP_8 0x00000110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) #define DREG_REGID_TRAP_9 0x00000111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) #define DREG_REGID_TRAP_10 0x00000112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) #define DREG_REGID_TRAP_11 0x00000113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) #define DREG_REGID_TRAP_12 0x00000114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) #define DREG_REGID_TRAP_13 0x00000115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) #define DREG_REGID_TRAP_14 0x00000116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) #define DREG_REGID_TRAP_15 0x00000117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) #define DREG_REGID_TRAP_16 0x00000118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) #define DREG_REGID_TRAP_17 0x00000119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) #define DREG_REGID_TRAP_18 0x0000011A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) #define DREG_REGID_TRAP_19 0x0000011B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) #define DREG_REGID_TRAP_20 0x0000011C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) #define DREG_REGID_TRAP_21 0x0000011D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) #define DREG_REGID_TRAP_22 0x0000011E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) #define DREG_REGID_TRAP_23 0x0000011F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) #define DREG_REGID_RSA0_LOW 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) #define DREG_REGID_RSA0_HIGH 0x00000201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) #define DREG_REGID_RSA1_LOW 0x00000202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) #define DREG_REGID_RSA1_HIGH 0x00000203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) #define DREG_REGID_RSA2 0x00000204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) #define DREG_REGID_RSA3 0x00000205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) #define DREG_REGID_RSI0_LOW 0x00000206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) #define DREG_REGID_RSI0_HIGH 0x00000207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) #define DREG_REGID_RSI1 0x00000208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) #define DREG_REGID_RSI2 0x00000209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) #define DREG_REGID_SAGUSTATUS 0x0000020A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) #define DREG_REGID_RSCONFIG01_LOW 0x0000020B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) #define DREG_REGID_RSCONFIG01_HIGH 0x0000020C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) #define DREG_REGID_RSCONFIG23_LOW 0x0000020D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) #define DREG_REGID_RSCONFIG23_HIGH 0x0000020E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) #define DREG_REGID_RSDMA01E 0x0000020F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) #define DREG_REGID_RSDMA23E 0x00000210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) #define DREG_REGID_RSD0_LOW 0x00000211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) #define DREG_REGID_RSD0_HIGH 0x00000212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) #define DREG_REGID_RSD1_LOW 0x00000213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) #define DREG_REGID_RSD1_HIGH 0x00000214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) #define DREG_REGID_RSD2_LOW 0x00000215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) #define DREG_REGID_RSD2_HIGH 0x00000216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) #define DREG_REGID_RSD3_LOW 0x00000217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) #define DREG_REGID_RSD3_HIGH 0x00000218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) #define DREG_REGID_SRAR_HIGH 0x0000021A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) #define DREG_REGID_SRAR_LOW 0x0000021B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) #define DREG_REGID_DMA_STATE 0x0000021C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) #define DREG_REGID_CURRENT_DMA_STREAM 0x0000021D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) #define DREG_REGID_NEXT_DMA_STREAM 0x0000021E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) #define DREG_REGID_CPU_STATUS 0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) #define DREG_REGID_MAC_MODE 0x00000301
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) #define DREG_REGID_STACK_AND_REPEAT 0x00000302
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) #define DREG_REGID_INDEX0 0x00000304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) #define DREG_REGID_INDEX1 0x00000305
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) #define DREG_REGID_DMA_STATE_0_3 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) #define DREG_REGID_DMA_STATE_4_7 0x00000404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) #define DREG_REGID_DMA_STATE_8_11 0x00000408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) #define DREG_REGID_DMA_STATE_12_15 0x0000040C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) #define DREG_REGID_DMA_STATE_16_19 0x00000410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) #define DREG_REGID_DMA_STATE_20_23 0x00000414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) #define DREG_REGID_DMA_STATE_24_27 0x00000418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) #define DREG_REGID_DMA_STATE_28_31 0x0000041C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) #define DREG_REGID_DMA_STATE_32_35 0x00000420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) #define DREG_REGID_DMA_STATE_36_39 0x00000424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) #define DREG_REGID_DMA_STATE_40_43 0x00000428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) #define DREG_REGID_DMA_STATE_44_47 0x0000042C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) #define DREG_REGID_DMA_STATE_48_51 0x00000430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) #define DREG_REGID_DMA_STATE_52_55 0x00000434
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) #define DREG_REGID_DMA_STATE_56_59 0x00000438
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) #define DREG_REGID_DMA_STATE_60_63 0x0000043C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) #define DREG_REGID_DMA_STATE_64_67 0x00000440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) #define DREG_REGID_DMA_STATE_68_71 0x00000444
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) #define DREG_REGID_DMA_STATE_72_75 0x00000448
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) #define DREG_REGID_DMA_STATE_76_79 0x0000044C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) #define DREG_REGID_DMA_STATE_80_83 0x00000450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) #define DREG_REGID_DMA_STATE_84_87 0x00000454
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) #define DREG_REGID_DMA_STATE_88_91 0x00000458
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) #define DREG_REGID_DMA_STATE_92_95 0x0000045C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) #define DREG_REGID_TRAP_SELECT 0x00000500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) #define DREG_REGID_TRAP_WRITE_0 0x00000500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) #define DREG_REGID_TRAP_WRITE_1 0x00000501
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) #define DREG_REGID_TRAP_WRITE_2 0x00000502
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) #define DREG_REGID_TRAP_WRITE_3 0x00000503
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) #define DREG_REGID_TRAP_WRITE_4 0x00000504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) #define DREG_REGID_TRAP_WRITE_5 0x00000505
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) #define DREG_REGID_TRAP_WRITE_6 0x00000506
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) #define DREG_REGID_TRAP_WRITE_7 0x00000507
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) #if !defined(NO_CS4612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) #if !defined(NO_CS4615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) #define DREG_REGID_TRAP_WRITE_8 0x00000510
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) #define DREG_REGID_TRAP_WRITE_9 0x00000511
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) #define DREG_REGID_TRAP_WRITE_10 0x00000512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) #define DREG_REGID_TRAP_WRITE_11 0x00000513
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) #define DREG_REGID_TRAP_WRITE_12 0x00000514
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) #define DREG_REGID_TRAP_WRITE_13 0x00000515
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) #define DREG_REGID_TRAP_WRITE_14 0x00000516
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) #define DREG_REGID_TRAP_WRITE_15 0x00000517
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) #define DREG_REGID_TRAP_WRITE_16 0x00000518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) #define DREG_REGID_TRAP_WRITE_17 0x00000519
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) #define DREG_REGID_TRAP_WRITE_18 0x0000051A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) #define DREG_REGID_TRAP_WRITE_19 0x0000051B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) #define DREG_REGID_TRAP_WRITE_20 0x0000051C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) #define DREG_REGID_TRAP_WRITE_21 0x0000051D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) #define DREG_REGID_TRAP_WRITE_22 0x0000051E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) #define DREG_REGID_TRAP_WRITE_23 0x0000051F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) #define DREG_REGID_MAC0_ACC0_LOW 0x00000600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) #define DREG_REGID_MAC0_ACC1_LOW 0x00000601
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) #define DREG_REGID_MAC0_ACC2_LOW 0x00000602
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) #define DREG_REGID_MAC0_ACC3_LOW 0x00000603
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) #define DREG_REGID_MAC1_ACC0_LOW 0x00000604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) #define DREG_REGID_MAC1_ACC1_LOW 0x00000605
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) #define DREG_REGID_MAC1_ACC2_LOW 0x00000606
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) #define DREG_REGID_MAC1_ACC3_LOW 0x00000607
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) #define DREG_REGID_MAC0_ACC0_MID 0x00000608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) #define DREG_REGID_MAC0_ACC1_MID 0x00000609
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) #define DREG_REGID_MAC0_ACC2_MID 0x0000060A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) #define DREG_REGID_MAC0_ACC3_MID 0x0000060B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) #define DREG_REGID_MAC1_ACC0_MID 0x0000060C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) #define DREG_REGID_MAC1_ACC1_MID 0x0000060D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) #define DREG_REGID_MAC1_ACC2_MID 0x0000060E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) #define DREG_REGID_MAC1_ACC3_MID 0x0000060F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) #define DREG_REGID_MAC0_ACC0_HIGH 0x00000610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) #define DREG_REGID_MAC0_ACC1_HIGH 0x00000611
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) #define DREG_REGID_MAC0_ACC2_HIGH 0x00000612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) #define DREG_REGID_MAC0_ACC3_HIGH 0x00000613
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) #define DREG_REGID_MAC1_ACC0_HIGH 0x00000614
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) #define DREG_REGID_MAC1_ACC1_HIGH 0x00000615
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) #define DREG_REGID_MAC1_ACC2_HIGH 0x00000616
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) #define DREG_REGID_MAC1_ACC3_HIGH 0x00000617
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) #define DREG_REGID_RSHOUT_LOW 0x00000620
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) #define DREG_REGID_RSHOUT_MID 0x00000628
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) #define DREG_REGID_RSHOUT_HIGH 0x00000630
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) * The following defines are for the flags in the DMA stream requestor write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) #define DSRWP_DSR_MASK 0x0000000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) #define DSRWP_DSR_BG_RQ 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) #define DSRWP_DSR_PRIORITY_MASK 0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) #define DSRWP_DSR_PRIORITY_0 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) #define DSRWP_DSR_PRIORITY_1 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) #define DSRWP_DSR_PRIORITY_2 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) #define DSRWP_DSR_PRIORITY_3 0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) #define DSRWP_DSR_RQ_PENDING 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) * The following defines are for the flags in the trap write port register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) #define TWPR_TW_MASK 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) #define TWPR_TW_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) * The following defines are for the flags in the stack pointer write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) #define SPWR_STKP_MASK 0x0000000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) #define SPWR_STKP_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) * The following defines are for the flags in the SP interrupt register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) #define SPIR_FRI 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) #define SPIR_DOI 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) #define SPIR_GPI2 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) #define SPIR_GPI3 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) #define SPIR_IP0 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) #define SPIR_IP1 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) #define SPIR_IP2 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) #define SPIR_IP3 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) * The following defines are for the flags in the functional group 1 register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) #define FGR1_F1S_MASK 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) #define FGR1_F1S_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) * The following defines are for the flags in the SP clock status register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) #define SPCS_FRI 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) #define SPCS_DOI 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) #define SPCS_GPI2 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) #define SPCS_GPI3 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) #define SPCS_IP0 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) #define SPCS_IP1 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) #define SPCS_IP2 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) #define SPCS_IP3 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) #define SPCS_SPRUN 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) #define SPCS_SLEEP 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) #define SPCS_FG 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) #define SPCS_ORUN 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) #define SPCS_IRQ 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) #define SPCS_FGN_MASK 0x0000E000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) #define SPCS_FGN_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) * The following defines are for the flags in the SP DMA requestor status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) #define SDSR_DCS_MASK 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) #define SDSR_DCS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) #define SDSR_DCS_NONE 0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) * The following defines are for the flags in the frame timer register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) #define FRMT_FTV_MASK 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) #define FRMT_FTV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) * The following defines are for the flags in the frame timer current count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) #define FRCC_FCC_MASK 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) #define FRCC_FCC_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) * The following defines are for the flags in the frame timer save count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) #define FRSC_FCS_MASK 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) #define FRSC_FCS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) * The following define the various flags stored in the scatter/gather
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) * descriptors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) #define DMA_SG_NEXT_ENTRY_MASK 0x00000FF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) #define DMA_SG_SAMPLE_END_MASK 0x0FFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) #define DMA_SG_SAMPLE_END_FLAG 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) #define DMA_SG_LOOP_END_FLAG 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) #define DMA_SG_SIGNAL_END_FLAG 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) #define DMA_SG_SIGNAL_PAGE_FLAG 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) #define DMA_SG_NEXT_ENTRY_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) #define DMA_SG_SAMPLE_END_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) * The following define the offsets of the fields within the on-chip generic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) * DMA requestor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) #define DMA_RQ_CONTROL1 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) #define DMA_RQ_CONTROL2 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) #define DMA_RQ_SOURCE_ADDR 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) #define DMA_RQ_DESTINATION_ADDR 0x0000000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) #define DMA_RQ_NEXT_PAGE_ADDR 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) #define DMA_RQ_NEXT_PAGE_SGDESC 0x00000014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) #define DMA_RQ_LOOP_START_ADDR 0x00000018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) #define DMA_RQ_POST_LOOP_ADDR 0x0000001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) #define DMA_RQ_PAGE_MAP_ADDR 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) * The following defines are for the flags in the first control word of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) * on-chip generic DMA requestor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) #define DMA_RQ_C1_COUNT_MASK 0x000003FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) #define DMA_RQ_C1_DESTINATION_SCATTER 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) #define DMA_RQ_C1_SOURCE_GATHER 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) #define DMA_RQ_C1_DONE_FLAG 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) #define DMA_RQ_C1_OPTIMIZE_STATE 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) #define DMA_RQ_C1_SAMPLE_END_STATE_MASK 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) #define DMA_RQ_C1_FULL_PAGE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) #define DMA_RQ_C1_BEFORE_SAMPLE_END 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) #define DMA_RQ_C1_PAGE_MAP_ERROR 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) #define DMA_RQ_C1_AT_SAMPLE_END 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) #define DMA_RQ_C1_LOOP_END_STATE_MASK 0x000C0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) #define DMA_RQ_C1_NOT_LOOP_END 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) #define DMA_RQ_C1_BEFORE_LOOP_END 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) #define DMA_RQ_C1_2PAGE_LOOP_BEGIN 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) #define DMA_RQ_C1_LOOP_BEGIN 0x000C0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) #define DMA_RQ_C1_PAGE_MAP_MASK 0x00300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) #define DMA_RQ_C1_PM_NONE_PENDING 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) #define DMA_RQ_C1_PM_NEXT_PENDING 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) #define DMA_RQ_C1_PM_RESERVED 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) #define DMA_RQ_C1_PM_LOOP_NEXT_PENDING 0x00300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) #define DMA_RQ_C1_WRITEBACK_DEST_FLAG 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) #define DMA_RQ_C1_WRITEBACK_SRC_FLAG 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) #define DMA_RQ_C1_DEST_SIZE_MASK 0x07000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) #define DMA_RQ_C1_DEST_LINEAR 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) #define DMA_RQ_C1_DEST_MOD16 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) #define DMA_RQ_C1_DEST_MOD32 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) #define DMA_RQ_C1_DEST_MOD64 0x03000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) #define DMA_RQ_C1_DEST_MOD128 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) #define DMA_RQ_C1_DEST_MOD256 0x05000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) #define DMA_RQ_C1_DEST_MOD512 0x06000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) #define DMA_RQ_C1_DEST_MOD1024 0x07000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) #define DMA_RQ_C1_DEST_ON_HOST 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) #define DMA_RQ_C1_SOURCE_SIZE_MASK 0x70000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) #define DMA_RQ_C1_SOURCE_LINEAR 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) #define DMA_RQ_C1_SOURCE_MOD16 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) #define DMA_RQ_C1_SOURCE_MOD32 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) #define DMA_RQ_C1_SOURCE_MOD64 0x30000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) #define DMA_RQ_C1_SOURCE_MOD128 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) #define DMA_RQ_C1_SOURCE_MOD256 0x50000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) #define DMA_RQ_C1_SOURCE_MOD512 0x60000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) #define DMA_RQ_C1_SOURCE_MOD1024 0x70000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) #define DMA_RQ_C1_SOURCE_ON_HOST 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) #define DMA_RQ_C1_COUNT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) * The following defines are for the flags in the second control word of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) * on-chip generic DMA requestor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) #define DMA_RQ_C2_VIRTUAL_CHANNEL_MASK 0x0000003F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) #define DMA_RQ_C2_VIRTUAL_SIGNAL_MASK 0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) #define DMA_RQ_C2_NO_VIRTUAL_SIGNAL 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) #define DMA_RQ_C2_SIGNAL_EVERY_DMA 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) #define DMA_RQ_C2_SIGNAL_SOURCE_PINGPONG 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) #define DMA_RQ_C2_SIGNAL_DEST_PINGPONG 0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) #define DMA_RQ_C2_AUDIO_CONVERT_MASK 0x0000F000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) #define DMA_RQ_C2_AC_NONE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) #define DMA_RQ_C2_AC_8_TO_16_BIT 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) #define DMA_RQ_C2_AC_MONO_TO_STEREO 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) #define DMA_RQ_C2_AC_ENDIAN_CONVERT 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) #define DMA_RQ_C2_AC_SIGNED_CONVERT 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) #define DMA_RQ_C2_LOOP_END_MASK 0x0FFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) #define DMA_RQ_C2_LOOP_MASK 0x30000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) #define DMA_RQ_C2_NO_LOOP 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) #define DMA_RQ_C2_ONE_PAGE_LOOP 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) #define DMA_RQ_C2_TWO_PAGE_LOOP 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) #define DMA_RQ_C2_MULTI_PAGE_LOOP 0x30000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) #define DMA_RQ_C2_SIGNAL_LOOP_BACK 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) #define DMA_RQ_C2_SIGNAL_POST_BEGIN_PAGE 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) #define DMA_RQ_C2_VIRTUAL_CHANNEL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) #define DMA_RQ_C2_LOOP_END_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) * The following defines are for the flags in the source and destination words
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) * of the on-chip generic DMA requestor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) #define DMA_RQ_SD_ADDRESS_MASK 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) #define DMA_RQ_SD_MEMORY_ID_MASK 0x000F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) #define DMA_RQ_SD_SP_PARAM_ADDR 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) #define DMA_RQ_SD_SP_SAMPLE_ADDR 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) #define DMA_RQ_SD_SP_PROGRAM_ADDR 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) #define DMA_RQ_SD_SP_DEBUG_ADDR 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) #define DMA_RQ_SD_OMNIMEM_ADDR 0x000E0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) #define DMA_RQ_SD_END_FLAG 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) #define DMA_RQ_SD_ERROR_FLAG 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) #define DMA_RQ_SD_ADDRESS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) * The following defines are for the flags in the page map address word of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) * on-chip generic DMA requestor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) #define DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_MASK 0x00000FF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) #define DMA_RQ_PMA_PAGE_TABLE_MASK 0xFFFFF000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) #define DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) #define DMA_RQ_PMA_PAGE_TABLE_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) #define BA1_VARIDEC_BUF_1 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) #define BA1_PDTC 0x0c0 /* BA1_PLAY_DMA_TRANSACTION_COUNT_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) #define BA1_PFIE 0x0c4 /* BA1_PLAY_FORMAT_&_INTERRUPT_ENABLE_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) #define BA1_PBA 0x0c8 /* BA1_PLAY_BUFFER_ADDRESS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) #define BA1_PVOL 0x0f8 /* BA1_PLAY_VOLUME_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) #define BA1_PSRC 0x288 /* BA1_PLAY_SAMPLE_RATE_CORRECTION_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) #define BA1_PCTL 0x2a4 /* BA1_PLAY_CONTROL_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) #define BA1_PPI 0x2b4 /* BA1_PLAY_PHASE_INCREMENT_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) #define BA1_CCTL 0x064 /* BA1_CAPTURE_CONTROL_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) #define BA1_CIE 0x104 /* BA1_CAPTURE_INTERRUPT_ENABLE_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) #define BA1_CBA 0x10c /* BA1_CAPTURE_BUFFER_ADDRESS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) #define BA1_CSRC 0x2c8 /* BA1_CAPTURE_SAMPLE_RATE_CORRECTION_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) #define BA1_CCI 0x2d8 /* BA1_CAPTURE_COEFFICIENT_INCREMENT_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) #define BA1_CD 0x2e0 /* BA1_CAPTURE_DELAY_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) #define BA1_CPI 0x2f4 /* BA1_CAPTURE_PHASE_INCREMENT_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) #define BA1_CVOL 0x2f8 /* BA1_CAPTURE_VOLUME_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) #define BA1_CFG1 0x134 /* BA1_CAPTURE_FRAME_GROUP_1_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) #define BA1_CFG2 0x138 /* BA1_CAPTURE_FRAME_GROUP_2_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) #define BA1_CCST 0x13c /* BA1_CAPTURE_CONSTANT_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) #define BA1_CSPB 0x340 /* BA1_CAPTURE_SPB_ADDRESS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) #define CS46XX_MODE_OUTPUT (1<<0) /* MIDI UART - output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) #define CS46XX_MODE_INPUT (1<<1) /* MIDI UART - input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) #define SAVE_REG_MAX 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) #define POWER_DOWN_ALL 0x7f0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) /* maxinum number of AC97 codecs connected, AC97 2.0 defined 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) #define MAX_NR_AC97 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) #define CS46XX_PRIMARY_CODEC_INDEX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) #define CS46XX_SECONDARY_CODEC_INDEX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) #define CS46XX_SECONDARY_CODEC_OFFSET 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) #define CS46XX_DSP_CAPTURE_CHANNEL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) /* capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) #define CS46XX_DSP_CAPTURE_CHANNEL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) /* mixer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) #define CS46XX_MIXER_SPDIF_INPUT_ELEMENT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) #define CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) struct snd_cs46xx_pcm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) struct snd_dma_buffer hw_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) unsigned int ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) unsigned int shift; /* Shift count to trasform frames in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) struct snd_pcm_indirect pcm_rec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) struct dsp_pcm_channel_descriptor * pcm_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) int pcm_channel_id; /* Fron Rear, Center Lfe ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) struct snd_cs46xx_region {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) char name[24];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) unsigned long base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) void __iomem *remap_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) unsigned long size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) struct resource *resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) struct snd_cs46xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) unsigned long ba0_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) unsigned long ba1_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) struct snd_cs46xx_region ba0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) struct snd_cs46xx_region data0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) struct snd_cs46xx_region data1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) struct snd_cs46xx_region pmem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) struct snd_cs46xx_region reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) } name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) struct snd_cs46xx_region idx[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) } region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) unsigned int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) struct snd_dma_buffer hw_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) unsigned int ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) unsigned int shift; /* Shift count to trasform frames in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) struct snd_pcm_indirect pcm_rec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) } capt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) int nr_ac97_codecs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) struct snd_ac97_bus *ac97_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) struct snd_ac97 *ac97[MAX_NR_AC97];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) struct pci_dev *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) struct snd_rawmidi *rmidi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) struct snd_rawmidi_substream *midi_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) struct snd_rawmidi_substream *midi_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) spinlock_t reg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) unsigned int midcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) unsigned int uartm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) int amplifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) void (*amplifier_ctrl)(struct snd_cs46xx *, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) void (*active_ctrl)(struct snd_cs46xx *, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) void (*mixer_init)(struct snd_cs46xx *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) int acpi_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) struct snd_kcontrol *eapd_switch; /* for amplifier hack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) int accept_valid; /* accept mmap valid (for OSS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) int in_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) struct gameport *gameport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) #ifdef CONFIG_SND_CS46XX_NEW_DSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) struct mutex spos_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) struct dsp_spos_instance * dsp_spos_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) struct snd_pcm *pcm_rear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) struct snd_pcm *pcm_center_lfe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) struct snd_pcm *pcm_iec958;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) #define CS46XX_DSP_MODULES 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) struct dsp_module_desc *modules[CS46XX_DSP_MODULES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) #else /* for compatibility */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) struct snd_cs46xx_pcm *playback_pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) unsigned int play_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) struct ba1_struct *ba1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) u32 *saved_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) int snd_cs46xx_create(struct snd_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) int external_amp, int thinkpad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) struct snd_cs46xx **rcodec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) extern const struct dev_pm_ops snd_cs46xx_pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) int snd_cs46xx_pcm(struct snd_cs46xx *chip, int device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) int snd_cs46xx_pcm_rear(struct snd_cs46xx *chip, int device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) int snd_cs46xx_pcm_iec958(struct snd_cs46xx *chip, int device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) int snd_cs46xx_pcm_center_lfe(struct snd_cs46xx *chip, int device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) int snd_cs46xx_mixer(struct snd_cs46xx *chip, int spdif_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) int snd_cs46xx_midi(struct snd_cs46xx *chip, int device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) int snd_cs46xx_start_dsp(struct snd_cs46xx *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) int snd_cs46xx_gameport(struct snd_cs46xx *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) #endif /* __SOUND_CS46XX_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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