^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Cirrus Logic CS4281 based PCI soundcard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gameport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <sound/control.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <sound/rawmidi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <sound/ac97_codec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <sound/tlv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <sound/opl3.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) MODULE_DESCRIPTION("Cirrus Logic CS4281");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) MODULE_SUPPORTED_DEVICE("{{Cirrus Logic,CS4281}}");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static bool dual_codec[SNDRV_CARDS]; /* dual codec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) module_param_array(index, int, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) MODULE_PARM_DESC(index, "Index value for CS4281 soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) module_param_array(id, charp, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) MODULE_PARM_DESC(id, "ID string for CS4281 soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) module_param_array(enable, bool, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) MODULE_PARM_DESC(enable, "Enable CS4281 soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) module_param_array(dual_codec, bool, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) MODULE_PARM_DESC(dual_codec, "Secondary Codec ID (0 = disabled).");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Direct registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CS4281_BA0_SIZE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CS4281_BA1_SIZE 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * BA0 registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define BA0_HISR 0x0000 /* Host Interrupt Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define BA0_HISR_INTENA (1<<31) /* Internal Interrupt Enable Bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define BA0_HISR_MIDI (1<<22) /* MIDI port interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define BA0_HISR_FIFOI (1<<20) /* FIFO polled interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define BA0_HISR_DMAI (1<<18) /* DMA interrupt (half or end) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define BA0_HISR_FIFO(c) (1<<(12+(c))) /* FIFO channel interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define BA0_HISR_DMA(c) (1<<(8+(c))) /* DMA channel interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define BA0_HISR_GPPI (1<<5) /* General Purpose Input (Primary chip) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define BA0_HISR_GPSI (1<<4) /* General Purpose Input (Secondary chip) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define BA0_HISR_GP3I (1<<3) /* GPIO3 pin Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define BA0_HISR_GP1I (1<<2) /* GPIO1 pin Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define BA0_HISR_VUPI (1<<1) /* VOLUP pin Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define BA0_HISR_VDNI (1<<0) /* VOLDN pin Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define BA0_HICR 0x0008 /* Host Interrupt Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define BA0_HICR_CHGM (1<<1) /* INTENA Change Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define BA0_HICR_IEV (1<<0) /* INTENA Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define BA0_HICR_EOI (3<<0) /* End of Interrupt command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define BA0_HIMR 0x000c /* Host Interrupt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Use same contants as for BA0_HISR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define BA0_IIER 0x0010 /* ISA Interrupt Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define BA0_HDSR0 0x00f0 /* Host DMA Engine 0 Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define BA0_HDSR1 0x00f4 /* Host DMA Engine 1 Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define BA0_HDSR2 0x00f8 /* Host DMA Engine 2 Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define BA0_HDSR3 0x00fc /* Host DMA Engine 3 Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define BA0_HDSR_CH1P (1<<25) /* Channel 1 Pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define BA0_HDSR_CH2P (1<<24) /* Channel 2 Pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define BA0_HDSR_DHTC (1<<17) /* DMA Half Terminal Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define BA0_HDSR_DTC (1<<16) /* DMA Terminal Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define BA0_HDSR_DRUN (1<<15) /* DMA Running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define BA0_HDSR_RQ (1<<7) /* Pending Request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define BA0_DCA0 0x0110 /* Host DMA Engine 0 Current Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define BA0_DCC0 0x0114 /* Host DMA Engine 0 Current Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define BA0_DBA0 0x0118 /* Host DMA Engine 0 Base Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define BA0_DBC0 0x011c /* Host DMA Engine 0 Base Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define BA0_DCA1 0x0120 /* Host DMA Engine 1 Current Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define BA0_DCC1 0x0124 /* Host DMA Engine 1 Current Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define BA0_DBA1 0x0128 /* Host DMA Engine 1 Base Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define BA0_DBC1 0x012c /* Host DMA Engine 1 Base Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define BA0_DCA2 0x0130 /* Host DMA Engine 2 Current Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define BA0_DCC2 0x0134 /* Host DMA Engine 2 Current Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define BA0_DBA2 0x0138 /* Host DMA Engine 2 Base Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define BA0_DBC2 0x013c /* Host DMA Engine 2 Base Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define BA0_DCA3 0x0140 /* Host DMA Engine 3 Current Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define BA0_DCC3 0x0144 /* Host DMA Engine 3 Current Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define BA0_DBA3 0x0148 /* Host DMA Engine 3 Base Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define BA0_DBC3 0x014c /* Host DMA Engine 3 Base Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define BA0_DMR0 0x0150 /* Host DMA Engine 0 Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define BA0_DCR0 0x0154 /* Host DMA Engine 0 Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define BA0_DMR1 0x0158 /* Host DMA Engine 1 Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define BA0_DCR1 0x015c /* Host DMA Engine 1 Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define BA0_DMR2 0x0160 /* Host DMA Engine 2 Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define BA0_DCR2 0x0164 /* Host DMA Engine 2 Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define BA0_DMR3 0x0168 /* Host DMA Engine 3 Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define BA0_DCR3 0x016c /* Host DMA Engine 3 Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define BA0_DMR_DMA (1<<29) /* Enable DMA mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define BA0_DMR_POLL (1<<28) /* Enable poll mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define BA0_DMR_TBC (1<<25) /* Transfer By Channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define BA0_DMR_CBC (1<<24) /* Count By Channel (0 = frame resolution) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define BA0_DMR_SWAPC (1<<22) /* Swap Left/Right Channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define BA0_DMR_SIZE20 (1<<20) /* Sample is 20-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define BA0_DMR_USIGN (1<<19) /* Unsigned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define BA0_DMR_BEND (1<<18) /* Big Endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define BA0_DMR_MONO (1<<17) /* Mono */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define BA0_DMR_SIZE8 (1<<16) /* Sample is 8-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define BA0_DMR_TYPE_DEMAND (0<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define BA0_DMR_TYPE_SINGLE (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define BA0_DMR_TYPE_BLOCK (2<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define BA0_DMR_TYPE_CASCADE (3<<6) /* Not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define BA0_DMR_DEC (1<<5) /* Access Increment (0) or Decrement (1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define BA0_DMR_AUTO (1<<4) /* Auto-Initialize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define BA0_DMR_TR_VERIFY (0<<2) /* Verify Transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define BA0_DMR_TR_WRITE (1<<2) /* Write Transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define BA0_DMR_TR_READ (2<<2) /* Read Transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define BA0_DCR_HTCIE (1<<17) /* Half Terminal Count Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define BA0_DCR_TCIE (1<<16) /* Terminal Count Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define BA0_DCR_MSK (1<<0) /* DMA Mask bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define BA0_FCR0 0x0180 /* FIFO Control 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define BA0_FCR1 0x0184 /* FIFO Control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define BA0_FCR2 0x0188 /* FIFO Control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define BA0_FCR3 0x018c /* FIFO Control 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define BA0_FCR_FEN (1<<31) /* FIFO Enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define BA0_FCR_DACZ (1<<30) /* DAC Zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define BA0_FCR_PSH (1<<29) /* Previous Sample Hold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define BA0_FCR_RS(x) (((x)&0x1f)<<24) /* Right Slot Mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define BA0_FCR_LS(x) (((x)&0x1f)<<16) /* Left Slot Mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define BA0_FCR_SZ(x) (((x)&0x7f)<<8) /* FIFO buffer size (in samples) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define BA0_FCR_OF(x) (((x)&0x7f)<<0) /* FIFO starting offset (in samples) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define BA0_FPDR0 0x0190 /* FIFO Polled Data 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define BA0_FPDR1 0x0194 /* FIFO Polled Data 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define BA0_FPDR2 0x0198 /* FIFO Polled Data 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define BA0_FPDR3 0x019c /* FIFO Polled Data 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define BA0_FCHS 0x020c /* FIFO Channel Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define BA0_FCHS_RCO(x) (1<<(7+(((x)&3)<<3))) /* Right Channel Out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define BA0_FCHS_LCO(x) (1<<(6+(((x)&3)<<3))) /* Left Channel Out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define BA0_FCHS_MRP(x) (1<<(5+(((x)&3)<<3))) /* Move Read Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define BA0_FCHS_FE(x) (1<<(4+(((x)&3)<<3))) /* FIFO Empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define BA0_FCHS_FF(x) (1<<(3+(((x)&3)<<3))) /* FIFO Full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define BA0_FCHS_IOR(x) (1<<(2+(((x)&3)<<3))) /* Internal Overrun Flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define BA0_FCHS_RCI(x) (1<<(1+(((x)&3)<<3))) /* Right Channel In */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define BA0_FCHS_LCI(x) (1<<(0+(((x)&3)<<3))) /* Left Channel In */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define BA0_FSIC0 0x0210 /* FIFO Status and Interrupt Control 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define BA0_FSIC1 0x0214 /* FIFO Status and Interrupt Control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define BA0_FSIC2 0x0218 /* FIFO Status and Interrupt Control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define BA0_FSIC3 0x021c /* FIFO Status and Interrupt Control 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define BA0_FSIC_FIC(x) (((x)&0x7f)<<24) /* FIFO Interrupt Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define BA0_FSIC_FORIE (1<<23) /* FIFO OverRun Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define BA0_FSIC_FURIE (1<<22) /* FIFO UnderRun Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define BA0_FSIC_FSCIE (1<<16) /* FIFO Sample Count Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define BA0_FSIC_FSC(x) (((x)&0x7f)<<8) /* FIFO Sample Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define BA0_FSIC_FOR (1<<7) /* FIFO OverRun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define BA0_FSIC_FUR (1<<6) /* FIFO UnderRun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define BA0_FSIC_FSCR (1<<0) /* FIFO Sample Count Reached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define BA0_PMCS 0x0344 /* Power Management Control/Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define BA0_CWPR 0x03e0 /* Configuration Write Protect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define BA0_EPPMC 0x03e4 /* Extended PCI Power Management Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define BA0_EPPMC_FPDN (1<<14) /* Full Power DowN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define BA0_GPIOR 0x03e8 /* GPIO Pin Interface Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define BA0_SPMC 0x03ec /* Serial Port Power Management Control (& ASDIN2 enable) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define BA0_SPMC_GIPPEN (1<<15) /* GP INT Primary PME# Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define BA0_SPMC_GISPEN (1<<14) /* GP INT Secondary PME# Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define BA0_SPMC_EESPD (1<<9) /* EEPROM Serial Port Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define BA0_SPMC_ASDI2E (1<<8) /* ASDIN2 Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define BA0_SPMC_ASDO (1<<7) /* Asynchronous ASDOUT Assertion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define BA0_SPMC_WUP2 (1<<3) /* Wakeup for Secondary Input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define BA0_SPMC_WUP1 (1<<2) /* Wakeup for Primary Input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define BA0_SPMC_ASYNC (1<<1) /* Asynchronous ASYNC Assertion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define BA0_SPMC_RSTN (1<<0) /* Reset Not! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define BA0_CFLR 0x03f0 /* Configuration Load Register (EEPROM or BIOS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define BA0_CFLR_DEFAULT 0x00000001 /* CFLR must be in AC97 link mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define BA0_IISR 0x03f4 /* ISA Interrupt Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define BA0_TMS 0x03f8 /* Test Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define BA0_SSVID 0x03fc /* Subsystem ID register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define BA0_CLKCR1 0x0400 /* Clock Control Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define BA0_CLKCR1_CLKON (1<<25) /* Read Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define BA0_CLKCR1_DLLRDY (1<<24) /* DLL Ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define BA0_CLKCR1_DLLOS (1<<6) /* DLL Output Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define BA0_CLKCR1_SWCE (1<<5) /* Clock Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define BA0_CLKCR1_DLLP (1<<4) /* DLL PowerUp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define BA0_CLKCR1_DLLSS (((x)&3)<<3) /* DLL Source Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define BA0_FRR 0x0410 /* Feature Reporting Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define BA0_SLT12O 0x041c /* Slot 12 GPIO Output Register for AC-Link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define BA0_SERMC 0x0420 /* Serial Port Master Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define BA0_SERMC_FCRN (1<<27) /* Force Codec Ready Not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define BA0_SERMC_ODSEN2 (1<<25) /* On-Demand Support Enable ASDIN2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define BA0_SERMC_ODSEN1 (1<<24) /* On-Demand Support Enable ASDIN1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define BA0_SERMC_SXLB (1<<21) /* ASDIN2 to ASDOUT Loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define BA0_SERMC_SLB (1<<20) /* ASDOUT to ASDIN2 Loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define BA0_SERMC_LOVF (1<<19) /* Loopback Output Valid Frame bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define BA0_SERMC_TCID(x) (((x)&3)<<16) /* Target Secondary Codec ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define BA0_SERMC_PXLB (5<<1) /* Primary Port External Loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define BA0_SERMC_PLB (4<<1) /* Primary Port Internal Loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define BA0_SERMC_PTC (7<<1) /* Port Timing Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define BA0_SERMC_PTC_AC97 (1<<1) /* AC97 mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define BA0_SERMC_MSPE (1<<0) /* Master Serial Port Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define BA0_SERC1 0x0428 /* Serial Port Configuration 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define BA0_SERC1_SO1F(x) (((x)&7)>>1) /* Primary Output Port Format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define BA0_SERC1_AC97 (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define BA0_SERC1_SO1EN (1<<0) /* Primary Output Port Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define BA0_SERC2 0x042c /* Serial Port Configuration 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define BA0_SERC2_SI1F(x) (((x)&7)>>1) /* Primary Input Port Format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define BA0_SERC2_AC97 (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define BA0_SERC2_SI1EN (1<<0) /* Primary Input Port Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define BA0_SLT12M 0x045c /* Slot 12 Monitor Register for Primary AC-Link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define BA0_ACCTL 0x0460 /* AC'97 Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define BA0_ACCTL_TC (1<<6) /* Target Codec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define BA0_ACCTL_CRW (1<<4) /* 0=Write, 1=Read Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define BA0_ACCTL_DCV (1<<3) /* Dynamic Command Valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define BA0_ACCTL_VFRM (1<<2) /* Valid Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define BA0_ACCTL_ESYN (1<<1) /* Enable Sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define BA0_ACSTS 0x0464 /* AC'97 Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define BA0_ACSTS_VSTS (1<<1) /* Valid Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define BA0_ACSTS_CRDY (1<<0) /* Codec Ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define BA0_ACOSV 0x0468 /* AC'97 Output Slot Valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define BA0_ACOSV_SLV(x) (1<<((x)-3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define BA0_ACCAD 0x046c /* AC'97 Command Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define BA0_ACCDA 0x0470 /* AC'97 Command Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define BA0_ACISV 0x0474 /* AC'97 Input Slot Valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define BA0_ACISV_SLV(x) (1<<((x)-3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define BA0_ACSAD 0x0478 /* AC'97 Status Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define BA0_ACSDA 0x047c /* AC'97 Status Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define BA0_JSPT 0x0480 /* Joystick poll/trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define BA0_JSCTL 0x0484 /* Joystick control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define BA0_JSC1 0x0488 /* Joystick control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define BA0_JSC2 0x048c /* Joystick control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define BA0_JSIO 0x04a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define BA0_MIDCR 0x0490 /* MIDI Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define BA0_MIDCR_MRST (1<<5) /* Reset MIDI Interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define BA0_MIDCR_MLB (1<<4) /* MIDI Loop Back Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define BA0_MIDCR_TIE (1<<3) /* MIDI Transmuit Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define BA0_MIDCR_RIE (1<<2) /* MIDI Receive Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define BA0_MIDCR_RXE (1<<1) /* MIDI Receive Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define BA0_MIDCR_TXE (1<<0) /* MIDI Transmit Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define BA0_MIDCMD 0x0494 /* MIDI Command (wo) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define BA0_MIDSR 0x0494 /* MIDI Status (ro) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define BA0_MIDSR_RDA (1<<15) /* Sticky bit (RBE 1->0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define BA0_MIDSR_TBE (1<<14) /* Sticky bit (TBF 0->1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define BA0_MIDSR_RBE (1<<7) /* Receive Buffer Empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define BA0_MIDSR_TBF (1<<6) /* Transmit Buffer Full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define BA0_MIDWP 0x0498 /* MIDI Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define BA0_MIDRP 0x049c /* MIDI Read (ro) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define BA0_AODSD1 0x04a8 /* AC'97 On-Demand Slot Disable for primary link (ro) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define BA0_AODSD1_NDS(x) (1<<((x)-3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define BA0_AODSD2 0x04ac /* AC'97 On-Demand Slot Disable for secondary link (ro) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define BA0_AODSD2_NDS(x) (1<<((x)-3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define BA0_CFGI 0x04b0 /* Configure Interface (EEPROM interface) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define BA0_SLT12M2 0x04dc /* Slot 12 Monitor Register 2 for secondary AC-link */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define BA0_ACSTS2 0x04e4 /* AC'97 Status Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define BA0_ACISV2 0x04f4 /* AC'97 Input Slot Valid Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define BA0_ACSAD2 0x04f8 /* AC'97 Status Address Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define BA0_ACSDA2 0x04fc /* AC'97 Status Data Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define BA0_FMSR 0x0730 /* FM Synthesis Status (ro) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define BA0_B0AP 0x0730 /* FM Bank 0 Address Port (wo) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define BA0_FMDP 0x0734 /* FM Data Port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define BA0_B1AP 0x0738 /* FM Bank 1 Address Port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define BA0_B1DP 0x073c /* FM Bank 1 Data Port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define BA0_SSPM 0x0740 /* Sound System Power Management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define BA0_SSPM_MIXEN (1<<6) /* Playback SRC + FM/Wavetable MIX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define BA0_SSPM_CSRCEN (1<<5) /* Capture Sample Rate Converter Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define BA0_SSPM_PSRCEN (1<<4) /* Playback Sample Rate Converter Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define BA0_SSPM_JSEN (1<<3) /* Joystick Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define BA0_SSPM_ACLEN (1<<2) /* Serial Port Engine and AC-Link Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define BA0_SSPM_FMEN (1<<1) /* FM Synthesis Block Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define BA0_DACSR 0x0744 /* DAC Sample Rate - Playback SRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define BA0_ADCSR 0x0748 /* ADC Sample Rate - Capture SRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define BA0_SSCR 0x074c /* Sound System Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define BA0_SSCR_HVS1 (1<<23) /* Hardwave Volume Step (0=1,1=2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define BA0_SSCR_MVCS (1<<19) /* Master Volume Codec Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define BA0_SSCR_MVLD (1<<18) /* Master Volume Line Out Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define BA0_SSCR_MVAD (1<<17) /* Master Volume Alternate Out Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define BA0_SSCR_MVMD (1<<16) /* Master Volume Mono Out Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define BA0_SSCR_XLPSRC (1<<8) /* External SRC Loopback Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define BA0_SSCR_LPSRC (1<<7) /* SRC Loopback Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define BA0_SSCR_CDTX (1<<5) /* CD Transfer Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define BA0_SSCR_HVC (1<<3) /* Harware Volume Control Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define BA0_FMLVC 0x0754 /* FM Synthesis Left Volume Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define BA0_FMRVC 0x0758 /* FM Synthesis Right Volume Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define BA0_SRCSA 0x075c /* SRC Slot Assignments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define BA0_PPLVC 0x0760 /* PCM Playback Left Volume Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define BA0_PPRVC 0x0764 /* PCM Playback Right Volume Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define BA0_PASR 0x0768 /* playback sample rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define BA0_CASR 0x076C /* capture sample rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* Source Slot Numbers - Playback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define SRCSLOT_LEFT_PCM_PLAYBACK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define SRCSLOT_RIGHT_PCM_PLAYBACK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define SRCSLOT_PHONE_LINE_1_DAC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define SRCSLOT_CENTER_PCM_PLAYBACK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define SRCSLOT_LEFT_SURROUND_PCM_PLAYBACK 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define SRCSLOT_RIGHT_SURROUND_PCM_PLAYBACK 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define SRCSLOT_LFE_PCM_PLAYBACK 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define SRCSLOT_PHONE_LINE_2_DAC 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define SRCSLOT_HEADSET_DAC 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define SRCSLOT_LEFT_WT 29 /* invalid for BA0_SRCSA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define SRCSLOT_RIGHT_WT 30 /* invalid for BA0_SRCSA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* Source Slot Numbers - Capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define SRCSLOT_LEFT_PCM_RECORD 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define SRCSLOT_RIGHT_PCM_RECORD 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define SRCSLOT_PHONE_LINE_1_ADC 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define SRCSLOT_MIC_ADC 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define SRCSLOT_PHONE_LINE_2_ADC 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define SRCSLOT_HEADSET_ADC 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define SRCSLOT_SECONDARY_LEFT_PCM_RECORD 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define SRCSLOT_SECONDARY_RIGHT_PCM_RECORD 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define SRCSLOT_SECONDARY_PHONE_LINE_1_ADC 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define SRCSLOT_SECONDARY_MIC_ADC 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define SRCSLOT_SECONDARY_PHONE_LINE_2_ADC 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define SRCSLOT_SECONDARY_HEADSET_ADC 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* Source Slot Numbers - Others */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define SRCSLOT_POWER_DOWN 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* MIDI modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define CS4281_MODE_OUTPUT (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define CS4281_MODE_INPUT (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* joystick bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* Bits for JSPT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define JSPT_CAX 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define JSPT_CAY 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define JSPT_CBX 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define JSPT_CBY 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define JSPT_BA1 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define JSPT_BA2 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define JSPT_BB1 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define JSPT_BB2 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* Bits for JSCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define JSCTL_SP_MASK 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define JSCTL_SP_SLOW 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define JSCTL_SP_MEDIUM_SLOW 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define JSCTL_SP_MEDIUM_FAST 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define JSCTL_SP_FAST 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define JSCTL_ARE 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* Data register pairs masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define JSC1_Y1V_MASK 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define JSC1_X1V_MASK 0xFFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define JSC1_Y1V_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define JSC1_X1V_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define JSC2_Y2V_MASK 0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define JSC2_X2V_MASK 0xFFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define JSC2_Y2V_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define JSC2_X2V_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* JS GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define JSIO_DAX 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define JSIO_DAY 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define JSIO_DBX 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define JSIO_DBY 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define JSIO_AXOE 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define JSIO_AYOE 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define JSIO_BXOE 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define JSIO_BYOE 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct cs4281_dma {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) unsigned int regDBA; /* offset to DBA register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) unsigned int regDCA; /* offset to DCA register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) unsigned int regDBC; /* offset to DBC register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) unsigned int regDCC; /* offset to DCC register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) unsigned int regDMR; /* offset to DMR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) unsigned int regDCR; /* offset to DCR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) unsigned int regHDSR; /* offset to HDSR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) unsigned int regFCR; /* offset to FCR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) unsigned int regFSIC; /* offset to FSIC register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) unsigned int valDMR; /* DMA mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) unsigned int valDCR; /* DMA command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) unsigned int valFCR; /* FIFO control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) unsigned int fifo_offset; /* FIFO offset within BA1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) unsigned char left_slot; /* FIFO left slot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) unsigned char right_slot; /* FIFO right slot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) int frag; /* period number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define SUSPEND_REGISTERS 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct cs4281 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) void __iomem *ba0; /* virtual (accessible) address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) void __iomem *ba1; /* virtual (accessible) address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) unsigned long ba0_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) unsigned long ba1_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) int dual_codec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct snd_ac97_bus *ac97_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct snd_ac97 *ac97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct snd_ac97 *ac97_secondary;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct pci_dev *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct snd_rawmidi *rmidi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct snd_rawmidi_substream *midi_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct snd_rawmidi_substream *midi_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct cs4281_dma dma[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) unsigned char src_left_play_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) unsigned char src_right_play_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) unsigned char src_left_rec_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) unsigned char src_right_rec_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) unsigned int spurious_dhtc_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) unsigned int spurious_dtc_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) spinlock_t reg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) unsigned int midcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) unsigned int uartm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct gameport *gameport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) u32 suspend_regs[SUSPEND_REGISTERS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static const struct pci_device_id snd_cs4281_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) { PCI_VDEVICE(CIRRUS, 0x6005), 0, }, /* CS4281 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) MODULE_DEVICE_TABLE(pci, snd_cs4281_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * constants
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define CS4281_FIFO_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * common I/O routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static inline void snd_cs4281_pokeBA0(struct cs4281 *chip, unsigned long offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) writel(val, chip->ba0 + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static inline unsigned int snd_cs4281_peekBA0(struct cs4281 *chip, unsigned long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return readl(chip->ba0 + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static void snd_cs4281_ac97_write(struct snd_ac97 *ac97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) unsigned short reg, unsigned short val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * 3. Write ACCTL = Control Register = 460h for initiating the write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * 5. if DCV not cleared, break and return error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct cs4281 *chip = ac97->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * Setup the AC97 control registers on the CS461x to send the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * appropriate command to the AC97 to perform the read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * ACCAD = Command Address Register = 46Ch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * ACCDA = Command Data Register = 470h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * ACCTL = Control Register = 460h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * set DCV - will clear when process completed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * reset CRW - Write command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * set VFRM - valid frame enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * set ESYN - ASYNC generation enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * set RSTN - ARST# inactive, AC97 codec not reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) snd_cs4281_pokeBA0(chip, BA0_ACCDA, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_VFRM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) BA0_ACCTL_ESYN | (ac97->num ? BA0_ACCTL_TC : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) for (count = 0; count < 2000; count++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * First, we want to wait for a short time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * Now, check to see if the write has completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * ACCTL = 460h, DCV should be reset by now and 460h = 07h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) "AC'97 write problem, reg = 0x%x, val = 0x%x\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static unsigned short snd_cs4281_ac97_read(struct snd_ac97 *ac97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) unsigned short reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct cs4281 *chip = ac97->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) unsigned short result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) // FIXME: volatile is necessary in the following due to a bug of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) // some gcc versions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) volatile int ac97_num = ((volatile struct snd_ac97 *)ac97)->num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * 3. Write ACCTL = Control Register = 460h for initiating the write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * 5. if DCV not cleared, break and return error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * 6. Read ACSTS = Status Register = 464h, check VSTS bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) * Setup the AC97 control registers on the CS461x to send the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) * appropriate command to the AC97 to perform the read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) * ACCAD = Command Address Register = 46Ch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) * ACCDA = Command Data Register = 470h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * ACCTL = Control Register = 460h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) * set DCV - will clear when process completed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * set CRW - Read command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) * set VFRM - valid frame enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * set ESYN - ASYNC generation enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * set RSTN - ARST# inactive, AC97 codec not reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) snd_cs4281_pokeBA0(chip, BA0_ACCAD, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) snd_cs4281_pokeBA0(chip, BA0_ACCDA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_DCV | BA0_ACCTL_CRW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) BA0_ACCTL_VFRM | BA0_ACCTL_ESYN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) (ac97_num ? BA0_ACCTL_TC : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * Wait for the read to occur.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) for (count = 0; count < 500; count++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * First, we want to wait for a short time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * Now, check to see if the read has completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * ACCTL = 460h, DCV should be reset by now and 460h = 17h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (!(snd_cs4281_peekBA0(chip, BA0_ACCTL) & BA0_ACCTL_DCV))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) goto __ok1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) result = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) goto __end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) __ok1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * Wait for the valid status bit to go active.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) for (count = 0; count < 100; count++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * Read the AC97 status register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * ACSTS = Status Register = 464h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * VSTS - Valid Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSTS2 : BA0_ACSTS) & BA0_ACSTS_VSTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) goto __ok2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) "AC'97 read problem (ACSTS_VSTS), reg = 0x%x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) result = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) goto __end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) __ok2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * Read the data returned from the AC97 register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * ACSDA = Status Data Register = 474h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) result = snd_cs4281_peekBA0(chip, ac97_num ? BA0_ACSDA2 : BA0_ACSDA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) __end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) * PCM part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static int snd_cs4281_trigger(struct snd_pcm_substream *substream, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) struct cs4281_dma *dma = substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) struct cs4281 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) spin_lock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) dma->valDCR |= BA0_DCR_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) dma->valFCR |= BA0_FCR_FEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) dma->valDCR &= ~BA0_DCR_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) dma->valFCR &= ~BA0_FCR_FEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR & ~BA0_DMR_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) dma->valDMR |= BA0_DMR_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) dma->valDCR &= ~BA0_DCR_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) dma->valFCR |= BA0_FCR_FEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) dma->valDMR &= ~(BA0_DMR_DMA|BA0_DMR_POLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) dma->valDCR |= BA0_DCR_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) dma->valFCR &= ~BA0_FCR_FEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* Leave wave playback FIFO enabled for FM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (dma->regFCR != BA0_FCR0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) dma->valFCR &= ~BA0_FCR_FEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) spin_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) snd_cs4281_pokeBA0(chip, dma->regDMR, dma->valDMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) snd_cs4281_pokeBA0(chip, dma->regDCR, dma->valDCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) spin_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) static unsigned int snd_cs4281_rate(unsigned int rate, unsigned int *real_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (real_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) *real_rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) /* special "hardcoded" rates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) switch (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) case 8000: return 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) case 11025: return 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) case 16000: return 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) case 22050: return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) case 44100: return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) case 48000: return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) val = 1536000 / rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (real_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) *real_rate = 1536000 / val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) static void snd_cs4281_mode(struct cs4281 *chip, struct cs4281_dma *dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct snd_pcm_runtime *runtime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) int capture, int src)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) int rec_mono;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) dma->valDMR = BA0_DMR_TYPE_SINGLE | BA0_DMR_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) (capture ? BA0_DMR_TR_WRITE : BA0_DMR_TR_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (runtime->channels == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) dma->valDMR |= BA0_DMR_MONO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (snd_pcm_format_unsigned(runtime->format) > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) dma->valDMR |= BA0_DMR_USIGN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (snd_pcm_format_big_endian(runtime->format) > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) dma->valDMR |= BA0_DMR_BEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) switch (snd_pcm_format_width(runtime->format)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) case 8: dma->valDMR |= BA0_DMR_SIZE8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (runtime->channels == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) dma->valDMR |= BA0_DMR_SWAPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) case 32: dma->valDMR |= BA0_DMR_SIZE20; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) dma->frag = 0; /* for workaround */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) dma->valDCR = BA0_DCR_TCIE | BA0_DCR_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (runtime->buffer_size != runtime->period_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) dma->valDCR |= BA0_DCR_HTCIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) /* Initialize DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) snd_cs4281_pokeBA0(chip, dma->regDBA, runtime->dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) snd_cs4281_pokeBA0(chip, dma->regDBC, runtime->buffer_size - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) rec_mono = (chip->dma[1].valDMR & BA0_DMR_MONO) == BA0_DMR_MONO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) (chip->src_right_play_slot << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) (chip->src_left_rec_slot << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) ((rec_mono ? 31 : chip->src_right_rec_slot) << 24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (!src)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) goto __skip_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (!capture) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (dma->left_slot == chip->src_left_play_slot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) snd_BUG_ON(dma->right_slot != chip->src_right_play_slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) snd_cs4281_pokeBA0(chip, BA0_DACSR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (dma->left_slot == chip->src_left_rec_slot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) unsigned int val = snd_cs4281_rate(runtime->rate, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) snd_BUG_ON(dma->right_slot != chip->src_right_rec_slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) snd_cs4281_pokeBA0(chip, BA0_ADCSR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) __skip_src:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) /* Deactivate wave playback FIFO before changing slot assignments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (dma->regFCR == BA0_FCR0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) snd_cs4281_pokeBA0(chip, dma->regFCR, snd_cs4281_peekBA0(chip, dma->regFCR) & ~BA0_FCR_FEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) /* Initialize FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) dma->valFCR = BA0_FCR_LS(dma->left_slot) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) BA0_FCR_RS(capture && (dma->valDMR & BA0_DMR_MONO) ? 31 : dma->right_slot) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) BA0_FCR_SZ(CS4281_FIFO_SIZE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) BA0_FCR_OF(dma->fifo_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | (capture ? BA0_FCR_PSH : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /* Activate FIFO again for FM playback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (dma->regFCR == BA0_FCR0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) snd_cs4281_pokeBA0(chip, dma->regFCR, dma->valFCR | BA0_FCR_FEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /* Clear FIFO Status and Interrupt Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) snd_cs4281_pokeBA0(chip, dma->regFSIC, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static int snd_cs4281_playback_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) struct cs4281_dma *dma = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) struct cs4281 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) snd_cs4281_mode(chip, dma, runtime, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) static int snd_cs4281_capture_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) struct cs4281_dma *dma = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct cs4281 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) snd_cs4281_mode(chip, dma, runtime, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static snd_pcm_uframes_t snd_cs4281_pointer(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) struct cs4281_dma *dma = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) struct cs4281 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) "DCC = 0x%x, buffer_size = 0x%x, jiffies = %li\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) snd_cs4281_peekBA0(chip, dma->regDCC), runtime->buffer_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) return runtime->buffer_size -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) snd_cs4281_peekBA0(chip, dma->regDCC) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) static const struct snd_pcm_hardware snd_cs4281_playback =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .info = SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) SNDRV_PCM_INFO_PAUSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) SNDRV_PCM_INFO_RESUME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .rate_min = 4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .buffer_bytes_max = (512*1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .period_bytes_min = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .period_bytes_max = (512*1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .periods_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .periods_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .fifo_size = CS4281_FIFO_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) static const struct snd_pcm_hardware snd_cs4281_capture =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .info = SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) SNDRV_PCM_INFO_PAUSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) SNDRV_PCM_INFO_RESUME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) SNDRV_PCM_FMTBIT_U16_BE | SNDRV_PCM_FMTBIT_S16_BE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_S32_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) SNDRV_PCM_FMTBIT_U32_BE | SNDRV_PCM_FMTBIT_S32_BE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .rate_min = 4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .buffer_bytes_max = (512*1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .period_bytes_min = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .period_bytes_max = (512*1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .periods_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .periods_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .fifo_size = CS4281_FIFO_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static int snd_cs4281_playback_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) struct cs4281 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) struct cs4281_dma *dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) dma = &chip->dma[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) dma->substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) dma->left_slot = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) dma->right_slot = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) runtime->private_data = dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) runtime->hw = snd_cs4281_playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) /* should be detected from the AC'97 layer, but it seems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) that although CS4297A rev B reports 18-bit ADC resolution,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) samples are 20-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) static int snd_cs4281_capture_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) struct cs4281 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) struct cs4281_dma *dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) dma = &chip->dma[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) dma->substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) dma->left_slot = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) dma->right_slot = 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) runtime->private_data = dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) runtime->hw = snd_cs4281_capture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /* should be detected from the AC'97 layer, but it seems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) that although CS4297A rev B reports 18-bit ADC resolution,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) samples are 20-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) static int snd_cs4281_playback_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) struct cs4281_dma *dma = substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) dma->substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) static int snd_cs4281_capture_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) struct cs4281_dma *dma = substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) dma->substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) static const struct snd_pcm_ops snd_cs4281_playback_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .open = snd_cs4281_playback_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .close = snd_cs4281_playback_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .prepare = snd_cs4281_playback_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .trigger = snd_cs4281_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .pointer = snd_cs4281_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) static const struct snd_pcm_ops snd_cs4281_capture_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .open = snd_cs4281_capture_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .close = snd_cs4281_capture_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .prepare = snd_cs4281_capture_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .trigger = snd_cs4281_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .pointer = snd_cs4281_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static int snd_cs4281_pcm(struct cs4281 *chip, int device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) err = snd_pcm_new(chip->card, "CS4281", device, 1, 1, &pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4281_playback_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4281_capture_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) pcm->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) pcm->info_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) strcpy(pcm->name, "CS4281");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) chip->pcm = pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) 64*1024, 512*1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) * Mixer section
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #define CS_VOL_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) static int snd_cs4281_info_volume(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) uinfo->count = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) uinfo->value.integer.max = CS_VOL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) static int snd_cs4281_get_volume(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) struct cs4281 *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) int regL = (kcontrol->private_value >> 16) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) int regR = kcontrol->private_value & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) int volL, volR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) ucontrol->value.integer.value[0] = volL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) ucontrol->value.integer.value[1] = volR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) static int snd_cs4281_put_volume(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) struct cs4281 *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) int change = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) int regL = (kcontrol->private_value >> 16) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) int regR = kcontrol->private_value & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) int volL, volR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) volL = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regL) & CS_VOL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) volR = CS_VOL_MASK - (snd_cs4281_peekBA0(chip, regR) & CS_VOL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) if (ucontrol->value.integer.value[0] != volL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) volL = CS_VOL_MASK - (ucontrol->value.integer.value[0] & CS_VOL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) snd_cs4281_pokeBA0(chip, regL, volL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) if (ucontrol->value.integer.value[1] != volR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) volR = CS_VOL_MASK - (ucontrol->value.integer.value[1] & CS_VOL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) snd_cs4281_pokeBA0(chip, regR, volR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) change = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) static const DECLARE_TLV_DB_SCALE(db_scale_dsp, -4650, 150, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) static const struct snd_kcontrol_new snd_cs4281_fm_vol =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .name = "Synth Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) .info = snd_cs4281_info_volume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) .get = snd_cs4281_get_volume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) .put = snd_cs4281_put_volume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) .private_value = ((BA0_FMLVC << 16) | BA0_FMRVC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) .tlv = { .p = db_scale_dsp },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) static const struct snd_kcontrol_new snd_cs4281_pcm_vol =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) .name = "PCM Stream Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) .info = snd_cs4281_info_volume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .get = snd_cs4281_get_volume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .put = snd_cs4281_put_volume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .private_value = ((BA0_PPLVC << 16) | BA0_PPRVC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) .tlv = { .p = db_scale_dsp },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) static void snd_cs4281_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) struct cs4281 *chip = bus->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) chip->ac97_bus = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) static void snd_cs4281_mixer_free_ac97(struct snd_ac97 *ac97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) struct cs4281 *chip = ac97->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) if (ac97->num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) chip->ac97_secondary = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) chip->ac97 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) static int snd_cs4281_mixer(struct cs4281 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) struct snd_card *card = chip->card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) struct snd_ac97_template ac97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) static const struct snd_ac97_bus_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) .write = snd_cs4281_ac97_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) .read = snd_cs4281_ac97_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) chip->ac97_bus->private_free = snd_cs4281_mixer_free_ac97_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) memset(&ac97, 0, sizeof(ac97));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) ac97.private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) ac97.private_free = snd_cs4281_mixer_free_ac97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) if (chip->dual_codec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) ac97.num = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97_secondary)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_fm_vol, chip))) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cs4281_pcm_vol, chip))) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) * proc interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) static void snd_cs4281_proc_read(struct snd_info_entry *entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) struct snd_info_buffer *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) struct cs4281 *chip = entry->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) snd_iprintf(buffer, "Cirrus Logic CS4281\n\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) snd_iprintf(buffer, "Spurious half IRQs : %u\n", chip->spurious_dhtc_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) snd_iprintf(buffer, "Spurious end IRQs : %u\n", chip->spurious_dtc_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) static ssize_t snd_cs4281_BA0_read(struct snd_info_entry *entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) void *file_private_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) struct file *file, char __user *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) size_t count, loff_t pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) struct cs4281 *chip = entry->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) if (copy_to_user_fromio(buf, chip->ba0 + pos, count))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) static ssize_t snd_cs4281_BA1_read(struct snd_info_entry *entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) void *file_private_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) struct file *file, char __user *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) size_t count, loff_t pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) struct cs4281 *chip = entry->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) if (copy_to_user_fromio(buf, chip->ba1 + pos, count))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) static const struct snd_info_entry_ops snd_cs4281_proc_ops_BA0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .read = snd_cs4281_BA0_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) static const struct snd_info_entry_ops snd_cs4281_proc_ops_BA1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) .read = snd_cs4281_BA1_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) static void snd_cs4281_proc_init(struct cs4281 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) struct snd_info_entry *entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) snd_card_ro_proc_new(chip->card, "cs4281", chip, snd_cs4281_proc_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) if (! snd_card_proc_new(chip->card, "cs4281_BA0", &entry)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) entry->content = SNDRV_INFO_CONTENT_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) entry->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) entry->c.ops = &snd_cs4281_proc_ops_BA0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) entry->size = CS4281_BA0_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if (! snd_card_proc_new(chip->card, "cs4281_BA1", &entry)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) entry->content = SNDRV_INFO_CONTENT_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) entry->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) entry->c.ops = &snd_cs4281_proc_ops_BA1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) entry->size = CS4281_BA1_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) * joystick support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) #if IS_REACHABLE(CONFIG_GAMEPORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) static void snd_cs4281_gameport_trigger(struct gameport *gameport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) struct cs4281 *chip = gameport_get_port_data(gameport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) if (snd_BUG_ON(!chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) snd_cs4281_pokeBA0(chip, BA0_JSPT, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) static unsigned char snd_cs4281_gameport_read(struct gameport *gameport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) struct cs4281 *chip = gameport_get_port_data(gameport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) if (snd_BUG_ON(!chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) return snd_cs4281_peekBA0(chip, BA0_JSPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) #ifdef COOKED_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) static int snd_cs4281_gameport_cooked_read(struct gameport *gameport,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) int *axes, int *buttons)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) struct cs4281 *chip = gameport_get_port_data(gameport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) unsigned js1, js2, jst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) if (snd_BUG_ON(!chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) js1 = snd_cs4281_peekBA0(chip, BA0_JSC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) js2 = snd_cs4281_peekBA0(chip, BA0_JSC2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) jst = snd_cs4281_peekBA0(chip, BA0_JSPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) *buttons = (~jst >> 4) & 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) for (jst = 0; jst < 4; ++jst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) if (axes[jst] == 0xFFFF) axes[jst] = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) #define snd_cs4281_gameport_cooked_read NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) static int snd_cs4281_gameport_open(struct gameport *gameport, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) #ifdef COOKED_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) case GAMEPORT_MODE_COOKED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) case GAMEPORT_MODE_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) static int snd_cs4281_create_gameport(struct cs4281 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) struct gameport *gp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) chip->gameport = gp = gameport_allocate_port();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (!gp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) "cannot allocate memory for gameport\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) gameport_set_name(gp, "CS4281 Gameport");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) gameport_set_dev_parent(gp, &chip->pci->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) gp->open = snd_cs4281_gameport_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) gp->read = snd_cs4281_gameport_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) gp->trigger = snd_cs4281_gameport_trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) gp->cooked_read = snd_cs4281_gameport_cooked_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) gameport_set_port_data(gp, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) snd_cs4281_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) snd_cs4281_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) gameport_register_port(gp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) static void snd_cs4281_free_gameport(struct cs4281 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) if (chip->gameport) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) gameport_unregister_port(chip->gameport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) chip->gameport = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) static inline int snd_cs4281_create_gameport(struct cs4281 *chip) { return -ENOSYS; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) static inline void snd_cs4281_free_gameport(struct cs4281 *chip) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) #endif /* IS_REACHABLE(CONFIG_GAMEPORT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) static int snd_cs4281_free(struct cs4281 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) snd_cs4281_free_gameport(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) /* Mask interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) /* Stop the DLL Clock logic. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) /* Sound System Power Management - Turn Everything OFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) /* PCI interface - D3 state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) pci_set_power_state(chip->pci, PCI_D3hot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) if (chip->irq >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) free_irq(chip->irq, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) iounmap(chip->ba0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) iounmap(chip->ba1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) pci_release_regions(chip->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) pci_disable_device(chip->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) kfree(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) static int snd_cs4281_dev_free(struct snd_device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) struct cs4281 *chip = device->device_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) return snd_cs4281_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) static int snd_cs4281_chip_init(struct cs4281 *chip); /* defined below */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) static int snd_cs4281_create(struct snd_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) struct cs4281 **rchip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) int dual_codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) struct cs4281 *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) static const struct snd_device_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) .dev_free = snd_cs4281_dev_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) *rchip = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) if ((err = pci_enable_device(pci)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) chip = kzalloc(sizeof(*chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) if (chip == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) spin_lock_init(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) chip->card = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) chip->pci = pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) chip->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) pci_set_master(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) if (dual_codec < 0 || dual_codec > 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) dev_err(card->dev, "invalid dual_codec option %d\n", dual_codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) dual_codec = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) chip->dual_codec = dual_codec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) if ((err = pci_request_regions(pci, "CS4281")) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) kfree(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) chip->ba0_addr = pci_resource_start(pci, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) chip->ba1_addr = pci_resource_start(pci, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) chip->ba0 = pci_ioremap_bar(pci, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) chip->ba1 = pci_ioremap_bar(pci, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) if (!chip->ba0 || !chip->ba1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) snd_cs4281_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) if (request_irq(pci->irq, snd_cs4281_interrupt, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) KBUILD_MODNAME, chip)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) snd_cs4281_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) chip->irq = pci->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) card->sync_irq = chip->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) tmp = snd_cs4281_chip_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) if (tmp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) snd_cs4281_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) return tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) snd_cs4281_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) snd_cs4281_proc_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) *rchip = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) static int snd_cs4281_chip_init(struct cs4281 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) unsigned long end_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) int retry_count = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) /* Having EPPMC.FPDN=1 prevent proper chip initialisation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) tmp = snd_cs4281_peekBA0(chip, BA0_EPPMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) if (tmp & BA0_EPPMC_FPDN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) snd_cs4281_pokeBA0(chip, BA0_EPPMC, tmp & ~BA0_EPPMC_FPDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) __retry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) if (tmp != BA0_CFLR_DEFAULT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) snd_cs4281_pokeBA0(chip, BA0_CFLR, BA0_CFLR_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) tmp = snd_cs4281_peekBA0(chip, BA0_CFLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) if (tmp != BA0_CFLR_DEFAULT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) "CFLR setup failed (0x%x)\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) /* Set the 'Configuration Write Protect' register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) * to 4281h. Allows vendor-defined configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) * space between 0e4h and 0ffh to be written. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) snd_cs4281_pokeBA0(chip, BA0_CWPR, 0x4281);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC1)) != (BA0_SERC1_SO1EN | BA0_SERC1_AC97)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) "SERC1 AC'97 check failed (0x%x)\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) if ((tmp = snd_cs4281_peekBA0(chip, BA0_SERC2)) != (BA0_SERC2_SI1EN | BA0_SERC2_AC97)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) "SERC2 AC'97 check failed (0x%x)\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) /* Sound System Power Management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) snd_cs4281_pokeBA0(chip, BA0_SSPM, BA0_SSPM_MIXEN | BA0_SSPM_CSRCEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) BA0_SSPM_PSRCEN | BA0_SSPM_JSEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) BA0_SSPM_ACLEN | BA0_SSPM_FMEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) /* Serial Port Power Management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) /* Blast the clock control register to zero so that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) * PLL starts out in a known state, and blast the master serial
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) * port control register to zero so that the serial ports also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) * start out in a known state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) /* Make ESYN go to zero to turn off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) * the Sync pulse on the AC97 link. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) snd_cs4281_pokeBA0(chip, BA0_ACCTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) /* Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) * spec) and then drive it high. This is done for non AC97 modes since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) * there might be logic external to the CS4281 that uses the ARST# line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) * for a reset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) if (chip->dual_codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) snd_cs4281_pokeBA0(chip, BA0_SPMC, BA0_SPMC_RSTN | BA0_SPMC_ASDI2E);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) * Set the serial port timing configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) snd_cs4281_pokeBA0(chip, BA0_SERMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) (chip->dual_codec ? BA0_SERMC_TCID(chip->dual_codec) : BA0_SERMC_TCID(1)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) BA0_SERMC_PTC_AC97 | BA0_SERMC_MSPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) * Start the DLL Clock logic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_DLLP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_SWCE | BA0_CLKCR1_DLLP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) * Wait for the DLL ready signal from the clock logic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) end_time = jiffies + HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) * Read the AC97 status register to see if we've seen a CODEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) * signal from the AC97 codec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) goto __ok0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) schedule_timeout_uninterruptible(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) } while (time_after_eq(end_time, jiffies));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) dev_err(chip->card->dev, "DLLRDY not seen\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) __ok0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) * The first thing we do here is to enable sync generation. As soon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) * as we start receiving bit clock, we'll start producing the SYNC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) * signal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_ESYN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) * Wait for the codec ready signal from the AC97 codec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) end_time = jiffies + HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) * Read the AC97 status register to see if we've seen a CODEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) * signal from the AC97 codec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) if (snd_cs4281_peekBA0(chip, BA0_ACSTS) & BA0_ACSTS_CRDY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) goto __ok1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) schedule_timeout_uninterruptible(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) } while (time_after_eq(end_time, jiffies));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) "never read codec ready from AC'97 (0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) snd_cs4281_peekBA0(chip, BA0_ACSTS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) __ok1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) if (chip->dual_codec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) end_time = jiffies + HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) if (snd_cs4281_peekBA0(chip, BA0_ACSTS2) & BA0_ACSTS_CRDY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) goto __codec2_ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) schedule_timeout_uninterruptible(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) } while (time_after_eq(end_time, jiffies));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) dev_info(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) "secondary codec doesn't respond. disable it...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) chip->dual_codec = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) __codec2_ok: ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) * Assert the valid frame signal so that we can start sending commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) * to the AC97 codec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) snd_cs4281_pokeBA0(chip, BA0_ACCTL, BA0_ACCTL_VFRM | BA0_ACCTL_ESYN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) * Wait until we've sampled input slots 3 and 4 as valid, meaning that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) * the codec is pumping ADC data across the AC-link.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) end_time = jiffies + HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) * Read the input slot valid register and see if input slots 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) * 4 are valid yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) if ((snd_cs4281_peekBA0(chip, BA0_ACISV) & (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4))) == (BA0_ACISV_SLV(3) | BA0_ACISV_SLV(4)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) goto __ok2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) schedule_timeout_uninterruptible(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) } while (time_after_eq(end_time, jiffies));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) if (--retry_count > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) goto __retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) dev_err(chip->card->dev, "never read ISV3 and ISV4 from AC'97\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) __ok2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) * Now, assert valid frame and the slot 3 and 4 valid bits. This will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) * commense the transfer of digital audio data to the AC97 codec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) snd_cs4281_pokeBA0(chip, BA0_ACOSV, BA0_ACOSV_SLV(3) | BA0_ACOSV_SLV(4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) * Initialize DMA structures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) for (tmp = 0; tmp < 4; tmp++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) struct cs4281_dma *dma = &chip->dma[tmp];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) dma->regDBA = BA0_DBA0 + (tmp * 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) dma->regDCA = BA0_DCA0 + (tmp * 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) dma->regDBC = BA0_DBC0 + (tmp * 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) dma->regDCC = BA0_DCC0 + (tmp * 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) dma->regDMR = BA0_DMR0 + (tmp * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) dma->regDCR = BA0_DCR0 + (tmp * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) dma->regHDSR = BA0_HDSR0 + (tmp * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) dma->regFCR = BA0_FCR0 + (tmp * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) dma->regFSIC = BA0_FSIC0 + (tmp * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) dma->fifo_offset = tmp * CS4281_FIFO_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) snd_cs4281_pokeBA0(chip, dma->regFCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) BA0_FCR_LS(31) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) BA0_FCR_RS(31) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) BA0_FCR_SZ(CS4281_FIFO_SIZE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) BA0_FCR_OF(dma->fifo_offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) chip->src_left_play_slot = 0; /* AC'97 left PCM playback (3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) chip->src_right_play_slot = 1; /* AC'97 right PCM playback (4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) chip->src_left_rec_slot = 10; /* AC'97 left PCM record (3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) chip->src_right_rec_slot = 11; /* AC'97 right PCM record (4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) /* Activate wave playback FIFO for FM playback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) chip->dma[0].valFCR = BA0_FCR_FEN | BA0_FCR_LS(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) BA0_FCR_RS(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) BA0_FCR_SZ(CS4281_FIFO_SIZE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) BA0_FCR_OF(chip->dma[0].fifo_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) snd_cs4281_pokeBA0(chip, chip->dma[0].regFCR, chip->dma[0].valFCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) snd_cs4281_pokeBA0(chip, BA0_SRCSA, (chip->src_left_play_slot << 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) (chip->src_right_play_slot << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) (chip->src_left_rec_slot << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) (chip->src_right_rec_slot << 24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) /* Initialize digital volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) snd_cs4281_pokeBA0(chip, BA0_PPLVC, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) snd_cs4281_pokeBA0(chip, BA0_PPRVC, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) /* Enable IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) /* Unmask interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) snd_cs4281_pokeBA0(chip, BA0_HIMR, 0x7fffffff & ~(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) BA0_HISR_MIDI |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) BA0_HISR_DMAI |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) BA0_HISR_DMA(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) BA0_HISR_DMA(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) BA0_HISR_DMA(2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) BA0_HISR_DMA(3)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) * MIDI section
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) static void snd_cs4281_midi_reset(struct cs4281 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr | BA0_MIDCR_MRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) static int snd_cs4281_midi_input_open(struct snd_rawmidi_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) struct cs4281 *chip = substream->rmidi->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) chip->midcr |= BA0_MIDCR_RXE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) chip->midi_input = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) snd_cs4281_midi_reset(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) static int snd_cs4281_midi_input_close(struct snd_rawmidi_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) struct cs4281 *chip = substream->rmidi->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) chip->midcr &= ~(BA0_MIDCR_RXE | BA0_MIDCR_RIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) chip->midi_input = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) if (!(chip->uartm & CS4281_MODE_OUTPUT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) snd_cs4281_midi_reset(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) chip->uartm &= ~CS4281_MODE_INPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) static int snd_cs4281_midi_output_open(struct snd_rawmidi_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) struct cs4281 *chip = substream->rmidi->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) chip->uartm |= CS4281_MODE_OUTPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) chip->midcr |= BA0_MIDCR_TXE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) chip->midi_output = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) if (!(chip->uartm & CS4281_MODE_INPUT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) snd_cs4281_midi_reset(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) static int snd_cs4281_midi_output_close(struct snd_rawmidi_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) struct cs4281 *chip = substream->rmidi->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) chip->midcr &= ~(BA0_MIDCR_TXE | BA0_MIDCR_TIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) chip->midi_output = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) if (!(chip->uartm & CS4281_MODE_INPUT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) snd_cs4281_midi_reset(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) chip->uartm &= ~CS4281_MODE_OUTPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) static void snd_cs4281_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) struct cs4281 *chip = substream->rmidi->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) if (up) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) if ((chip->midcr & BA0_MIDCR_RIE) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) chip->midcr |= BA0_MIDCR_RIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) if (chip->midcr & BA0_MIDCR_RIE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) chip->midcr &= ~BA0_MIDCR_RIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) static void snd_cs4281_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) struct cs4281 *chip = substream->rmidi->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) unsigned char byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) if (up) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) if ((chip->midcr & BA0_MIDCR_TIE) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) chip->midcr |= BA0_MIDCR_TIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) while ((chip->midcr & BA0_MIDCR_TIE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) (snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) chip->midcr &= ~BA0_MIDCR_TIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) snd_cs4281_pokeBA0(chip, BA0_MIDWP, byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) if (chip->midcr & BA0_MIDCR_TIE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) chip->midcr &= ~BA0_MIDCR_TIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) static const struct snd_rawmidi_ops snd_cs4281_midi_output =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) .open = snd_cs4281_midi_output_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) .close = snd_cs4281_midi_output_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) .trigger = snd_cs4281_midi_output_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) static const struct snd_rawmidi_ops snd_cs4281_midi_input =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) .open = snd_cs4281_midi_input_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) .close = snd_cs4281_midi_input_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) .trigger = snd_cs4281_midi_input_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) static int snd_cs4281_midi(struct cs4281 *chip, int device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) struct snd_rawmidi *rmidi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) if ((err = snd_rawmidi_new(chip->card, "CS4281", device, 1, 1, &rmidi)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) strcpy(rmidi->name, "CS4281");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs4281_midi_output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs4281_midi_input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) rmidi->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) chip->rmidi = rmidi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) * Interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) static irqreturn_t snd_cs4281_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) struct cs4281 *chip = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) unsigned int status, dma, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) struct cs4281_dma *cdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) if (chip == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) status = snd_cs4281_peekBA0(chip, BA0_HISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) if ((status & 0x7fffffff) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) if (status & (BA0_HISR_DMA(0)|BA0_HISR_DMA(1)|BA0_HISR_DMA(2)|BA0_HISR_DMA(3))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) for (dma = 0; dma < 4; dma++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) if (status & BA0_HISR_DMA(dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) cdma = &chip->dma[dma];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) spin_lock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) /* ack DMA IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) val = snd_cs4281_peekBA0(chip, cdma->regHDSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) /* workaround, sometimes CS4281 acknowledges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) /* end or middle transfer position twice */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) cdma->frag++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) if ((val & BA0_HDSR_DHTC) && !(cdma->frag & 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) cdma->frag--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) chip->spurious_dhtc_irq++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) spin_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) if ((val & BA0_HDSR_DTC) && (cdma->frag & 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) cdma->frag--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) chip->spurious_dtc_irq++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) spin_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) spin_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) snd_pcm_period_elapsed(cdma->substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) if ((status & BA0_HISR_MIDI) && chip->rmidi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) unsigned char c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) spin_lock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_RBE) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) c = snd_cs4281_peekBA0(chip, BA0_MIDRP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) if ((chip->midcr & BA0_MIDCR_RIE) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) snd_rawmidi_receive(chip->midi_input, &c, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) while ((snd_cs4281_peekBA0(chip, BA0_MIDSR) & BA0_MIDSR_TBF) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) if ((chip->midcr & BA0_MIDCR_TIE) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) chip->midcr &= ~BA0_MIDCR_TIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) snd_cs4281_pokeBA0(chip, BA0_MIDCR, chip->midcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) snd_cs4281_pokeBA0(chip, BA0_MIDWP, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) spin_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) /* EOI to the PCI part... reenables interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_EOI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) * OPL3 command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) static void snd_cs4281_opl3_command(struct snd_opl3 *opl3, unsigned short cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) unsigned char val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) struct cs4281 *chip = opl3->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) void __iomem *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) if (cmd & OPL3_RIGHT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) port = chip->ba0 + BA0_B1AP; /* right port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) port = chip->ba0 + BA0_B0AP; /* left port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) spin_lock_irqsave(&opl3->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) writel((unsigned int)cmd, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) writel((unsigned int)val, port + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) udelay(30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) spin_unlock_irqrestore(&opl3->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) static int snd_cs4281_probe(struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) const struct pci_device_id *pci_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) static int dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) struct cs4281 *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) struct snd_opl3 *opl3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) if (dev >= SNDRV_CARDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) if (!enable[dev]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) dev++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) 0, &card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) if ((err = snd_cs4281_create(card, pci, &chip, dual_codec[dev])) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) card->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) if ((err = snd_cs4281_mixer(chip)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) if ((err = snd_cs4281_pcm(chip, 0)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) if ((err = snd_cs4281_midi(chip, 0)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) if ((err = snd_opl3_new(card, OPL3_HW_OPL3_CS4281, &opl3)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) opl3->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) opl3->command = snd_cs4281_opl3_command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) snd_opl3_init(opl3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) snd_cs4281_create_gameport(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) strcpy(card->driver, "CS4281");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) strcpy(card->shortname, "Cirrus Logic CS4281");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) sprintf(card->longname, "%s at 0x%lx, irq %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) card->shortname,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) chip->ba0_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) chip->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) if ((err = snd_card_register(card)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) pci_set_drvdata(pci, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) dev++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) static void snd_cs4281_remove(struct pci_dev *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) snd_card_free(pci_get_drvdata(pci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) * Power Management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) static const int saved_regs[SUSPEND_REGISTERS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) BA0_JSCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) BA0_GPIOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) BA0_SSCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) BA0_MIDCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) BA0_SRCSA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) BA0_PASR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) BA0_CASR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) BA0_DACSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) BA0_ADCSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) BA0_FMLVC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) BA0_FMRVC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) BA0_PPLVC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) BA0_PPRVC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) #define CLKCR1_CKRA 0x00010000L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) static int cs4281_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) struct cs4281 *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) u32 ulCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) snd_ac97_suspend(chip->ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) snd_ac97_suspend(chip->ac97_secondary);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) ulCLK |= CLKCR1_CKRA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) /* Disable interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) snd_cs4281_pokeBA0(chip, BA0_HICR, BA0_HICR_CHGM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) /* remember the status registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) if (saved_regs[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) chip->suspend_regs[i] = snd_cs4281_peekBA0(chip, saved_regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) /* Turn off the serial ports. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) snd_cs4281_pokeBA0(chip, BA0_SERMC, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) /* Power off FM, Joystick, AC link, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) snd_cs4281_pokeBA0(chip, BA0_SSPM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) /* DLL off. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) /* AC link off. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) snd_cs4281_pokeBA0(chip, BA0_SPMC, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) ulCLK &= ~CLKCR1_CKRA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) static int cs4281_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) struct cs4281 *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) u32 ulCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) ulCLK |= CLKCR1_CKRA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) snd_cs4281_chip_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) /* restore the status registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) if (saved_regs[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) snd_cs4281_pokeBA0(chip, saved_regs[i], chip->suspend_regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) snd_ac97_resume(chip->ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) snd_ac97_resume(chip->ac97_secondary);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) ulCLK &= ~CLKCR1_CKRA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) snd_power_change_state(card, SNDRV_CTL_POWER_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) static SIMPLE_DEV_PM_OPS(cs4281_pm, cs4281_suspend, cs4281_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) #define CS4281_PM_OPS &cs4281_pm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) #define CS4281_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) static struct pci_driver cs4281_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) .name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) .id_table = snd_cs4281_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) .probe = snd_cs4281_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) .remove = snd_cs4281_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) .pm = CS4281_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) module_pci_driver(cs4281_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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