^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for C-Media CMI8338 and 8738 PCI soundcards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) /* Does not work. Warning may block system in capture mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /* #define USE_VAR48KRATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/gameport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <sound/info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <sound/control.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <sound/rawmidi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <sound/mpu401.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <sound/opl3.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <sound/sb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <sound/asoundef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) MODULE_DESCRIPTION("C-Media CMI8x38 PCI");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8738},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) "{C-Media,CMI8738B},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) "{C-Media,CMI8338A},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) "{C-Media,CMI8338B}}");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #if IS_REACHABLE(CONFIG_GAMEPORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SUPPORT_JOYSTICK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable switches */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static long mpu_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static long fm_port[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static bool soft_ac3[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)]=1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #ifdef SUPPORT_JOYSTICK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static int joystick_port[SNDRV_CARDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) module_param_array(index, int, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) MODULE_PARM_DESC(index, "Index value for C-Media PCI soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) module_param_array(id, charp, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) MODULE_PARM_DESC(id, "ID string for C-Media PCI soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) module_param_array(enable, bool, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) MODULE_PARM_DESC(enable, "Enable C-Media PCI soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) module_param_hw_array(mpu_port, long, ioport, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MODULE_PARM_DESC(mpu_port, "MPU-401 port.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) module_param_hw_array(fm_port, long, ioport, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MODULE_PARM_DESC(fm_port, "FM port.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) module_param_array(soft_ac3, bool, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) MODULE_PARM_DESC(soft_ac3, "Software-conversion of raw SPDIF packets (model 033 only).");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #ifdef SUPPORT_JOYSTICK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) module_param_hw_array(joystick_port, int, ioport, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) MODULE_PARM_DESC(joystick_port, "Joystick port address.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * CM8x38 registers definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CM_REG_FUNCTRL0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CM_RST_CH1 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CM_RST_CH0 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CM_CHEN1 0x00020000 /* ch1: enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CM_CHEN0 0x00010000 /* ch0: enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CM_PAUSE1 0x00000008 /* ch1: pause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CM_PAUSE0 0x00000004 /* ch0: pause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CM_CHADC1 0x00000002 /* ch1, 0:playback, 1:record */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CM_REG_FUNCTRL1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CM_DSFC_MASK 0x0000E000 /* channel 1 (DAC?) sampling frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CM_DSFC_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CM_ASFC_MASK 0x00001C00 /* channel 0 (ADC?) sampling frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CM_ASFC_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/IN -> OUT loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CM_BREQ 0x00000010 /* bus master enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CM_UART_EN 0x00000004 /* legacy UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CM_JYSTK_EN 0x00000002 /* legacy joystick */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CM_ZVPORT 0x00000001 /* ZVPORT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CM_REG_CHFORMAT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CM_CHB3D5C 0x80000000 /* 5,6 channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CM_FMOFFSET2 0x40000000 /* initial FM PCM offset 2 when Fmute=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CM_CHB3D 0x20000000 /* 4 channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CM_CHIP_MASK1 0x1f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CM_CHIP_037 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CM_SETLAT48 0x00800000 /* set latency timer 48h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CM_EDGEIRQ 0x00400000 /* emulated edge trigger legacy IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CM_SPD24SEL39 0x00200000 /* 24-bit spdif: model 039 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* #define CM_SPDIF_INVERSE 0x00010000 */ /* ??? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CM_ADCBITLEN_MASK 0x0000C000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CM_ADCBITLEN_16 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CM_ADCBITLEN_15 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CM_ADCBITLEN_14 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CM_ADCBITLEN_13 0x0000C000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CM_ADCDACLEN_MASK 0x00003000 /* model 037 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CM_ADCDACLEN_060 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CM_ADCDACLEN_066 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CM_ADCDACLEN_130 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CM_ADCDACLEN_280 0x00003000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CM_ADCDLEN_MASK 0x00003000 /* model 039 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CM_ADCDLEN_ORIGINAL 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CM_ADCDLEN_EXTRA 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CM_ADCDLEN_24K 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CM_ADCDLEN_WEIGHT 0x00003000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CM_CH1_SRATE_176K 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CM_CH1_SRATE_96K 0x00000800 /* model 055? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CM_CH1_SRATE_88K 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CM_CH0_SRATE_176K 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CM_CH0_SRATE_96K 0x00000200 /* model 055? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CM_CH0_SRATE_88K 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CM_CH0_SRATE_128K 0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CM_CH0_SRATE_MASK 0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CM_DBLSPDS 0x00000040 /* double SPDIF sample rate 88.2/96 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CM_POLVALID 0x00000020 /* inverse SPDIF/IN valid bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CM_SPDLOCKED 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CM_CH1FMT_MASK 0x0000000C /* bit 3: 16 bits, bit 2: stereo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CM_CH1FMT_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CM_CH0FMT_MASK 0x00000003 /* bit 1: 16 bits, bit 0: stereo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CM_CH0FMT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CM_REG_INT_HLDCLR 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CM_CHIP_MASK2 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CM_CHIP_8768 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CM_CHIP_055 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CM_CHIP_039 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CM_CHIP_039_6CH 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CM_UNKNOWN_INT_EN 0x00080000 /* ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CM_TDMA_INT_EN 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CM_CH1_INT_EN 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CM_CH0_INT_EN 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define CM_REG_INT_STATUS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CM_INTR 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CM_VCO 0x08000000 /* Voice Control? CMI8738 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CM_MCBINT 0x04000000 /* Master Control Block abort cond.? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CM_UARTINT 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CM_LTDMAINT 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CM_HTDMAINT 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CM_XDO46 0x00000080 /* Modell 033? Direct programming EEPROM (read data register) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CM_LHBTOG 0x00000040 /* High/Low status from DMA ctrl register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CM_LEG_HDMA 0x00000020 /* Legacy is in High DMA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define CM_LEG_STEREO 0x00000010 /* Legacy is in Stereo mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define CM_CH1BUSY 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define CM_CH0BUSY 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define CM_CHINT1 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define CM_CHINT0 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CM_REG_LEGACY_CTRL 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CM_NXCHG 0x80000000 /* don't map base reg dword->sample */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CM_VMPU_330 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CM_VMPU_320 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CM_VMPU_310 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define CM_VMPU_300 0x60000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define CM_ENWR8237 0x10000000 /* enable bus master to write 8237 base reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define CM_VSBSEL_220 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define CM_VSBSEL_240 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define CM_VSBSEL_260 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define CM_VSBSEL_280 0x0C000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define CM_FMSEL_MASK 0x03000000 /* FM OPL3 base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define CM_FMSEL_388 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define CM_FMSEL_3C8 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define CM_FMSEL_3E0 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define CM_FMSEL_3E8 0x03000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define CM_ENSPDOUT 0x00800000 /* enable XSPDIF/OUT to I/O interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define CM_SPDCOPYRHT 0x00400000 /* spdif in/out copyright bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define CM_INVIDWEN 0x00100000 /* internal vendor ID write enable, model 039? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define CM_SETRETRY 0x00100000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define CM_C_EEACCESS 0x00080000 /* direct programming eeprom regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define CM_C_EECS 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define CM_C_EEDI46 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define CM_C_EECK46 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define CM_CHB3D6C 0x00008000 /* 5.1 channels support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define CM_CENTR2LIN 0x00004000 /* line-in as center out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define CM_BASE2LIN 0x00002000 /* line-in as bass out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define CM_EXBASEN 0x00001000 /* external bass input enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define CM_REG_MISC_CTRL 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define CM_PWD 0x80000000 /* power down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define CM_RESET 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define CM_SFIL_MASK 0x30000000 /* filter control at front end DAC, model 037? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define CM_VMGAIN 0x10000000 /* analog master amp +6dB, model 039? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define CM_TXVX 0x08000000 /* model 037? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define CM_N4SPK3D 0x04000000 /* copy front to rear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define CM_SPDIF48K 0x01000000 /* write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define CM_SPATUS48K 0x01000000 /* read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define CM_ENDBDAC 0x00800000 /* enable double dac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-OUT -> int. IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define CM_FM_EN 0x00080000 /* enable legacy FM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define CM_ENWRASID 0x00010000 /* choose writable internal SUBID (audio) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define CM_VIDWPDSB 0x00010000 /* model 037? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define CM_MASK_EN 0x00004000 /* activate channel mask on legacy DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define CM_ENWRMSID 0x00002000 /* choose writable internal SUBID (modem) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define CM_VIDWPPRT 0x00002000 /* model 037? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define CM_SFILENB 0x00001000 /* filter stepping at front end DAC, model 037? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define CM_MMODE_MASK 0x00000E00 /* model DAA interface mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define CM_ENCENTER 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define CM_FLINKON 0x00000040 /* force modem link detection on, model 037 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define CM_MUTECH1 0x00000040 /* mute PCI ch1 to DAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define CM_FLINKOFF 0x00000020 /* force modem link detection off, model 037 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define CM_MIDSMP 0x00000010 /* 1/2 interpolation at front end DAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define CM_UPDDMA_MASK 0x0000000C /* TDMA position update notification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define CM_UPDDMA_2048 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define CM_UPDDMA_1024 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define CM_UPDDMA_512 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define CM_UPDDMA_256 0x0000000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define CM_TWAIT_MASK 0x00000003 /* model 037 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define CM_TWAIT1 0x00000002 /* FM i/o cycle, 0: 48, 1: 64 PCICLKs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define CM_TWAIT0 0x00000001 /* i/o cycle, 0: 4, 1: 6 PCICLKs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define CM_REG_TDMA_POSITION 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define CM_TDMA_CNT_MASK 0xFFFF0000 /* current byte/word count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define CM_TDMA_ADR_MASK 0x0000FFFF /* current address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define CM_REG_MIXER0 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define CM_REG_SBVR 0x20 /* write: sb16 version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define CM_REG_DEV 0x20 /* read: hardware device version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define CM_REG_MIXER21 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define CM_UNKNOWN_21_MASK 0x78 /* ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define CM_X_ADPCM 0x04 /* SB16 ADPCM enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define CM_PROINV 0x02 /* SBPro left/right channel switching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define CM_X_SB16 0x01 /* SB16 compatible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define CM_REG_SB16_DATA 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define CM_REG_SB16_ADDR 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define CM_REFFREQ_XIN (315*1000*1000)/22 /* 14.31818 Mhz reference clock frequency pin XIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define CM_ADCMULT_XIN 512 /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define CM_TOLERANCE_RATE 0.001 /* Tolerance sample rate pitch (1000ppm) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define CM_MAXIMUM_RATE 80000000 /* Note more than 80MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define CM_REG_MIXER1 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define CM_FMMUTE 0x80 /* mute FM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define CM_FMMUTE_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define CM_WSMUTE 0x40 /* mute PCM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define CM_WSMUTE_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define CM_REAR2LIN 0x20 /* lin-in -> rear line out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define CM_REAR2LIN_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define CM_REAR2FRONT 0x10 /* exchange rear/front */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define CM_REAR2FRONT_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define CM_WAVEINL 0x08 /* digital wave rec. left chan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define CM_WAVEINL_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define CM_WAVEINR 0x04 /* digical wave rec. right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define CM_WAVEINR_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define CM_X3DEN 0x02 /* 3D surround enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define CM_X3DEN_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define CM_CDPLAY 0x01 /* enable SPDIF/IN PCM -> DAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define CM_CDPLAY_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define CM_REG_MIXER2 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define CM_RAUXREN 0x80 /* AUX right capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define CM_RAUXREN_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define CM_RAUXLEN 0x40 /* AUX left capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define CM_RAUXLEN_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define CM_VAUXRM 0x20 /* AUX right mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define CM_VAUXRM_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define CM_VAUXLM 0x10 /* AUX left mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define CM_VAUXLM_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define CM_VADMIC_MASK 0x0e /* mic gain level (0-3) << 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define CM_VADMIC_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define CM_MICGAINZ 0x01 /* mic boost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define CM_MICGAINZ_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define CM_REG_AUX_VOL 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define CM_VAUXL_MASK 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define CM_VAUXR_MASK 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define CM_REG_MISC 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define CM_UNKNOWN_27_MASK 0xd8 /* ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define CM_XGPO1 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) // #define CM_XGPBIO 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define CM_SPDVALID 0x02 /* spdif input valid check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define CM_DMAUTO 0x01 /* SB16 DMA auto detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * or identical with AC97 codec?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define CM_REG_EXTERN_CODEC CM_REG_AC97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define CM_REG_MPU_PCI 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define CM_REG_FM_PCI 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * access from SB-mixer port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define CM_REG_EXTENT_IND 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define CM_VPHONE_MASK 0xe0 /* Phone volume control (0-3) << 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define CM_VPHONE_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define CM_VPHOM 0x10 /* Phone mute control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define CM_VSPKM 0x08 /* Speaker mute control, default high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define CM_RLOOPREN 0x04 /* Rec. R-channel enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define CM_RLOOPLEN 0x02 /* Rec. L-channel enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define CM_VADMIC3 0x01 /* Mic record boost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * unit (readonly?).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define CM_REG_PLL 0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * extended registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define CM_REG_CH0_FRAME1 0x80 /* write: base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define CM_REG_CH0_FRAME2 0x84 /* read: current address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define CM_REG_EXT_MISC 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define CM_ADC48K44K 0x10000000 /* ADC parameters group, 0: 44k, 1: 48k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define CM_CHB3D8C 0x00200000 /* 7.1 channels support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define CM_SPD32FMT 0x00100000 /* SPDIF/IN 32k sample rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define CM_ADC2SPDIF 0x00080000 /* ADC output to SPDIF/OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define CM_SHAREADC 0x00040000 /* DAC in ADC as Center/LFE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define CM_REALTCMP 0x00020000 /* monitor the CMPL/CMPR of ADC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define CM_INVLRCK 0x00010000 /* invert ZVPORT's LRCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define CM_UNKNOWN_90_MASK 0x0000FFFF /* ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * size of i/o region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define CM_EXTENT_CODEC 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define CM_EXTENT_MIDI 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define CM_EXTENT_SYNTH 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * channels for playback / capture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define CM_CH_PLAY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define CM_CH_CAPT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * flags to check device open/close
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define CM_OPEN_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define CM_OPEN_CH_MASK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define CM_OPEN_DAC 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define CM_OPEN_ADC 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define CM_OPEN_SPDIF 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define CM_OPEN_MCHAN 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define CM_OPEN_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define CM_OPEN_PLAYBACK2 (CM_CH_CAPT | CM_OPEN_DAC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define CM_OPEN_PLAYBACK_MULTI (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define CM_OPEN_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define CM_OPEN_SPDIF_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define CM_OPEN_SPDIF_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #if CM_CH_PLAY == 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define CM_PLAYBACK_SRATE_176K CM_CH1_SRATE_176K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define CM_PLAYBACK_SPDF CM_SPDF_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define CM_CAPTURE_SPDF CM_SPDF_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define CM_PLAYBACK_SPDF CM_SPDF_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define CM_CAPTURE_SPDF CM_SPDF_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * driver data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct cmipci_pcm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) u8 running; /* dac/adc running? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) u8 fmt; /* format bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) u8 is_dac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) u8 needs_silencing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) unsigned int dma_size; /* in frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) unsigned int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) unsigned int ch; /* channel (0/1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) unsigned int offset; /* physical address of the buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* mixer elements toggled/resumed during ac3 playback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct cmipci_mixer_auto_switches {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) const char *name; /* switch to toggle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) int toggle_on; /* value to change when ac3 mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static const struct cmipci_mixer_auto_switches cm_saved_mixer[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {"PCM Playback Switch", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {"IEC958 Output Switch", 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {"IEC958 Mix Analog", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) // {"IEC958 Out To DAC", 1}, // no longer used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {"IEC958 Loop", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define CM_SAVED_MIXERS ARRAY_SIZE(cm_saved_mixer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct cmipci {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct pci_dev *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) unsigned int device; /* device ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) unsigned long iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) unsigned int ctrl; /* FUNCTRL0 current value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct snd_pcm *pcm; /* DAC/ADC PCM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct snd_pcm *pcm2; /* 2nd DAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct snd_pcm *pcm_spdif; /* SPDIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) int chip_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) int max_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) unsigned int can_ac3_sw: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) unsigned int can_ac3_hw: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) unsigned int can_multi_ch: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) unsigned int can_96k: 1; /* samplerate above 48k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) unsigned int do_soft_ac3: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) unsigned int spdif_playback_avail: 1; /* spdif ready? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) unsigned int spdif_playback_enabled: 1; /* spdif switch enabled? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) int spdif_counter; /* for software AC3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) unsigned int dig_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) unsigned int dig_pcm_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct snd_pcm_hardware *hw_info[3]; /* for playbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) int opened[2]; /* open mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct mutex open_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) unsigned int mixer_insensitive: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) struct snd_kcontrol *mixer_res_ctl[CM_SAVED_MIXERS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) int mixer_res_status[CM_SAVED_MIXERS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct cmipci_pcm channel[2]; /* ch0 - DAC, ch1 - ADC or 2nd DAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /* external MIDI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct snd_rawmidi *rmidi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #ifdef SUPPORT_JOYSTICK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct gameport *gameport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) spinlock_t reg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) unsigned int saved_regs[0x20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) unsigned char saved_mixers[0x20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* read/write operations for dword register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static inline void snd_cmipci_write(struct cmipci *cm, unsigned int cmd, unsigned int data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) outl(data, cm->iobase + cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static inline unsigned int snd_cmipci_read(struct cmipci *cm, unsigned int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return inl(cm->iobase + cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* read/write operations for word register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static inline void snd_cmipci_write_w(struct cmipci *cm, unsigned int cmd, unsigned short data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) outw(data, cm->iobase + cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static inline unsigned short snd_cmipci_read_w(struct cmipci *cm, unsigned int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return inw(cm->iobase + cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* read/write operations for byte register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static inline void snd_cmipci_write_b(struct cmipci *cm, unsigned int cmd, unsigned char data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) outb(data, cm->iobase + cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static inline unsigned char snd_cmipci_read_b(struct cmipci *cm, unsigned int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return inb(cm->iobase + cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /* bit operations for dword register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static int snd_cmipci_set_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) unsigned int val, oval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) val = oval = inl(cm->iobase + cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) val |= flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (val == oval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) outl(val, cm->iobase + cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static int snd_cmipci_clear_bit(struct cmipci *cm, unsigned int cmd, unsigned int flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) unsigned int val, oval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) val = oval = inl(cm->iobase + cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) val &= ~flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (val == oval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) outl(val, cm->iobase + cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* bit operations for byte register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static int snd_cmipci_set_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) unsigned char val, oval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) val = oval = inb(cm->iobase + cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) val |= flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (val == oval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) outb(val, cm->iobase + cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static int snd_cmipci_clear_bit_b(struct cmipci *cm, unsigned int cmd, unsigned char flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) unsigned char val, oval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) val = oval = inb(cm->iobase + cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) val &= ~flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (val == oval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) outb(val, cm->iobase + cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) * PCM interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) * calculate frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static const unsigned int rates[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static unsigned int snd_cmipci_rate_freq(unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) for (i = 0; i < ARRAY_SIZE(rates); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (rates[i] == rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) snd_BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #ifdef USE_VAR48KRATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * does it this way .. maybe not. Never get any information from C-Media about
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * that <werner@suse.de>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static int snd_cmipci_pll_rmn(unsigned int rate, unsigned int adcmult, int *r, int *m, int *n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) unsigned int delta, tolerance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) int xm, xn, xr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) for (*r = 0; rate < CM_MAXIMUM_RATE/adcmult; *r += (1<<5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) rate <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) *n = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (*r > 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) tolerance = rate*CM_TOLERANCE_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) for (xn = (1+2); xn < (0x1f+2); xn++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) for (xm = (1+2); xm < (0xff+2); xm++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) xr = ((CM_REFFREQ_XIN/adcmult) * xm) / xn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (xr < rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) delta = rate - xr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) delta = xr - rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * If we found one, remember this,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * and try to find a closer one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (delta < tolerance) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) tolerance = delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) *m = xm - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) *n = xn - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return (*n > -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * Program pll register bits, I assume that the 8 registers 0xf8 up to 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * are mapped onto the 8 ADC/DAC sampling frequency which can be chosen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * at the register CM_REG_FUNCTRL1 (0x04).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * Problem: other ways are also possible (any information about that?)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static void snd_cmipci_set_pll(struct cmipci *cm, unsigned int rate, unsigned int slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) unsigned int reg = CM_REG_PLL + slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * Guess that this programs at reg. 0x04 the pos 15:13/12:10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * for DSFC/ASFC (000 up to 111).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /* FIXME: Init (Do we've to set an other register first before programming?) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) snd_cmipci_write_b(cm, reg, rate>>8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) snd_cmipci_write_b(cm, reg, rate&0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /* FIXME: Setup (Do we've to set an other register first to enable this?) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #endif /* USE_VAR48KRATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static int snd_cmipci_playback2_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) struct snd_pcm_hw_params *hw_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) struct cmipci *cm = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (params_channels(hw_params) > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) mutex_lock(&cm->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (cm->opened[CM_CH_PLAY]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) mutex_unlock(&cm->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* reserve the channel A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) cm->opened[CM_CH_PLAY] = CM_OPEN_PLAYBACK_MULTI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) mutex_unlock(&cm->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) static void snd_cmipci_ch_reset(struct cmipci *cm, int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) int reset = CM_RST_CH0 << (cm->channel[ch].ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static const unsigned int hw_channels[] = {1, 2, 4, 6, 8};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static const struct snd_pcm_hw_constraint_list hw_constraints_channels_4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .count = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .list = hw_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static const struct snd_pcm_hw_constraint_list hw_constraints_channels_6 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .count = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .list = hw_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static const struct snd_pcm_hw_constraint_list hw_constraints_channels_8 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .count = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .list = hw_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static int set_dac_channels(struct cmipci *cm, struct cmipci_pcm *rec, int channels)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (channels > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (!cm->can_multi_ch || !rec->ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (rec->fmt != 0x03) /* stereo 16bit only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (cm->can_multi_ch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) spin_lock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (channels > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_NXCHG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (channels == 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_CHB3D8C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (channels == 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D5C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CHB3D6C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (channels == 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_CHB3D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) spin_unlock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) * prepare playback/capture channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) * channel to be used must have been set in rec->ch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static int snd_cmipci_pcm_prepare(struct cmipci *cm, struct cmipci_pcm *rec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) unsigned int reg, freq, freq_ext, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) unsigned int period_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) rec->fmt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) rec->shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (snd_pcm_format_width(runtime->format) >= 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) rec->fmt |= 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (snd_pcm_format_width(runtime->format) > 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) rec->shift++; /* 24/32bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (runtime->channels > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) rec->fmt |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (rec->is_dac && set_dac_channels(cm, rec, runtime->channels) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) dev_dbg(cm->card->dev, "cannot set dac channels\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) rec->offset = runtime->dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /* buffer and period sizes in frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) rec->dma_size = runtime->buffer_size << rec->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) period_size = runtime->period_size << rec->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (runtime->channels > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) /* multi-channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) rec->dma_size = (rec->dma_size * runtime->channels) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) period_size = (period_size * runtime->channels) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) spin_lock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) /* set buffer address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) snd_cmipci_write(cm, reg, rec->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /* program sample counts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) snd_cmipci_write_w(cm, reg, rec->dma_size - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) snd_cmipci_write_w(cm, reg + 2, period_size - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) /* set adc/dac flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) val = rec->ch ? CM_CHADC1 : CM_CHADC0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (rec->is_dac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) cm->ctrl &= ~val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) cm->ctrl |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /* dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) /* set sample rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) freq_ext = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (runtime->rate > 48000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) switch (runtime->rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) case 88200: freq_ext = CM_CH0_SRATE_88K; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) case 96000: freq_ext = CM_CH0_SRATE_96K; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) case 128000: freq_ext = CM_CH0_SRATE_128K; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) default: snd_BUG(); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) freq = snd_cmipci_rate_freq(runtime->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (rec->ch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) val &= ~CM_DSFC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) val |= (freq << CM_DSFC_SHIFT) & CM_DSFC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) val &= ~CM_ASFC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) val |= (freq << CM_ASFC_SHIFT) & CM_ASFC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) dev_dbg(cm->card->dev, "functrl1 = %08x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) /* set format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if (rec->ch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) val &= ~CM_CH1FMT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) val |= rec->fmt << CM_CH1FMT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) val &= ~CM_CH0FMT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) val |= rec->fmt << CM_CH0FMT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (cm->can_96k) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) val |= freq_ext << (rec->ch * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) dev_dbg(cm->card->dev, "chformat = %08x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (!rec->is_dac && cm->chip_version) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (runtime->rate > 44100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) snd_cmipci_set_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) snd_cmipci_clear_bit(cm, CM_REG_EXT_MISC, CM_ADC48K44K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) rec->running = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) spin_unlock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) * PCM trigger/stop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static int snd_cmipci_pcm_trigger(struct cmipci *cm, struct cmipci_pcm *rec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) unsigned int inthld, chen, reset, pause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) int result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) inthld = CM_CH0_INT_EN << rec->ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) chen = CM_CHEN0 << rec->ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) reset = CM_RST_CH0 << rec->ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) pause = CM_PAUSE0 << rec->ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) spin_lock(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) rec->running = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) /* set interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, inthld);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) cm->ctrl |= chen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /* enable channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) dev_dbg(cm->card->dev, "functrl0 = %08x\n", cm->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) rec->running = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) /* disable interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, inthld);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) /* reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) cm->ctrl &= ~chen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) rec->needs_silencing = rec->is_dac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) cm->ctrl |= pause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) cm->ctrl &= ~pause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) result = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) spin_unlock(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) * return the current pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static snd_pcm_uframes_t snd_cmipci_pcm_pointer(struct cmipci *cm, struct cmipci_pcm *rec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) size_t ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) unsigned int reg, rem, tries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (!rec->running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #if 1 // this seems better..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) for (tries = 0; tries < 3; tries++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) rem = snd_cmipci_read_w(cm, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (rem < rec->dma_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) goto ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) dev_err(cm->card->dev, "invalid PCM pointer: %#x\n", rem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) return SNDRV_PCM_POS_XRUN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) ok:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) ptr = (rec->dma_size - (rem + 1)) >> rec->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) reg = rec->ch ? CM_REG_CH1_FRAME1 : CM_REG_CH0_FRAME1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) ptr = snd_cmipci_read(cm, reg) - rec->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) ptr = bytes_to_frames(substream->runtime, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (substream->runtime->channels > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) ptr = (ptr * 2) / substream->runtime->channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) return ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) * playback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) static int snd_cmipci_playback_trigger(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) struct cmipci *cm = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_PLAY], cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) static snd_pcm_uframes_t snd_cmipci_playback_pointer(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) struct cmipci *cm = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_PLAY], substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) * capture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) static int snd_cmipci_capture_trigger(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) struct cmipci *cm = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) return snd_cmipci_pcm_trigger(cm, &cm->channel[CM_CH_CAPT], cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) static snd_pcm_uframes_t snd_cmipci_capture_pointer(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) struct cmipci *cm = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) return snd_cmipci_pcm_pointer(cm, &cm->channel[CM_CH_CAPT], substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) * hw preparation for spdif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) static int snd_cmipci_spdif_default_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) static int snd_cmipci_spdif_default_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) struct cmipci *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) for (i = 0; i < 4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) ucontrol->value.iec958.status[i] = (chip->dig_status >> (i * 8)) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) static int snd_cmipci_spdif_default_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) struct cmipci *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) int i, change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) for (i = 0; i < 4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) change = val != chip->dig_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) chip->dig_status = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) static const struct snd_kcontrol_new snd_cmipci_spdif_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .info = snd_cmipci_spdif_default_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .get = snd_cmipci_spdif_default_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) .put = snd_cmipci_spdif_default_put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) static int snd_cmipci_spdif_mask_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) static int snd_cmipci_spdif_mask_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) ucontrol->value.iec958.status[0] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) ucontrol->value.iec958.status[1] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) ucontrol->value.iec958.status[2] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) ucontrol->value.iec958.status[3] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) static const struct snd_kcontrol_new snd_cmipci_spdif_mask =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .access = SNDRV_CTL_ELEM_ACCESS_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .info = snd_cmipci_spdif_mask_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .get = snd_cmipci_spdif_mask_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) static int snd_cmipci_spdif_stream_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) static int snd_cmipci_spdif_stream_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) struct cmipci *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) for (i = 0; i < 4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) ucontrol->value.iec958.status[i] = (chip->dig_pcm_status >> (i * 8)) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) static int snd_cmipci_spdif_stream_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) struct cmipci *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) int i, change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) for (i = 0; i < 4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) change = val != chip->dig_pcm_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) chip->dig_pcm_status = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) static const struct snd_kcontrol_new snd_cmipci_spdif_stream =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .info = snd_cmipci_spdif_stream_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .get = snd_cmipci_spdif_stream_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .put = snd_cmipci_spdif_stream_put
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) /* save mixer setting and mute for AC3 playback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) static int save_mixer_state(struct cmipci *cm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) if (! cm->mixer_insensitive) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) struct snd_ctl_elem_value *val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) val = kmalloc(sizeof(*val), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) if (!val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) for (i = 0; i < CM_SAVED_MIXERS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) if (ctl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) int event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) memset(val, 0, sizeof(*val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) ctl->get(ctl, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) cm->mixer_res_status[i] = val->value.integer.value[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) val->value.integer.value[0] = cm_saved_mixer[i].toggle_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) event = SNDRV_CTL_EVENT_MASK_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) if (cm->mixer_res_status[i] != val->value.integer.value[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) ctl->put(ctl, val); /* toggle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) event |= SNDRV_CTL_EVENT_MASK_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) snd_ctl_notify(cm->card, event, &ctl->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) kfree(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) cm->mixer_insensitive = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) /* restore the previously saved mixer status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) static void restore_mixer_state(struct cmipci *cm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) if (cm->mixer_insensitive) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) struct snd_ctl_elem_value *val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) val = kmalloc(sizeof(*val), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) if (!val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) cm->mixer_insensitive = 0; /* at first clear this;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) otherwise the changes will be ignored */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) for (i = 0; i < CM_SAVED_MIXERS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) struct snd_kcontrol *ctl = cm->mixer_res_ctl[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) if (ctl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) int event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) memset(val, 0, sizeof(*val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) ctl->get(ctl, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) event = SNDRV_CTL_EVENT_MASK_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) if (val->value.integer.value[0] != cm->mixer_res_status[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) val->value.integer.value[0] = cm->mixer_res_status[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) ctl->put(ctl, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) event |= SNDRV_CTL_EVENT_MASK_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) snd_ctl_notify(cm->card, event, &ctl->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) kfree(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) /* spinlock held! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) static void setup_ac3(struct cmipci *cm, struct snd_pcm_substream *subs, int do_ac3, int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) if (do_ac3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) /* AC3EN for 037 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) /* AC3EN for 039 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (cm->can_ac3_hw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) /* SPD24SEL for 037, 0x02 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) /* SPD24SEL for 039, 0x20, but cannot be set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) } else { /* can_ac3_sw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) /* SPD32SEL for 037 & 039, 0x20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) /* set 176K sample rate to fix 033 HW bug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if (cm->chip_version == 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) if (rate >= 48000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_AC3EN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_AC3EN2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) if (cm->can_ac3_hw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) /* chip model >= 37 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) if (snd_pcm_format_width(subs->runtime->format) > 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_SPD24SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_PLAYBACK_SRATE_176K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) static int setup_spdif_playback(struct cmipci *cm, struct snd_pcm_substream *subs, int up, int do_ac3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) int rate, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) rate = subs->runtime->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) if (up && do_ac3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if ((err = save_mixer_state(cm)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) spin_lock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) cm->spdif_playback_avail = up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) if (up) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) /* they are controlled via "IEC958 Output Switch" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) if (cm->spdif_playback_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) setup_ac3(cm, subs, do_ac3, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) if (rate == 48000 || rate == 96000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K | CM_SPDF_AC97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) if (rate > 48000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) /* they are controlled via "IEC958 Output Switch" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) setup_ac3(cm, subs, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) spin_unlock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) * preparation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) /* playback - enable spdif only on the certain condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) static int snd_cmipci_playback_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) struct cmipci *cm = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) int rate = substream->runtime->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) int err, do_spdif, do_ac3 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) do_spdif = (rate >= 44100 && rate <= 96000 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) substream->runtime->channels == 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) if (do_spdif && cm->can_ac3_hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) if ((err = setup_spdif_playback(cm, substream, do_spdif, do_ac3)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) /* playback (via device #2) - enable spdif always */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) static int snd_cmipci_playback_spdif_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) struct cmipci *cm = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) int err, do_ac3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) if (cm->can_ac3_hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) do_ac3 = cm->dig_pcm_status & IEC958_AES0_NONAUDIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) do_ac3 = 1; /* doesn't matter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) if ((err = setup_spdif_playback(cm, substream, 1, do_ac3)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_PLAY], substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) * Apparently, the samples last played on channel A stay in some buffer, even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) * after the channel is reset, and get added to the data for the rear DACs when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) * playing a multichannel stream on channel B. This is likely to generate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) * wraparounds and thus distortions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) * To avoid this, we play at least one zero sample after the actual stream has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) * stopped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) static void snd_cmipci_silence_hack(struct cmipci *cm, struct cmipci_pcm *rec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) struct snd_pcm_runtime *runtime = rec->substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) unsigned int reg, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) if (rec->needs_silencing && runtime && runtime->dma_area) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) /* set up a small silence buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) memset(runtime->dma_area, 0, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) reg = rec->ch ? CM_REG_CH1_FRAME2 : CM_REG_CH0_FRAME2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) val = ((PAGE_SIZE / 4) - 1) | (((PAGE_SIZE / 4) / 2 - 1) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) snd_cmipci_write(cm, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) /* configure for 16 bits, 2 channels, 8 kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) if (runtime->channels > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) set_dac_channels(cm, rec, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) spin_lock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) val &= ~(CM_ASFC_MASK << (rec->ch * 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) val |= (4 << CM_ASFC_SHIFT) << (rec->ch * 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) val = snd_cmipci_read(cm, CM_REG_CHFORMAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) val &= ~(CM_CH0FMT_MASK << (rec->ch * 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) val |= (3 << CM_CH0FMT_SHIFT) << (rec->ch * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) if (cm->can_96k)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) val &= ~(CM_CH0_SRATE_MASK << (rec->ch * 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) snd_cmipci_write(cm, CM_REG_CHFORMAT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) /* start stream (we don't need interrupts) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) cm->ctrl |= CM_CHEN0 << rec->ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) spin_unlock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) /* stop and reset stream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) spin_lock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) cm->ctrl &= ~(CM_CHEN0 << rec->ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) val = CM_RST_CH0 << rec->ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) spin_unlock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) rec->needs_silencing = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) static int snd_cmipci_playback_hw_free(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) struct cmipci *cm = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) setup_spdif_playback(cm, substream, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) restore_mixer_state(cm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) snd_cmipci_silence_hack(cm, &cm->channel[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) static int snd_cmipci_playback2_hw_free(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) struct cmipci *cm = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) snd_cmipci_silence_hack(cm, &cm->channel[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) /* capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) static int snd_cmipci_capture_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) struct cmipci *cm = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) /* capture with spdif (via device #2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) static int snd_cmipci_capture_spdif_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) struct cmipci *cm = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) spin_lock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) if (cm->can_96k) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) if (substream->runtime->rate > 48000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) snd_cmipci_set_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) snd_cmipci_clear_bit(cm, CM_REG_CHFORMAT, CM_DBLSPDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) if (snd_pcm_format_width(substream->runtime->format) > 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) spin_unlock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) return snd_cmipci_pcm_prepare(cm, &cm->channel[CM_CH_CAPT], substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) static int snd_cmipci_capture_spdif_hw_free(struct snd_pcm_substream *subs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) struct cmipci *cm = snd_pcm_substream_chip(subs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) spin_lock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_SPD32SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) spin_unlock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) * interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) static irqreturn_t snd_cmipci_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) struct cmipci *cm = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) unsigned int status, mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) /* fastpath out, to ease interrupt sharing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) status = snd_cmipci_read(cm, CM_REG_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) if (!(status & CM_INTR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) /* acknowledge interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) spin_lock(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) if (status & CM_CHINT0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) mask |= CM_CH0_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) if (status & CM_CHINT1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) mask |= CM_CH1_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) snd_cmipci_clear_bit(cm, CM_REG_INT_HLDCLR, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) snd_cmipci_set_bit(cm, CM_REG_INT_HLDCLR, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) spin_unlock(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) if (cm->rmidi && (status & CM_UARTINT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) snd_mpu401_uart_interrupt(irq, cm->rmidi->private_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) if (cm->pcm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) if ((status & CM_CHINT0) && cm->channel[0].running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) snd_pcm_period_elapsed(cm->channel[0].substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) if ((status & CM_CHINT1) && cm->channel[1].running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) snd_pcm_period_elapsed(cm->channel[1].substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) * h/w infos
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) /* playback on channel A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) static const struct snd_pcm_hardware snd_cmipci_playback =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) .rate_min = 5512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) .buffer_bytes_max = (128*1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) .period_bytes_min = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) .period_bytes_max = (128*1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) .periods_max = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) .fifo_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) /* capture on channel B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) static const struct snd_pcm_hardware snd_cmipci_capture =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) .rate_min = 5512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) .buffer_bytes_max = (128*1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) .period_bytes_min = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) .period_bytes_max = (128*1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) .periods_max = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) .fifo_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) /* playback on channel B - stereo 16bit only? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) static const struct snd_pcm_hardware snd_cmipci_playback2 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) .formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) .rates = SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) .rate_min = 5512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) .buffer_bytes_max = (128*1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) .period_bytes_min = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) .period_bytes_max = (128*1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) .periods_max = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) .fifo_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) /* spdif playback on channel A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) static const struct snd_pcm_hardware snd_cmipci_playback_spdif =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) .formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) .rate_min = 44100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) .buffer_bytes_max = (128*1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) .period_bytes_min = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) .period_bytes_max = (128*1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) .periods_max = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) .fifo_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) /* spdif playback on channel A (32bit, IEC958 subframes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) static const struct snd_pcm_hardware snd_cmipci_playback_iec958_subframe =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) .rate_min = 44100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) .buffer_bytes_max = (128*1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .period_bytes_min = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) .period_bytes_max = (128*1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) .periods_max = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) .fifo_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) /* spdif capture on channel B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) static const struct snd_pcm_hardware snd_cmipci_capture_spdif =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_PAUSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) SNDRV_PCM_INFO_RESUME | SNDRV_PCM_INFO_MMAP_VALID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) .formats = SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) .rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) .rate_min = 44100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) .buffer_bytes_max = (128*1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) .period_bytes_min = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) .period_bytes_max = (128*1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) .periods_max = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) .fifo_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) static const unsigned int rate_constraints[] = { 5512, 8000, 11025, 16000, 22050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) 32000, 44100, 48000, 88200, 96000, 128000 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) static const struct snd_pcm_hw_constraint_list hw_constraints_rates = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) .count = ARRAY_SIZE(rate_constraints),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) .list = rate_constraints,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) .mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) * check device open/close
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) static int open_device_check(struct cmipci *cm, int mode, struct snd_pcm_substream *subs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) int ch = mode & CM_OPEN_CH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) /* FIXME: a file should wait until the device becomes free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) * when it's opened on blocking mode. however, since the current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) * pcm framework doesn't pass file pointer before actually opened,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) * we can't know whether blocking mode or not in open callback..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) mutex_lock(&cm->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) if (cm->opened[ch]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) mutex_unlock(&cm->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) cm->opened[ch] = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) cm->channel[ch].substream = subs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) if (! (mode & CM_OPEN_DAC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) /* disable dual DAC mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) cm->channel[ch].is_dac = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) spin_lock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) spin_unlock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) mutex_unlock(&cm->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) static void close_device_check(struct cmipci *cm, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) int ch = mode & CM_OPEN_CH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) mutex_lock(&cm->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) if (cm->opened[ch] == mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) if (cm->channel[ch].substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) snd_cmipci_ch_reset(cm, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) cm->channel[ch].running = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) cm->channel[ch].substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) cm->opened[ch] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) if (! cm->channel[ch].is_dac) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) /* enable dual DAC mode again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) cm->channel[ch].is_dac = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) spin_lock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) spin_unlock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) mutex_unlock(&cm->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) static int snd_cmipci_playback_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) struct cmipci *cm = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) if ((err = open_device_check(cm, CM_OPEN_PLAYBACK, substream)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) runtime->hw = snd_cmipci_playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) if (cm->chip_version == 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) SNDRV_PCM_RATE_96000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) runtime->hw.rate_max = 96000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) } else if (cm->chip_version == 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) err = snd_pcm_hw_constraint_list(runtime, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) runtime->hw.rate_max = 128000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) cm->dig_pcm_status = cm->dig_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) static int snd_cmipci_capture_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) struct cmipci *cm = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) if ((err = open_device_check(cm, CM_OPEN_CAPTURE, substream)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) runtime->hw = snd_cmipci_capture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) if (cm->chip_version == 68) { // 8768 only supports 44k/48k recording
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) runtime->hw.rate_min = 41000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) runtime->hw.rates = SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) } else if (cm->chip_version == 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) err = snd_pcm_hw_constraint_list(runtime, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) runtime->hw.rate_max = 128000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) static int snd_cmipci_playback2_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) struct cmipci *cm = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) if ((err = open_device_check(cm, CM_OPEN_PLAYBACK2, substream)) < 0) /* use channel B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) runtime->hw = snd_cmipci_playback2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) mutex_lock(&cm->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) if (! cm->opened[CM_CH_PLAY]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) if (cm->can_multi_ch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) runtime->hw.channels_max = cm->max_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) if (cm->max_channels == 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) else if (cm->max_channels == 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) else if (cm->max_channels == 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels_8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) mutex_unlock(&cm->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) if (cm->chip_version == 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) SNDRV_PCM_RATE_96000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) runtime->hw.rate_max = 96000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) } else if (cm->chip_version == 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) err = snd_pcm_hw_constraint_list(runtime, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) runtime->hw.rate_max = 128000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) static int snd_cmipci_playback_spdif_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) struct cmipci *cm = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) if ((err = open_device_check(cm, CM_OPEN_SPDIF_PLAYBACK, substream)) < 0) /* use channel A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) if (cm->can_ac3_hw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) runtime->hw = snd_cmipci_playback_spdif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) if (cm->chip_version >= 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) if (cm->can_96k) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) SNDRV_PCM_RATE_96000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) runtime->hw.rate_max = 96000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) runtime->hw = snd_cmipci_playback_iec958_subframe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) cm->dig_pcm_status = cm->dig_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) static int snd_cmipci_capture_spdif_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) struct cmipci *cm = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) if ((err = open_device_check(cm, CM_OPEN_SPDIF_CAPTURE, substream)) < 0) /* use channel B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) runtime->hw = snd_cmipci_capture_spdif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) if (cm->can_96k && !(cm->chip_version == 68)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) runtime->hw.rates |= SNDRV_PCM_RATE_88200 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) SNDRV_PCM_RATE_96000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) runtime->hw.rate_max = 96000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 0, 0x40000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) static int snd_cmipci_playback_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) struct cmipci *cm = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) close_device_check(cm, CM_OPEN_PLAYBACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) static int snd_cmipci_capture_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) struct cmipci *cm = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) close_device_check(cm, CM_OPEN_CAPTURE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) static int snd_cmipci_playback2_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) struct cmipci *cm = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) close_device_check(cm, CM_OPEN_PLAYBACK2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) close_device_check(cm, CM_OPEN_PLAYBACK_MULTI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) static int snd_cmipci_playback_spdif_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) struct cmipci *cm = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) close_device_check(cm, CM_OPEN_SPDIF_PLAYBACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) static int snd_cmipci_capture_spdif_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) struct cmipci *cm = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) close_device_check(cm, CM_OPEN_SPDIF_CAPTURE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) static const struct snd_pcm_ops snd_cmipci_playback_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) .open = snd_cmipci_playback_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) .close = snd_cmipci_playback_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) .hw_free = snd_cmipci_playback_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) .prepare = snd_cmipci_playback_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) .trigger = snd_cmipci_playback_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) .pointer = snd_cmipci_playback_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) static const struct snd_pcm_ops snd_cmipci_capture_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) .open = snd_cmipci_capture_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) .close = snd_cmipci_capture_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) .prepare = snd_cmipci_capture_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) .trigger = snd_cmipci_capture_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) .pointer = snd_cmipci_capture_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) static const struct snd_pcm_ops snd_cmipci_playback2_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) .open = snd_cmipci_playback2_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) .close = snd_cmipci_playback2_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) .hw_params = snd_cmipci_playback2_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) .hw_free = snd_cmipci_playback2_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) .prepare = snd_cmipci_capture_prepare, /* channel B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) .trigger = snd_cmipci_capture_trigger, /* channel B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) .pointer = snd_cmipci_capture_pointer, /* channel B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) static const struct snd_pcm_ops snd_cmipci_playback_spdif_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) .open = snd_cmipci_playback_spdif_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) .close = snd_cmipci_playback_spdif_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) .hw_free = snd_cmipci_playback_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) .prepare = snd_cmipci_playback_spdif_prepare, /* set up rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) .trigger = snd_cmipci_playback_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) .pointer = snd_cmipci_playback_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) static const struct snd_pcm_ops snd_cmipci_capture_spdif_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) .open = snd_cmipci_capture_spdif_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) .close = snd_cmipci_capture_spdif_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) .hw_free = snd_cmipci_capture_spdif_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) .prepare = snd_cmipci_capture_spdif_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) .trigger = snd_cmipci_capture_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) .pointer = snd_cmipci_capture_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) static int snd_cmipci_pcm_new(struct cmipci *cm, int device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) pcm->private_data = cm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) pcm->info_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) strcpy(pcm->name, "C-Media PCI DAC/ADC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) cm->pcm = pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) &cm->pci->dev, 64*1024, 128*1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) static int snd_cmipci_pcm2_new(struct cmipci *cm, int device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 0, &pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback2_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) pcm->private_data = cm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) pcm->info_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) strcpy(pcm->name, "C-Media PCI 2nd DAC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) cm->pcm2 = pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) &cm->pci->dev, 64*1024, 128*1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) static int snd_cmipci_pcm_spdif_new(struct cmipci *cm, int device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) err = snd_pcm_new(cm->card, cm->card->driver, device, 1, 1, &pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cmipci_playback_spdif_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cmipci_capture_spdif_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) pcm->private_data = cm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) pcm->info_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) strcpy(pcm->name, "C-Media PCI IEC958");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) cm->pcm_spdif = pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) &cm->pci->dev, 64*1024, 128*1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) snd_pcm_alt_chmaps, cm->max_channels, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) * mixer interface:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) * - CM8338/8738 has a compatible mixer interface with SB16, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) * lack of some elements like tone control, i/o gain and AGC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) * - Access to native registers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) * - A 3D switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) * - Output mute switches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) static void snd_cmipci_mixer_write(struct cmipci *s, unsigned char idx, unsigned char data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) outb(idx, s->iobase + CM_REG_SB16_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) outb(data, s->iobase + CM_REG_SB16_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) static unsigned char snd_cmipci_mixer_read(struct cmipci *s, unsigned char idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) unsigned char v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) outb(idx, s->iobase + CM_REG_SB16_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) v = inb(s->iobase + CM_REG_SB16_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) return v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) * general mixer element
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) struct cmipci_sb_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) unsigned int left_reg, right_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) unsigned int left_shift, right_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) unsigned int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) unsigned int invert: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) unsigned int stereo: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) #define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) #define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) .info = snd_cmipci_info_volume, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) #define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) #define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) #define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) #define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) static void cmipci_sb_reg_decode(struct cmipci_sb_reg *r, unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) r->left_reg = val & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) r->right_reg = (val >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) r->left_shift = (val >> 16) & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) r->right_shift = (val >> 19) & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) r->invert = (val >> 22) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) r->stereo = (val >> 23) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) r->mask = (val >> 24) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) static int snd_cmipci_info_volume(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) struct cmipci_sb_reg reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) cmipci_sb_reg_decode(®, kcontrol->private_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) uinfo->count = reg.stereo + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) uinfo->value.integer.max = reg.mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) static int snd_cmipci_get_volume(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) struct cmipci *cm = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) struct cmipci_sb_reg reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) cmipci_sb_reg_decode(®, kcontrol->private_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) spin_lock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) val = (snd_cmipci_mixer_read(cm, reg.left_reg) >> reg.left_shift) & reg.mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) if (reg.invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) val = reg.mask - val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) ucontrol->value.integer.value[0] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) if (reg.stereo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) val = (snd_cmipci_mixer_read(cm, reg.right_reg) >> reg.right_shift) & reg.mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) if (reg.invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) val = reg.mask - val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) ucontrol->value.integer.value[1] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) spin_unlock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) static int snd_cmipci_put_volume(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) struct cmipci *cm = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) struct cmipci_sb_reg reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) int left, right, oleft, oright;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) cmipci_sb_reg_decode(®, kcontrol->private_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) left = ucontrol->value.integer.value[0] & reg.mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) if (reg.invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) left = reg.mask - left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) left <<= reg.left_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) if (reg.stereo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) right = ucontrol->value.integer.value[1] & reg.mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) if (reg.invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) right = reg.mask - right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) right <<= reg.right_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) right = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) spin_lock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) oleft = snd_cmipci_mixer_read(cm, reg.left_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) left |= oleft & ~(reg.mask << reg.left_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) change = left != oleft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) if (reg.stereo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) if (reg.left_reg != reg.right_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) snd_cmipci_mixer_write(cm, reg.left_reg, left);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) oright = snd_cmipci_mixer_read(cm, reg.right_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) oright = left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) right |= oright & ~(reg.mask << reg.right_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) change |= right != oright;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) snd_cmipci_mixer_write(cm, reg.right_reg, right);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) snd_cmipci_mixer_write(cm, reg.left_reg, left);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) spin_unlock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) * input route (left,right) -> (left,right)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) #define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) .info = snd_cmipci_info_input_sw, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) static int snd_cmipci_info_input_sw(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) uinfo->count = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) uinfo->value.integer.max = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) static int snd_cmipci_get_input_sw(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) struct cmipci *cm = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) struct cmipci_sb_reg reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) int val1, val2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) cmipci_sb_reg_decode(®, kcontrol->private_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) spin_lock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) val1 = snd_cmipci_mixer_read(cm, reg.left_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) val2 = snd_cmipci_mixer_read(cm, reg.right_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) spin_unlock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) ucontrol->value.integer.value[0] = (val1 >> reg.left_shift) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) ucontrol->value.integer.value[1] = (val2 >> reg.left_shift) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) ucontrol->value.integer.value[2] = (val1 >> reg.right_shift) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) ucontrol->value.integer.value[3] = (val2 >> reg.right_shift) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) static int snd_cmipci_put_input_sw(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) struct cmipci *cm = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) struct cmipci_sb_reg reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) int val1, val2, oval1, oval2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) cmipci_sb_reg_decode(®, kcontrol->private_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) spin_lock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) oval1 = snd_cmipci_mixer_read(cm, reg.left_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) oval2 = snd_cmipci_mixer_read(cm, reg.right_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) val1 = oval1 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) val2 = oval2 & ~((1 << reg.left_shift) | (1 << reg.right_shift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) val1 |= (ucontrol->value.integer.value[0] & 1) << reg.left_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) val2 |= (ucontrol->value.integer.value[1] & 1) << reg.left_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) val1 |= (ucontrol->value.integer.value[2] & 1) << reg.right_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) val2 |= (ucontrol->value.integer.value[3] & 1) << reg.right_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) change = val1 != oval1 || val2 != oval2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) snd_cmipci_mixer_write(cm, reg.left_reg, val1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) snd_cmipci_mixer_write(cm, reg.right_reg, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) spin_unlock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) * native mixer switches/volumes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) #define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) .info = snd_cmipci_info_native_mixer, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) #define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) .info = snd_cmipci_info_native_mixer, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) #define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) .info = snd_cmipci_info_native_mixer, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) #define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) .info = snd_cmipci_info_native_mixer, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) static int snd_cmipci_info_native_mixer(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) struct cmipci_sb_reg reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) cmipci_sb_reg_decode(®, kcontrol->private_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) uinfo->type = reg.mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) uinfo->count = reg.stereo + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) uinfo->value.integer.max = reg.mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) static int snd_cmipci_get_native_mixer(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) struct cmipci *cm = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) struct cmipci_sb_reg reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) unsigned char oreg, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) cmipci_sb_reg_decode(®, kcontrol->private_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) spin_lock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) oreg = inb(cm->iobase + reg.left_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) val = (oreg >> reg.left_shift) & reg.mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) if (reg.invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) val = reg.mask - val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) ucontrol->value.integer.value[0] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) if (reg.stereo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) val = (oreg >> reg.right_shift) & reg.mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) if (reg.invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) val = reg.mask - val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) ucontrol->value.integer.value[1] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) spin_unlock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) static int snd_cmipci_put_native_mixer(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) struct cmipci *cm = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) struct cmipci_sb_reg reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) unsigned char oreg, nreg, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) cmipci_sb_reg_decode(®, kcontrol->private_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) spin_lock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) oreg = inb(cm->iobase + reg.left_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) val = ucontrol->value.integer.value[0] & reg.mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) if (reg.invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) val = reg.mask - val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) nreg = oreg & ~(reg.mask << reg.left_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) nreg |= (val << reg.left_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) if (reg.stereo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) val = ucontrol->value.integer.value[1] & reg.mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) if (reg.invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) val = reg.mask - val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) nreg &= ~(reg.mask << reg.right_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) nreg |= (val << reg.right_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) outb(nreg, cm->iobase + reg.left_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) spin_unlock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) return (nreg != oreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) * special case - check mixer sensitivity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) static int snd_cmipci_get_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) //struct cmipci *cm = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) return snd_cmipci_get_native_mixer(kcontrol, ucontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) static int snd_cmipci_put_native_mixer_sensitive(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) struct cmipci *cm = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) if (cm->mixer_insensitive) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) /* ignored */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) return snd_cmipci_put_native_mixer(kcontrol, ucontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) static const struct snd_kcontrol_new snd_cmipci_mixers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV, 3, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1, CM_X3DEN_SHIFT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV, 3, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) { /* switch with sensitivity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) .name = "PCM Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) .info = snd_cmipci_info_native_mixer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) .get = snd_cmipci_get_native_mixer_sensitive,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) .put = snd_cmipci_put_native_mixer_sensitive,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) .private_value = COMPOSE_SB_REG(CM_REG_MIXER1, CM_REG_MIXER1, CM_WSMUTE_SHIFT, CM_WSMUTE_SHIFT, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1, CM_WAVEINL_SHIFT, CM_WAVEINR_SHIFT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV, 3, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1, CM_FMMUTE_SHIFT, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV, 3, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV, 3, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV, 3, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) CMIPCI_SB_SW_MONO("Mic Playback Switch", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, 0, 0, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) CMIPCI_SB_VOL_MONO("Beep Playback Volume", SB_DSP4_SPEAKER_DEV, 6, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL, 4, 0, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2, CM_VAUXLM_SHIFT, CM_VAUXRM_SHIFT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2, CM_RAUXLEN_SHIFT, CM_RAUXREN_SHIFT, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2, CM_MICGAINZ_SHIFT, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2, CM_VADMIC_SHIFT, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND, 5, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 4, 4, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) CMIPCI_DOUBLE("Beep Playback Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 3, 3, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND, CM_REG_EXTENT_IND, 0, 0, 1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) * other switches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) struct cmipci_switch_args {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) int reg; /* register index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) unsigned int mask; /* mask bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) unsigned int mask_on; /* mask bits to turn on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) unsigned int is_byte: 1; /* byte access? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) unsigned int ac3_sensitive: 1; /* access forbidden during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) * non-audio operation?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) #define snd_cmipci_uswitch_info snd_ctl_boolean_mono_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) static int _snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) struct snd_ctl_elem_value *ucontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) struct cmipci_switch_args *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) struct cmipci *cm = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) spin_lock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) if (args->ac3_sensitive && cm->mixer_insensitive) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) ucontrol->value.integer.value[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) spin_unlock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) if (args->is_byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) val = inb(cm->iobase + args->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) val = snd_cmipci_read(cm, args->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) ucontrol->value.integer.value[0] = ((val & args->mask) == args->mask_on) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) spin_unlock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) static int snd_cmipci_uswitch_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) struct cmipci_switch_args *args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) args = (struct cmipci_switch_args *)kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) if (snd_BUG_ON(!args))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) return _snd_cmipci_uswitch_get(kcontrol, ucontrol, args);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) static int _snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) struct snd_ctl_elem_value *ucontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) struct cmipci_switch_args *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) struct cmipci *cm = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) spin_lock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) if (args->ac3_sensitive && cm->mixer_insensitive) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) /* ignored */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) spin_unlock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) if (args->is_byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) val = inb(cm->iobase + args->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) val = snd_cmipci_read(cm, args->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) change = (val & args->mask) != (ucontrol->value.integer.value[0] ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) args->mask_on : (args->mask & ~args->mask_on));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) if (change) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) val &= ~args->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) if (ucontrol->value.integer.value[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) val |= args->mask_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) val |= (args->mask & ~args->mask_on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) if (args->is_byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) outb((unsigned char)val, cm->iobase + args->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) snd_cmipci_write(cm, args->reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) spin_unlock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) static int snd_cmipci_uswitch_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) struct cmipci_switch_args *args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) args = (struct cmipci_switch_args *)kcontrol->private_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) if (snd_BUG_ON(!args))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) return _snd_cmipci_uswitch_put(kcontrol, ucontrol, args);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) #define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) static struct cmipci_switch_args cmipci_switch_arg_##sname = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) .reg = xreg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) .mask = xmask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) .mask_on = xmask_on, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) .is_byte = xis_byte, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) .ac3_sensitive = xac3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) #define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) #if 0 /* these will be controlled in pcm device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) DEFINE_BIT_SWITCH_ARG(spdif_in_sel1, CM_REG_CHFORMAT, CM_SPDIF_SELECT1, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) DEFINE_BIT_SWITCH_ARG(spdif_in_sel2, CM_REG_MISC_CTRL, CM_SPDIF_SELECT2, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) DEFINE_BIT_SWITCH_ARG(spdif_enable, CM_REG_LEGACY_CTRL, CM_ENSPDOUT, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) DEFINE_BIT_SWITCH_ARG(spdi_valid, CM_REG_MISC, CM_SPDVALID, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) DEFINE_BIT_SWITCH_ARG(spdif_copyright, CM_REG_LEGACY_CTRL, CM_SPDCOPYRHT, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) DEFINE_BIT_SWITCH_ARG(spdif_dac_out, CM_REG_LEGACY_CTRL, CM_DAC2SPDO, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) DEFINE_SWITCH_ARG(spdo_5v, CM_REG_MISC_CTRL, CM_SPDO5V, 0, 0, 0); /* inverse: 0 = 5V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) // DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) DEFINE_BIT_SWITCH_ARG(spdi_monitor, CM_REG_MIXER1, CM_CDPLAY, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) /* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_MISC, CM_SPDIF_INVERSE, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) DEFINE_BIT_SWITCH_ARG(spdi_phase2, CM_REG_CHFORMAT, CM_SPDIF_INVERSE2, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) #if CM_CH_PLAY == 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, 0, 0, 0); /* reversed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) DEFINE_SWITCH_ARG(exchange_dac, CM_REG_MISC_CTRL, CM_XCHGDAC, CM_XCHGDAC, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) DEFINE_BIT_SWITCH_ARG(fourch, CM_REG_MISC_CTRL, CM_N4SPK3D, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) // DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_REAR2LIN, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) // DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_CENTR2LIN|CM_BASE2LIN, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) // DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) DEFINE_SWITCH_ARG(modem, CM_REG_MISC_CTRL, CM_FLINKON|CM_FLINKOFF, CM_FLINKON, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) #define DEFINE_SWITCH(sname, stype, sarg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) { .name = sname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) .iface = stype, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) .info = snd_cmipci_uswitch_info, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) .get = snd_cmipci_uswitch_get, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) .put = snd_cmipci_uswitch_put, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) #define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) #define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) * callbacks for spdif output switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) * needs toggle two registers..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) static int snd_cmipci_spdout_enable_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) int changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) changed = _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) changed |= _snd_cmipci_uswitch_get(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) return changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) static int snd_cmipci_spdout_enable_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) struct cmipci *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) int changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) changed = _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdif_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) changed |= _snd_cmipci_uswitch_put(kcontrol, ucontrol, &cmipci_switch_arg_spdo2dac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) if (changed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) if (ucontrol->value.integer.value[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) if (chip->spdif_playback_avail)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) if (chip->spdif_playback_avail)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) chip->spdif_playback_enabled = ucontrol->value.integer.value[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) return changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) static int snd_cmipci_line_in_mode_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) struct cmipci *cm = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) static const char *const texts[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) "Line-In", "Rear Output", "Bass Output"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) return snd_ctl_enum_info(uinfo, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) cm->chip_version >= 39 ? 3 : 2, texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) static inline unsigned int get_line_in_mode(struct cmipci *cm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) if (cm->chip_version >= 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) if (val & (CM_CENTR2LIN | CM_BASE2LIN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) val = snd_cmipci_read_b(cm, CM_REG_MIXER1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) if (val & CM_REAR2LIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) static int snd_cmipci_line_in_mode_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) struct cmipci *cm = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) spin_lock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) ucontrol->value.enumerated.item[0] = get_line_in_mode(cm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) spin_unlock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) static int snd_cmipci_line_in_mode_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) struct cmipci *cm = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) spin_lock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) if (ucontrol->value.enumerated.item[0] == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) change = snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) change = snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_CENTR2LIN | CM_BASE2LIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) if (ucontrol->value.enumerated.item[0] == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) change |= snd_cmipci_set_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) change |= snd_cmipci_clear_bit_b(cm, CM_REG_MIXER1, CM_REAR2LIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) spin_unlock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) static int snd_cmipci_mic_in_mode_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) static const char *const texts[2] = { "Mic-In", "Center/LFE Output" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) return snd_ctl_enum_info(uinfo, 1, 2, texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) static int snd_cmipci_mic_in_mode_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) struct cmipci *cm = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) /* same bit as spdi_phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) spin_lock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) ucontrol->value.enumerated.item[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) (snd_cmipci_read_b(cm, CM_REG_MISC) & CM_SPDIF_INVERSE) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) spin_unlock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) static int snd_cmipci_mic_in_mode_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) struct cmipci *cm = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) spin_lock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) if (ucontrol->value.enumerated.item[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) change = snd_cmipci_set_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) change = snd_cmipci_clear_bit_b(cm, CM_REG_MISC, CM_SPDIF_INVERSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) spin_unlock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) /* both for CM8338/8738 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) static const struct snd_kcontrol_new snd_cmipci_mixer_switches[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) DEFINE_MIXER_SWITCH("Four Channel Mode", fourch),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) .name = "Line-In Mode",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) .info = snd_cmipci_line_in_mode_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) .get = snd_cmipci_line_in_mode_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) .put = snd_cmipci_line_in_mode_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) /* for non-multichannel chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) static const struct snd_kcontrol_new snd_cmipci_nomulti_switch =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) /* only for CM8738 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) static const struct snd_kcontrol_new snd_cmipci_8738_mixer_switches[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) #if 0 /* controlled in pcm device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) { .name = "IEC958 Output Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) .info = snd_cmipci_uswitch_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) .get = snd_cmipci_spdout_enable_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) .put = snd_cmipci_spdout_enable_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) // DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) /* only for model 033/037 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) static const struct snd_kcontrol_new snd_cmipci_old_mixer_switches[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) /* only for model 039 or later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) static const struct snd_kcontrol_new snd_cmipci_extra_mixer_switches[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) .name = "Mic-In Mode",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) .info = snd_cmipci_mic_in_mode_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) .get = snd_cmipci_mic_in_mode_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) .put = snd_cmipci_mic_in_mode_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) /* card control switches */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) static const struct snd_kcontrol_new snd_cmipci_modem_switch =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) DEFINE_CARD_SWITCH("Modem", modem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) static int snd_cmipci_mixer_new(struct cmipci *cm, int pcm_spdif_device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) const struct snd_kcontrol_new *sw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) struct snd_kcontrol *kctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) if (snd_BUG_ON(!cm || !cm->card))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) card = cm->card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) strcpy(card->mixername, "CMedia PCI");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) spin_lock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) snd_cmipci_mixer_write(cm, 0x00, 0x00); /* mixer reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) spin_unlock_irq(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixers); idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) if (cm->chip_version == 68) { // 8768 has no PCM volume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) if (!strcmp(snd_cmipci_mixers[idx].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) "PCM Playback Volume"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_cmipci_mixers[idx], cm))) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) /* mixer switches */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) sw = snd_cmipci_mixer_switches;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_mixer_switches); idx++, sw++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) if (! cm->can_multi_ch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) err = snd_ctl_add(cm->card, snd_ctl_new1(&snd_cmipci_nomulti_switch, cm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) if (cm->device == PCI_DEVICE_ID_CMEDIA_CM8738 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) cm->device == PCI_DEVICE_ID_CMEDIA_CM8738B) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) sw = snd_cmipci_8738_mixer_switches;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_8738_mixer_switches); idx++, sw++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) if (cm->can_ac3_hw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_default, cm))) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) kctl->id.device = pcm_spdif_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_mask, cm))) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) kctl->id.device = pcm_spdif_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_cmipci_spdif_stream, cm))) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) kctl->id.device = pcm_spdif_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) if (cm->chip_version <= 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) sw = snd_cmipci_old_mixer_switches;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_old_mixer_switches); idx++, sw++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) if (cm->chip_version >= 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) sw = snd_cmipci_extra_mixer_switches;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) for (idx = 0; idx < ARRAY_SIZE(snd_cmipci_extra_mixer_switches); idx++, sw++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) err = snd_ctl_add(cm->card, snd_ctl_new1(sw, cm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) /* card switches */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) * newer chips don't have the register bits to force modem link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) * detection; the bit that was FLINKON now mutes CH1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) if (cm->chip_version < 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) err = snd_ctl_add(cm->card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) snd_ctl_new1(&snd_cmipci_modem_switch, cm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) for (idx = 0; idx < CM_SAVED_MIXERS; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) struct snd_ctl_elem_id elem_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) struct snd_kcontrol *ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) memset(&elem_id, 0, sizeof(elem_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) strcpy(elem_id.name, cm_saved_mixer[idx].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) ctl = snd_ctl_find_id(cm->card, &elem_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) if (ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) cm->mixer_res_ctl[idx] = ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) * proc interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) static void snd_cmipci_proc_read(struct snd_info_entry *entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) struct snd_info_buffer *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) struct cmipci *cm = entry->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) int i, v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) snd_iprintf(buffer, "%s\n", cm->card->longname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) for (i = 0; i < 0x94; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) if (i == 0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) i = 0x90;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) v = inb(cm->iobase + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) if (i % 4 == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) snd_iprintf(buffer, "\n%02x:", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) snd_iprintf(buffer, " %02x", v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) snd_iprintf(buffer, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) static void snd_cmipci_proc_init(struct cmipci *cm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) snd_card_ro_proc_new(cm->card, "cmipci", cm, snd_cmipci_proc_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) static const struct pci_device_id snd_cmipci_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338A), 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8338B), 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738), 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) {PCI_VDEVICE(CMEDIA, PCI_DEVICE_ID_CMEDIA_CM8738B), 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) {PCI_VDEVICE(AL, PCI_DEVICE_ID_CMEDIA_CM8738), 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) {0,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) * check chip version and capabilities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) * driver name is modified according to the chip model
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) static void query_chip(struct cmipci *cm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) unsigned int detect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) /* check reg 0Ch, bit 24-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) detect = snd_cmipci_read(cm, CM_REG_INT_HLDCLR) & CM_CHIP_MASK2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) if (! detect) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) /* check reg 08h, bit 24-28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) detect = snd_cmipci_read(cm, CM_REG_CHFORMAT) & CM_CHIP_MASK1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) switch (detect) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) cm->chip_version = 33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) if (cm->do_soft_ac3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) cm->can_ac3_sw = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) cm->can_ac3_hw = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) case CM_CHIP_037:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) cm->chip_version = 37;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) cm->can_ac3_hw = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) cm->chip_version = 39;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) cm->can_ac3_hw = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) cm->max_channels = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) if (detect & CM_CHIP_039) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) cm->chip_version = 39;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) if (detect & CM_CHIP_039_6CH) /* 4 or 6 channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) cm->max_channels = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) cm->max_channels = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) } else if (detect & CM_CHIP_8768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) cm->chip_version = 68;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) cm->max_channels = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) cm->can_96k = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) cm->chip_version = 55;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) cm->max_channels = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) cm->can_96k = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) cm->can_ac3_hw = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) cm->can_multi_ch = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) #ifdef SUPPORT_JOYSTICK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) static int snd_cmipci_create_gameport(struct cmipci *cm, int dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) static const int ports[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) struct gameport *gp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) struct resource *r = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) int i, io_port = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) if (joystick_port[dev] == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) if (joystick_port[dev] == 1) { /* auto-detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) for (i = 0; ports[i]; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) io_port = ports[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) r = request_region(io_port, 1, "CMIPCI gameport");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) io_port = joystick_port[dev];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) r = request_region(io_port, 1, "CMIPCI gameport");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) if (!r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) dev_warn(cm->card->dev, "cannot reserve joystick ports\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) cm->gameport = gp = gameport_allocate_port();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) if (!gp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) dev_err(cm->card->dev, "cannot allocate memory for gameport\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) release_and_free_resource(r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) gameport_set_name(gp, "C-Media Gameport");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) gameport_set_phys(gp, "pci%s/gameport0", pci_name(cm->pci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) gameport_set_dev_parent(gp, &cm->pci->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) gp->io = io_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) gameport_set_port_data(gp, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) gameport_register_port(cm->gameport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) static void snd_cmipci_free_gameport(struct cmipci *cm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) if (cm->gameport) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) struct resource *r = gameport_get_port_data(cm->gameport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) gameport_unregister_port(cm->gameport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) cm->gameport = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) release_and_free_resource(r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) static inline int snd_cmipci_create_gameport(struct cmipci *cm, int dev) { return -ENOSYS; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) static inline void snd_cmipci_free_gameport(struct cmipci *cm) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) static int snd_cmipci_free(struct cmipci *cm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) if (cm->irq >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) snd_cmipci_ch_reset(cm, CM_CH_PLAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) snd_cmipci_ch_reset(cm, CM_CH_CAPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) /* reset mixer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) snd_cmipci_mixer_write(cm, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) free_irq(cm->irq, cm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) snd_cmipci_free_gameport(cm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) pci_release_regions(cm->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) pci_disable_device(cm->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) kfree(cm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) static int snd_cmipci_dev_free(struct snd_device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) struct cmipci *cm = device->device_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) return snd_cmipci_free(cm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) static int snd_cmipci_create_fm(struct cmipci *cm, long fm_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) long iosynth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) struct snd_opl3 *opl3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) if (!fm_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) goto disable_fm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) if (cm->chip_version >= 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) /* first try FM regs in PCI port range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) iosynth = cm->iobase + CM_REG_FM_PCI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) err = snd_opl3_create(cm->card, iosynth, iosynth + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) OPL3_HW_OPL3, 1, &opl3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) /* then try legacy ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) val = snd_cmipci_read(cm, CM_REG_LEGACY_CTRL) & ~CM_FMSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) iosynth = fm_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) switch (iosynth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) case 0x3E8: val |= CM_FMSEL_3E8; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) case 0x3E0: val |= CM_FMSEL_3E0; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) case 0x3C8: val |= CM_FMSEL_3C8; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) case 0x388: val |= CM_FMSEL_388; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) goto disable_fm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) /* enable FM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) if (snd_opl3_create(cm->card, iosynth, iosynth + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) OPL3_HW_OPL3, 0, &opl3) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) dev_err(cm->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) "no OPL device at %#lx, skipping...\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) iosynth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) goto disable_fm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) dev_err(cm->card->dev, "cannot create OPL3 hwdep\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) disable_fm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_FMSEL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_FM_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) static int snd_cmipci_create(struct snd_card *card, struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) int dev, struct cmipci **rcmipci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) struct cmipci *cm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) static const struct snd_device_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) .dev_free = snd_cmipci_dev_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) long iomidi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) int integrated_midi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) char modelstr[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) int pcm_index, pcm_spdif_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) static const struct pci_device_id intel_82437vx[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) *rcmipci = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) if ((err = pci_enable_device(pci)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) cm = kzalloc(sizeof(*cm), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) if (cm == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) spin_lock_init(&cm->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) mutex_init(&cm->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) cm->device = pci->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) cm->card = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) cm->pci = pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) cm->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) cm->channel[0].ch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) cm->channel[1].ch = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) cm->channel[0].is_dac = cm->channel[1].is_dac = 1; /* dual DAC mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) if ((err = pci_request_regions(pci, card->driver)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) kfree(cm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) cm->iobase = pci_resource_start(pci, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) if (request_irq(pci->irq, snd_cmipci_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) IRQF_SHARED, KBUILD_MODNAME, cm)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) snd_cmipci_free(cm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) cm->irq = pci->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) card->sync_irq = cm->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) pci_set_master(cm->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) * check chip version, max channels and capabilities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) cm->chip_version = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) cm->max_channels = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) cm->do_soft_ac3 = soft_ac3[dev];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) if (pci->device != PCI_DEVICE_ID_CMEDIA_CM8338A &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) pci->device != PCI_DEVICE_ID_CMEDIA_CM8338B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) query_chip(cm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) /* added -MCx suffix for chip supporting multi-channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) if (cm->can_multi_ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) sprintf(cm->card->driver + strlen(cm->card->driver),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) "-MC%d", cm->max_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) else if (cm->can_ac3_sw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) strcpy(cm->card->driver + strlen(cm->card->driver), "-SWIEC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) cm->dig_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) cm->dig_pcm_status = SNDRV_PCM_DEFAULT_CON_SPDIF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) #if CM_CH_PLAY == 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) cm->ctrl = CM_CHADC0; /* default FUNCNTRL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) cm->ctrl = CM_CHADC1; /* default FUNCNTRL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) /* initialize codec registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0); /* disable ints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) snd_cmipci_ch_reset(cm, CM_CH_PLAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) snd_cmipci_ch_reset(cm, CM_CH_CAPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) snd_cmipci_write(cm, CM_REG_FUNCTRL0, 0); /* disable channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) snd_cmipci_write(cm, CM_REG_CHFORMAT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_ENDBDAC|CM_N4SPK3D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) #if CM_CH_PLAY == 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) snd_cmipci_clear_bit(cm, CM_REG_MISC_CTRL, CM_XCHGDAC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) if (cm->chip_version) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) snd_cmipci_write_b(cm, CM_REG_EXT_MISC, 0x20); /* magic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) snd_cmipci_write_b(cm, CM_REG_EXT_MISC + 1, 0x09); /* more magic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) /* Set Bus Master Request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) switch (pci->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) case PCI_DEVICE_ID_CMEDIA_CM8738:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) case PCI_DEVICE_ID_CMEDIA_CM8738B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) if (!pci_dev_present(intel_82437vx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_TXVX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) if (cm->chip_version < 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) val = pci->device < 0x110 ? 8338 : 8738;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) switch (snd_cmipci_read_b(cm, CM_REG_INT_HLDCLR + 3) & 0x03) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) val = 8769;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) val = 8762;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) switch ((pci->subsystem_vendor << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) pci->subsystem_device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) case 0x13f69761:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) case 0x584d3741:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) case 0x584d3751:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) case 0x584d3761:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) case 0x584d3771:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) case 0x72848384:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) val = 8770;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) val = 8768;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) sprintf(card->shortname, "C-Media CMI%d", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) if (cm->chip_version < 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) sprintf(modelstr, " (model %d)", cm->chip_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) modelstr[0] = '\0';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) sprintf(card->longname, "%s%s at %#lx, irq %i",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) card->shortname, modelstr, cm->iobase, cm->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, cm, &ops)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) snd_cmipci_free(cm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) if (cm->chip_version >= 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) val = snd_cmipci_read_b(cm, CM_REG_MPU_PCI + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) if (val != 0x00 && val != 0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) if (mpu_port[dev])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) iomidi = cm->iobase + CM_REG_MPU_PCI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) integrated_midi = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) if (!integrated_midi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) iomidi = mpu_port[dev];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) switch (iomidi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) case 0x320: val = CM_VMPU_320; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) case 0x310: val = CM_VMPU_310; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) case 0x300: val = CM_VMPU_300; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) case 0x330: val = CM_VMPU_330; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) iomidi = 0; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) if (iomidi > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) snd_cmipci_write(cm, CM_REG_LEGACY_CTRL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) /* enable UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) if (inb(iomidi + 1) == 0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) dev_err(cm->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) "cannot enable MPU-401 port at %#lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) iomidi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) CM_UART_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) iomidi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) if (cm->chip_version < 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) err = snd_cmipci_create_fm(cm, fm_port[dev]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) /* reset mixer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) snd_cmipci_mixer_write(cm, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) snd_cmipci_proc_init(cm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) /* create pcm devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) pcm_index = pcm_spdif_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) if ((err = snd_cmipci_pcm_new(cm, pcm_index)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) pcm_index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) if ((err = snd_cmipci_pcm2_new(cm, pcm_index)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) pcm_index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) if (cm->can_ac3_hw || cm->can_ac3_sw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) pcm_spdif_index = pcm_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) if ((err = snd_cmipci_pcm_spdif_new(cm, pcm_index)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) /* create mixer interface & switches */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) if ((err = snd_cmipci_mixer_new(cm, pcm_spdif_index)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) if (iomidi > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) iomidi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) (integrated_midi ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) MPU401_INFO_INTEGRATED : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) MPU401_INFO_IRQ_HOOK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) -1, &cm->rmidi)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) dev_err(cm->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) "no UART401 device at 0x%lx\n", iomidi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) #ifdef USE_VAR48KRATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) for (val = 0; val < ARRAY_SIZE(rates); val++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) snd_cmipci_set_pll(cm, rates[val], val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) * (Re-)Enable external switch spdo_48k
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) snd_cmipci_set_bit(cm, CM_REG_MISC_CTRL, CM_SPDIF48K|CM_SPDF_AC97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) #endif /* USE_VAR48KRATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) if (snd_cmipci_create_gameport(cm, dev) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) *rcmipci = cm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) MODULE_DEVICE_TABLE(pci, snd_cmipci_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) static int snd_cmipci_probe(struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) const struct pci_device_id *pci_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) static int dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) struct cmipci *cm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) if (dev >= SNDRV_CARDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) if (! enable[dev]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) dev++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) 0, &card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) switch (pci->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) case PCI_DEVICE_ID_CMEDIA_CM8738:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) case PCI_DEVICE_ID_CMEDIA_CM8738B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) strcpy(card->driver, "CMI8738");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) case PCI_DEVICE_ID_CMEDIA_CM8338A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) case PCI_DEVICE_ID_CMEDIA_CM8338B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) strcpy(card->driver, "CMI8338");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) strcpy(card->driver, "CMIPCI");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) err = snd_cmipci_create(card, pci, dev, &cm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) goto free_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) card->private_data = cm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) err = snd_card_register(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) goto free_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) pci_set_drvdata(pci, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) dev++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) free_card:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) static void snd_cmipci_remove(struct pci_dev *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) snd_card_free(pci_get_drvdata(pci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) * power management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) static const unsigned char saved_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) CM_REG_MIXER0, CM_REG_MIXER1, CM_REG_MIXER2, CM_REG_AUX_VOL, CM_REG_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) CM_REG_CH0_FRAME1, CM_REG_CH0_FRAME2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) CM_REG_CH1_FRAME1, CM_REG_CH1_FRAME2, CM_REG_EXT_MISC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) CM_REG_INT_STATUS, CM_REG_INT_HLDCLR, CM_REG_FUNCTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) static const unsigned char saved_mixers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) SB_DSP4_MASTER_DEV, SB_DSP4_MASTER_DEV + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) SB_DSP4_PCM_DEV, SB_DSP4_PCM_DEV + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) SB_DSP4_SYNTH_DEV, SB_DSP4_SYNTH_DEV + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) SB_DSP4_CD_DEV, SB_DSP4_CD_DEV + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) SB_DSP4_LINE_DEV, SB_DSP4_LINE_DEV + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) SB_DSP4_MIC_DEV, SB_DSP4_SPEAKER_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) CM_REG_EXTENT_IND, SB_DSP4_OUTPUT_SW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) static int snd_cmipci_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) struct cmipci *cm = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) /* save registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) cm->saved_regs[i] = snd_cmipci_read(cm, saved_regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) cm->saved_mixers[i] = snd_cmipci_mixer_read(cm, saved_mixers[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) /* disable ints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) static int snd_cmipci_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) struct cmipci *cm = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) /* reset / initialize to a sane state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) snd_cmipci_write(cm, CM_REG_INT_HLDCLR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) snd_cmipci_ch_reset(cm, CM_CH_PLAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) snd_cmipci_ch_reset(cm, CM_CH_CAPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) snd_cmipci_mixer_write(cm, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) /* restore registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) snd_cmipci_write(cm, saved_regs[i], cm->saved_regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) for (i = 0; i < ARRAY_SIZE(saved_mixers); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) snd_cmipci_mixer_write(cm, saved_mixers[i], cm->saved_mixers[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) snd_power_change_state(card, SNDRV_CTL_POWER_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) static SIMPLE_DEV_PM_OPS(snd_cmipci_pm, snd_cmipci_suspend, snd_cmipci_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) #define SND_CMIPCI_PM_OPS &snd_cmipci_pm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) #define SND_CMIPCI_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) static struct pci_driver cmipci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) .name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) .id_table = snd_cmipci_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) .probe = snd_cmipci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) .remove = snd_cmipci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) .pm = SND_CMIPCI_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) module_pci_driver(cmipci_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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