^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2004 James Courtier-Dutton <James@superbug.demon.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Driver CA0106 chips. e.g. Sound Blaster Audigy LS and Live 24bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Version: 0.0.25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * FEATURES currently supported:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Front, Rear and Center/LFE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Surround40 and Surround51.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Capture from MIC an LINE IN input.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * SPDIF digital playback of PCM stereo and AC3/DTS works.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * (One can use a standard mono mini-jack to one RCA plugs cable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * or one can use a standard stereo mini-jack to two RCA plugs cable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Plug one of the RCA plugs into the Coax input of the external decoder/receiver.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * ( In theory one could output 3 different AC3 streams at once, to 3 different SPDIF outputs. )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Notes on how to capture sound:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * The AC97 is used in the PLAYBACK direction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * The output from the AC97 chip, instead of reaching the speakers, is fed into the Philips 1361T ADC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * So, to record from the MIC, set the MIC Playback volume to max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * unmute the MIC and turn up the MASTER Playback volume.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * So, to prevent feedback when capturing, minimise the "Capture feedback into Playback" volume.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * The only playback controls that currently do anything are: -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Analog Front
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Analog Rear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Analog Center/LFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * SPDIF Front
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * SPDIF Rear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * SPDIF Center/LFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * For capture from Mic in or Line in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * Digital/Analog ( switch must be in Analog mode for CAPTURE. )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * CAPTURE feedback into PLAYBACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * Changelog:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Support interrupts per period.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Removed noise from Center/LFE channel when in Analog mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * Rename and remove mixer controls.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * 0.0.6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * Use separate card based DMA buffer for periods table list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * 0.0.7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * Change remove and rename ctrls into lists.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * 0.0.8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Try to fix capture sources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * 0.0.9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * Fix AC3 output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * Enable S32_LE format support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * 0.0.10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * Enable playback 48000 and 96000 rates. (Rates other that these do not work, even with "plug:front".)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * 0.0.11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Add Model name recognition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * 0.0.12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * Correct interrupt timing. interrupt at end of period, instead of in the middle of a playback period.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * Remove redundent "voice" handling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * 0.0.13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * Single trigger call for multi channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * 0.0.14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * Set limits based on what the sound card hardware can do.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * playback periods_min=2, periods_max=8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * capture hw constraints require period_size = n * 64 bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * playback hw constraints require period_size = n * 64 bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * 0.0.15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * Minor updates.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * 0.0.16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * Implement 192000 sample rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * 0.0.17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * Add support for SB0410 and SB0413.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * 0.0.18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * Modified Copyright message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * 0.0.19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * Finally fix support for SB Live 24 bit. SB0410 and SB0413.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * The output codec needs resetting, otherwise all output is muted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * 0.0.20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * Merge "pci_disable_device(pci);" fixes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * 0.0.21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * Add 4 capture channels. (SPDIF only comes in on channel 0. )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * Add SPDIF capture using optional digital I/O module for SB Live 24bit. (Analog capture does not yet work.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * 0.0.22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * Add support for MSI K8N Diamond Motherboard with onboard SB Live 24bit without AC97. From kiksen, bug #901
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * 0.0.23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * Implement support for Line-in capture on SB Live 24bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * 0.0.24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * Add support for mute control on SB Live 24bit (cards w/ SPI DAC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * 0.0.25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * Powerdown SPI DAC channels when not in use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * BUGS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * Some stability problems when unloading the snd-ca0106 kernel module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * --
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * TODO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * 4 Capture channels, only one implemented so far.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * Other capture rates apart from 48khz not implemented.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * MIDI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * --
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * GENERAL INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * Model: SB0310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * P17 Chip: CA0106-DAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * AC97 Codec: STAC 9721
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * ADC: Philips 1361T (Stereo 24bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * DAC: WM8746EDS (6-channel, 24bit, 192Khz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * GENERAL INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * Model: SB0410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * P17 Chip: CA0106-DAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * AC97 Codec: None
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * ADC: WM8775EDS (4 Channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * DAC: CS4382 (114 dB, 24-Bit, 192 kHz, 8-Channel D/A Converter with DSD Support)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * SPDIF Out control switches between Mic in and SPDIF out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * No sound out or mic input working yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * GENERAL INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * Model: SB0413
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * P17 Chip: CA0106-DAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * AC97 Codec: None.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * ADC: Unknown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * DAC: Unknown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * Trying to handle it like the SB0410.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * This code was initially based on code from ALSA's emu10k1x.c which is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * Copyright (c) by Francisco Moraes <fmoraes@nc.rr.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #include <sound/ac97_codec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #include <sound/info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) MODULE_AUTHOR("James Courtier-Dutton <James@superbug.demon.co.uk>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) MODULE_DESCRIPTION("CA0106");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) MODULE_SUPPORTED_DEVICE("{{Creative,SB CA0106 chip}}");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) // module parameters (see "Module Parameters")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static uint subsystem[SNDRV_CARDS]; /* Force card subsystem model */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) module_param_array(index, int, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) MODULE_PARM_DESC(index, "Index value for the CA0106 soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) module_param_array(id, charp, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) MODULE_PARM_DESC(id, "ID string for the CA0106 soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) module_param_array(enable, bool, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) MODULE_PARM_DESC(enable, "Enable the CA0106 soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) module_param_array(subsystem, uint, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) MODULE_PARM_DESC(subsystem, "Force card subsystem model.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #include "ca0106.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static const struct snd_ca0106_details ca0106_chip_details[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Sound Blaster X-Fi Extreme Audio. This does not have an AC97. 53SB079000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* It is really just a normal SB Live 24bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* Tested:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * See ALSA bug#3251
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { .serial = 0x10131102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .name = "X-Fi Extreme Audio [SBxxxx]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .gpio_type = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .i2c_adc = 1 } ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* Sound Blaster X-Fi Extreme Audio. This does not have an AC97. 53SB079000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* It is really just a normal SB Live 24bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * CTRL:CA0111-WTLF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * ADC: WM8775SEDS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * DAC: CS4382-KQZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* Tested:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * Playback on front, rear, center/lfe speakers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * Capture from Mic in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * Not-Tested:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * Capture from Line in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * Playback to digital out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { .serial = 0x10121102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .name = "X-Fi Extreme Audio [SB0790]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .gpio_type = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .i2c_adc = 1 } ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* New Dell Sound Blaster Live! 7.1 24bit. This does not have an AC97. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* AudigyLS[SB0310] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { .serial = 0x10021102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .name = "AudigyLS [SB0310]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .ac97 = 1 } ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Unknown AudigyLS that also says SB0310 on it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { .serial = 0x10051102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .name = "AudigyLS [SB0310b]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .ac97 = 1 } ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* New Sound Blaster Live! 7.1 24bit. This does not have an AC97. 53SB041000001 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { .serial = 0x10061102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .name = "Live! 7.1 24bit [SB0410]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .gpio_type = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .i2c_adc = 1 } ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* New Dell Sound Blaster Live! 7.1 24bit. This does not have an AC97. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) { .serial = 0x10071102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .name = "Live! 7.1 24bit [SB0413]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .gpio_type = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .i2c_adc = 1 } ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* New Audigy SE. Has a different DAC. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* SB0570:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * CTRL:CA0106-DAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * ADC: WM8775EDS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * DAC: WM8768GEDS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) { .serial = 0x100a1102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .name = "Audigy SE [SB0570]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .gpio_type = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .i2c_adc = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .spi_dac = 0x4021 } ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* New Audigy LS. Has a different DAC. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* SB0570:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * CTRL:CA0106-DAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * ADC: WM8775EDS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * DAC: WM8768GEDS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) { .serial = 0x10111102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .name = "Audigy SE OEM [SB0570a]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .gpio_type = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .i2c_adc = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .spi_dac = 0x4021 } ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* Sound Blaster 5.1vx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * Tested: Playback on front, rear, center/lfe speakers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * Not-Tested: Capture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { .serial = 0x10041102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .name = "Sound Blaster 5.1vx [SB1070]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .gpio_type = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .i2c_adc = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .spi_dac = 0x0124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) } ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* MSI K8N Diamond Motherboard with onboard SB Live 24bit without AC97 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* SB0438
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * CTRL:CA0106-DAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * ADC: WM8775SEDS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * DAC: CS4382-KQZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) { .serial = 0x10091462,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .name = "MSI K8N Diamond MB [SB0438]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .gpio_type = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .i2c_adc = 1 } ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* MSI K8N Diamond PLUS MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) { .serial = 0x10091102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .name = "MSI K8N Diamond MB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .gpio_type = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .i2c_adc = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .spi_dac = 0x4021 } ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* Giga-byte GA-G1975X mobo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * Novell bnc#395807
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* FIXME: the GPIO and I2C setting aren't tested well */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) { .serial = 0x1458a006,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .name = "Giga-byte GA-G1975X",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .gpio_type = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .i2c_adc = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* Shuttle XPC SD31P which has an onboard Creative Labs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * Sound Blaster Live! 24-bit EAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * high-definition 7.1 audio processor".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * Added using info from andrewvegan in alsa bug #1298
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) { .serial = 0x30381297,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .name = "Shuttle XPC SD31P [SD31P]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .gpio_type = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .i2c_adc = 1 } ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* Shuttle XPC SD11G5 which has an onboard Creative Labs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * Sound Blaster Live! 24-bit EAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * high-definition 7.1 audio processor".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * Fixes ALSA bug#1600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) { .serial = 0x30411297,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .name = "Shuttle XPC SD11G5 [SD11G5]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .gpio_type = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .i2c_adc = 1 } ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) { .serial = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .name = "AudigyLS [Unknown]" }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* hardware definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static const struct snd_pcm_hardware snd_ca0106_playback_hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .info = SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) SNDRV_PCM_INFO_BLOCK_TRANSFER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) SNDRV_PCM_INFO_SYNC_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .rates = (SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) SNDRV_PCM_RATE_192000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .rate_min = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .rate_max = 192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .channels_min = 2, //1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .channels_max = 2, //6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .buffer_bytes_max = ((65536 - 64) * 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .period_bytes_min = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .period_bytes_max = (65536 - 64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .periods_max = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .fifo_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static const struct snd_pcm_hardware snd_ca0106_capture_hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .info = (SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) SNDRV_PCM_INFO_BLOCK_TRANSFER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) SNDRV_PCM_INFO_MMAP_VALID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #if 0 /* FIXME: looks like 44.1kHz capture causes noisy output on 48kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .rates = (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .rate_min = 44100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .rates = (SNDRV_PCM_RATE_48000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .rate_min = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #endif /* FIXME */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .rate_max = 192000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .buffer_bytes_max = 65536 - 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .period_bytes_min = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .period_bytes_max = 32768 - 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .periods_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .fifo_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) unsigned int snd_ca0106_ptr_read(struct snd_ca0106 * emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) unsigned int chn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) unsigned int regptr, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) regptr = (reg << 16) | chn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) spin_lock_irqsave(&emu->emu_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) outl(regptr, emu->port + PTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) val = inl(emu->port + DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) spin_unlock_irqrestore(&emu->emu_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) void snd_ca0106_ptr_write(struct snd_ca0106 *emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) unsigned int chn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) unsigned int data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) unsigned int regptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) regptr = (reg << 16) | chn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) spin_lock_irqsave(&emu->emu_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) outl(regptr, emu->port + PTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) outl(data, emu->port + DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) spin_unlock_irqrestore(&emu->emu_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int snd_ca0106_spi_write(struct snd_ca0106 * emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) unsigned int data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) unsigned int reset, set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) unsigned int reg, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) int n, result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) reg = SPI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (data > 0xffff) /* Only 16bit values allowed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) tmp = snd_ca0106_ptr_read(emu, reg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) reset = (tmp & ~0x3ffff) | 0x20000; /* Set xxx20000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) set = reset | 0x10000; /* Set xxx1xxxx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) snd_ca0106_ptr_write(emu, reg, 0, reset | data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) tmp = snd_ca0106_ptr_read(emu, reg, 0); /* write post */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) snd_ca0106_ptr_write(emu, reg, 0, set | data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) result = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* Wait for status bit to return to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) for (n = 0; n < 100; n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) tmp = snd_ca0106_ptr_read(emu, reg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (!(tmp & 0x10000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (result) /* Timed out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) snd_ca0106_ptr_write(emu, reg, 0, reset | data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) tmp = snd_ca0106_ptr_read(emu, reg, 0); /* Write post */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* The ADC does not support i2c read, so only write is implemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) int snd_ca0106_i2c_write(struct snd_ca0106 *emu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) u32 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) int timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) int retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if ((reg > 0x7f) || (value > 0x1ff)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) dev_err(emu->card->dev, "i2c_write: invalid values.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) tmp = reg << 25 | value << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) dev_dbg(emu->card->dev, "I2C-write:reg=0x%x, value=0x%x\n", reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* Not sure what this I2C channel controls. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* snd_ca0106_ptr_write(emu, I2C_D0, 0, tmp); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* This controls the I2C connected to the WM8775 ADC Codec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) snd_ca0106_ptr_write(emu, I2C_D1, 0, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) for (retry = 0; retry < 10; retry++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* Send the data to i2c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) //tmp = snd_ca0106_ptr_read(emu, I2C_A, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) //tmp = tmp & ~(I2C_A_ADC_READ|I2C_A_ADC_LAST|I2C_A_ADC_START|I2C_A_ADC_ADD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) tmp = tmp | (I2C_A_ADC_LAST|I2C_A_ADC_START|I2C_A_ADC_ADD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) snd_ca0106_ptr_write(emu, I2C_A, 0, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* Wait till the transaction ends */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) status = snd_ca0106_ptr_read(emu, I2C_A, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /*dev_dbg(emu->card->dev, "I2C:status=0x%x\n", status);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) timeout++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if ((status & I2C_A_ADC_START) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (timeout > 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) //Read back and see if the transaction is successful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if ((status & I2C_A_ADC_ABORT) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (retry == 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) dev_err(emu->card->dev, "Writing to ADC failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static void snd_ca0106_intr_enable(struct snd_ca0106 *emu, unsigned int intrenb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) unsigned int intr_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) spin_lock_irqsave(&emu->emu_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) intr_enable = inl(emu->port + INTE) | intrenb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) outl(intr_enable, emu->port + INTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) spin_unlock_irqrestore(&emu->emu_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static void snd_ca0106_intr_disable(struct snd_ca0106 *emu, unsigned int intrenb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) unsigned int intr_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) spin_lock_irqsave(&emu->emu_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) intr_enable = inl(emu->port + INTE) & ~intrenb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) outl(intr_enable, emu->port + INTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) spin_unlock_irqrestore(&emu->emu_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static void snd_ca0106_pcm_free_substream(struct snd_pcm_runtime *runtime)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) kfree(runtime->private_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static const int spi_dacd_reg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) SPI_DACD0_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) SPI_DACD1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) SPI_DACD2_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) SPI_DACD4_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static const int spi_dacd_bit[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) SPI_DACD0_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) SPI_DACD1_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) SPI_DACD2_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) SPI_DACD4_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static void restore_spdif_bits(struct snd_ca0106 *chip, int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (chip->spdif_str_bits[idx] != chip->spdif_bits[idx]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) chip->spdif_str_bits[idx] = chip->spdif_bits[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) snd_ca0106_ptr_write(chip, SPCS0 + idx, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) chip->spdif_str_bits[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static int snd_ca0106_channel_dac(struct snd_ca0106 *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) const struct snd_ca0106_details *details,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) int channel_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) switch (channel_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) case PCM_FRONT_CHANNEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return (details->spi_dac & 0xf000) >> (4 * 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) case PCM_REAR_CHANNEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return (details->spi_dac & 0x0f00) >> (4 * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) case PCM_CENTER_LFE_CHANNEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return (details->spi_dac & 0x00f0) >> (4 * 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) case PCM_UNKNOWN_CHANNEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return (details->spi_dac & 0x000f) >> (4 * 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) dev_dbg(chip->card->dev, "ca0106: unknown channel_id %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) channel_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static int snd_ca0106_pcm_power_dac(struct snd_ca0106 *chip, int channel_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) int power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (chip->details->spi_dac) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) const int dac = snd_ca0106_channel_dac(chip, chip->details,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) channel_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) const int reg = spi_dacd_reg[dac];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) const int bit = spi_dacd_bit[dac];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* Power up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) chip->spi_dac_reg[reg] &= ~bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* Power down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) chip->spi_dac_reg[reg] |= bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (snd_ca0106_spi_write(chip, chip->spi_dac_reg[reg]) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* open_playback callback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static int snd_ca0106_pcm_open_playback_channel(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) int channel_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct snd_ca0106 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct snd_ca0106_channel *channel = &(chip->playback_channels[channel_id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct snd_ca0106_pcm *epcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) epcm = kzalloc(sizeof(*epcm), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (epcm == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) epcm->emu = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) epcm->substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) epcm->channel_id=channel_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) runtime->private_data = epcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) runtime->private_free = snd_ca0106_pcm_free_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) runtime->hw = snd_ca0106_playback_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) channel->emu = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) channel->number = channel_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) channel->use = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) dev_dbg(chip->card->dev, "open:channel_id=%d, chip=%p, channel=%p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) channel_id, chip, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) //channel->interrupt = snd_ca0106_pcm_channel_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) channel->epcm = epcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if ((err = snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 64)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) snd_pcm_set_sync(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* Front channel dac should already be on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (channel_id != PCM_FRONT_CHANNEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) err = snd_ca0106_pcm_power_dac(chip, channel_id, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) restore_spdif_bits(chip, channel_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /* close callback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static int snd_ca0106_pcm_close_playback(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct snd_ca0106 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) struct snd_ca0106_pcm *epcm = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) chip->playback_channels[epcm->channel_id].use = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) restore_spdif_bits(chip, epcm->channel_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /* Front channel dac should stay on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (epcm->channel_id != PCM_FRONT_CHANNEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) err = snd_ca0106_pcm_power_dac(chip, epcm->channel_id, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /* FIXME: maybe zero others */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static int snd_ca0106_pcm_open_playback_front(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return snd_ca0106_pcm_open_playback_channel(substream, PCM_FRONT_CHANNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static int snd_ca0106_pcm_open_playback_center_lfe(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return snd_ca0106_pcm_open_playback_channel(substream, PCM_CENTER_LFE_CHANNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static int snd_ca0106_pcm_open_playback_unknown(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return snd_ca0106_pcm_open_playback_channel(substream, PCM_UNKNOWN_CHANNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static int snd_ca0106_pcm_open_playback_rear(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return snd_ca0106_pcm_open_playback_channel(substream, PCM_REAR_CHANNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /* open_capture callback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static int snd_ca0106_pcm_open_capture_channel(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) int channel_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) struct snd_ca0106 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct snd_ca0106_channel *channel = &(chip->capture_channels[channel_id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) struct snd_ca0106_pcm *epcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) epcm = kzalloc(sizeof(*epcm), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (!epcm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) epcm->emu = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) epcm->substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) epcm->channel_id=channel_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) runtime->private_data = epcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) runtime->private_free = snd_ca0106_pcm_free_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) runtime->hw = snd_ca0106_capture_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) channel->emu = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) channel->number = channel_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) channel->use = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) dev_dbg(chip->card->dev, "open:channel_id=%d, chip=%p, channel=%p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) channel_id, chip, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) //channel->interrupt = snd_ca0106_pcm_channel_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) channel->epcm = epcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) //snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hw_constraints_capture_period_sizes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if ((err = snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 64)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* close callback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) static int snd_ca0106_pcm_close_capture(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct snd_ca0106 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) struct snd_ca0106_pcm *epcm = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) chip->capture_channels[epcm->channel_id].use = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) /* FIXME: maybe zero others */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static int snd_ca0106_pcm_open_0_capture(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return snd_ca0106_pcm_open_capture_channel(substream, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static int snd_ca0106_pcm_open_1_capture(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) return snd_ca0106_pcm_open_capture_channel(substream, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static int snd_ca0106_pcm_open_2_capture(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return snd_ca0106_pcm_open_capture_channel(substream, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static int snd_ca0106_pcm_open_3_capture(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return snd_ca0106_pcm_open_capture_channel(substream, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /* prepare playback callback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static int snd_ca0106_pcm_prepare_playback(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) struct snd_ca0106 *emu = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) struct snd_ca0106_pcm *epcm = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) int channel = epcm->channel_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) u32 *table_base = (u32 *)(emu->buffer.area+(8*16*channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) u32 period_size_bytes = frames_to_bytes(runtime, runtime->period_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) u32 hcfg_mask = HCFG_PLAYBACK_S32_LE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) u32 hcfg_set = 0x00000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) u32 hcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) u32 reg40_mask = 0x30000 << (channel<<1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) u32 reg40_set = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) u32 reg40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /* FIXME: Depending on mixer selection of SPDIF out or not, select the spdif rate or the DAC rate. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) u32 reg71_mask = 0x03030000 ; /* Global. Set SPDIF rate. We only support 44100 to spdif, not to DAC. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) u32 reg71_set = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) u32 reg71;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #if 0 /* debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) dev_dbg(emu->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) "prepare:channel_number=%d, rate=%d, format=0x%x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) "channels=%d, buffer_size=%ld, period_size=%ld, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) "periods=%u, frames_to_bytes=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) channel, runtime->rate, runtime->format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) runtime->channels, runtime->buffer_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) runtime->period_size, runtime->periods,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) frames_to_bytes(runtime, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) dev_dbg(emu->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) "dma_addr=%x, dma_area=%p, table_base=%p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) runtime->dma_addr, runtime->dma_area, table_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) dev_dbg(emu->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) "dma_addr=%x, dma_area=%p, dma_bytes(size)=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) emu->buffer.addr, emu->buffer.area, emu->buffer.bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #endif /* debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* Rate can be set per channel. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /* reg40 control host to fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /* reg71 controls DAC rate. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) switch (runtime->rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) case 44100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) reg40_set = 0x10000 << (channel<<1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) reg71_set = 0x01010000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) reg40_set = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) reg71_set = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) case 96000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) reg40_set = 0x20000 << (channel<<1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) reg71_set = 0x02020000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) case 192000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) reg40_set = 0x30000 << (channel<<1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) reg71_set = 0x03030000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) reg40_set = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) reg71_set = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /* Format is a global setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) /* FIXME: Only let the first channel accessed set this. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) switch (runtime->format) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) case SNDRV_PCM_FORMAT_S16_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) hcfg_set = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) case SNDRV_PCM_FORMAT_S32_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) hcfg_set = HCFG_PLAYBACK_S32_LE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) hcfg_set = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) hcfg = inl(emu->port + HCFG) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) hcfg = (hcfg & ~hcfg_mask) | hcfg_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) outl(hcfg, emu->port + HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) reg40 = snd_ca0106_ptr_read(emu, 0x40, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) reg40 = (reg40 & ~reg40_mask) | reg40_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) snd_ca0106_ptr_write(emu, 0x40, 0, reg40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) reg71 = snd_ca0106_ptr_read(emu, 0x71, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) reg71 = (reg71 & ~reg71_mask) | reg71_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) snd_ca0106_ptr_write(emu, 0x71, 0, reg71);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) /* FIXME: Check emu->buffer.size before actually writing to it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) for(i=0; i < runtime->periods; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) table_base[i*2] = runtime->dma_addr + (i * period_size_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) table_base[i*2+1] = period_size_bytes << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) snd_ca0106_ptr_write(emu, PLAYBACK_LIST_ADDR, channel, emu->buffer.addr+(8*16*channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) snd_ca0106_ptr_write(emu, PLAYBACK_LIST_SIZE, channel, (runtime->periods - 1) << 19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) snd_ca0106_ptr_write(emu, PLAYBACK_LIST_PTR, channel, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) snd_ca0106_ptr_write(emu, PLAYBACK_DMA_ADDR, channel, runtime->dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) snd_ca0106_ptr_write(emu, PLAYBACK_PERIOD_SIZE, channel, frames_to_bytes(runtime, runtime->period_size)<<16); // buffer size in bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) /* FIXME test what 0 bytes does. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) snd_ca0106_ptr_write(emu, PLAYBACK_PERIOD_SIZE, channel, 0); // buffer size in bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) snd_ca0106_ptr_write(emu, PLAYBACK_POINTER, channel, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) snd_ca0106_ptr_write(emu, 0x07, channel, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) snd_ca0106_ptr_write(emu, 0x08, channel, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) snd_ca0106_ptr_write(emu, PLAYBACK_MUTE, 0x0, 0x0); /* Unmute output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) snd_ca0106_ptr_write(emu, SPCS0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) SPCS_GENERATIONSTATUS | 0x00001200 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) 0x00000000 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) /* prepare capture callback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static int snd_ca0106_pcm_prepare_capture(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) struct snd_ca0106 *emu = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) struct snd_ca0106_pcm *epcm = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) int channel = epcm->channel_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) u32 hcfg_mask = HCFG_CAPTURE_S32_LE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) u32 hcfg_set = 0x00000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) u32 hcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) u32 over_sampling=0x2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) u32 reg71_mask = 0x0000c000 ; /* Global. Set ADC rate. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) u32 reg71_set = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) u32 reg71;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #if 0 /* debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) dev_dbg(emu->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) "prepare:channel_number=%d, rate=%d, format=0x%x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) "channels=%d, buffer_size=%ld, period_size=%ld, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) "periods=%u, frames_to_bytes=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) channel, runtime->rate, runtime->format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) runtime->channels, runtime->buffer_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) runtime->period_size, runtime->periods,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) frames_to_bytes(runtime, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) dev_dbg(emu->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) "dma_addr=%x, dma_area=%p, table_base=%p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) runtime->dma_addr, runtime->dma_area, table_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) dev_dbg(emu->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) "dma_addr=%x, dma_area=%p, dma_bytes(size)=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) emu->buffer.addr, emu->buffer.area, emu->buffer.bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #endif /* debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /* reg71 controls ADC rate. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) switch (runtime->rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) case 44100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) reg71_set = 0x00004000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) reg71_set = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) case 96000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) reg71_set = 0x00008000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) over_sampling=0xa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) case 192000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) reg71_set = 0x0000c000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) over_sampling=0xa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) reg71_set = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) /* Format is a global setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) /* FIXME: Only let the first channel accessed set this. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) switch (runtime->format) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) case SNDRV_PCM_FORMAT_S16_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) hcfg_set = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) case SNDRV_PCM_FORMAT_S32_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) hcfg_set = HCFG_CAPTURE_S32_LE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) hcfg_set = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) hcfg = inl(emu->port + HCFG) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) hcfg = (hcfg & ~hcfg_mask) | hcfg_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) outl(hcfg, emu->port + HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) reg71 = snd_ca0106_ptr_read(emu, 0x71, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) reg71 = (reg71 & ~reg71_mask) | reg71_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) snd_ca0106_ptr_write(emu, 0x71, 0, reg71);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (emu->details->i2c_adc == 1) { /* The SB0410 and SB0413 use I2C to control ADC. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) snd_ca0106_i2c_write(emu, ADC_MASTER, over_sampling); /* Adjust the over sampler to better suit the capture rate. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) dev_dbg(emu->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) "prepare:channel_number=%d, rate=%d, format=0x%x, channels=%d, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) "buffer_size=%ld, period_size=%ld, frames_to_bytes=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) channel, runtime->rate, runtime->format, runtime->channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) runtime->buffer_size, runtime->period_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) frames_to_bytes(runtime, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) snd_ca0106_ptr_write(emu, 0x13, channel, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) snd_ca0106_ptr_write(emu, CAPTURE_DMA_ADDR, channel, runtime->dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) snd_ca0106_ptr_write(emu, CAPTURE_BUFFER_SIZE, channel, frames_to_bytes(runtime, runtime->buffer_size)<<16); // buffer size in bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) snd_ca0106_ptr_write(emu, CAPTURE_POINTER, channel, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) /* trigger_playback callback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) static int snd_ca0106_pcm_trigger_playback(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) struct snd_ca0106 *emu = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) struct snd_pcm_runtime *runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) struct snd_ca0106_pcm *epcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) int channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) int result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) struct snd_pcm_substream *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) u32 basic = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) u32 extended = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) u32 bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) int running = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) running = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) running = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) snd_pcm_group_for_each_entry(s, substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (snd_pcm_substream_chip(s) != emu ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) s->stream != SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) runtime = s->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) epcm = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) channel = epcm->channel_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) /* dev_dbg(emu->card->dev, "channel=%d\n", channel); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) epcm->running = running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) basic |= (0x1 << channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) extended |= (0x10 << channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) snd_pcm_trigger_done(s, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) /* dev_dbg(emu->card->dev, "basic=0x%x, extended=0x%x\n",basic, extended); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) bits = snd_ca0106_ptr_read(emu, EXTENDED_INT_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) bits |= extended;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) snd_ca0106_ptr_write(emu, EXTENDED_INT_MASK, 0, bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) bits = snd_ca0106_ptr_read(emu, BASIC_INTERRUPT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) bits |= basic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) snd_ca0106_ptr_write(emu, BASIC_INTERRUPT, 0, bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) bits = snd_ca0106_ptr_read(emu, BASIC_INTERRUPT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) bits &= ~basic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) snd_ca0106_ptr_write(emu, BASIC_INTERRUPT, 0, bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) bits = snd_ca0106_ptr_read(emu, EXTENDED_INT_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) bits &= ~extended;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) snd_ca0106_ptr_write(emu, EXTENDED_INT_MASK, 0, bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) result = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) /* trigger_capture callback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) static int snd_ca0106_pcm_trigger_capture(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) struct snd_ca0106 *emu = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) struct snd_ca0106_pcm *epcm = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) int channel = epcm->channel_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) int result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) snd_ca0106_ptr_write(emu, EXTENDED_INT_MASK, 0, snd_ca0106_ptr_read(emu, EXTENDED_INT_MASK, 0) | (0x110000<<channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) snd_ca0106_ptr_write(emu, BASIC_INTERRUPT, 0, snd_ca0106_ptr_read(emu, BASIC_INTERRUPT, 0)|(0x100<<channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) epcm->running = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) snd_ca0106_ptr_write(emu, BASIC_INTERRUPT, 0, snd_ca0106_ptr_read(emu, BASIC_INTERRUPT, 0) & ~(0x100<<channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) snd_ca0106_ptr_write(emu, EXTENDED_INT_MASK, 0, snd_ca0106_ptr_read(emu, EXTENDED_INT_MASK, 0) & ~(0x110000<<channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) epcm->running = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) result = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) /* pointer_playback callback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) static snd_pcm_uframes_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) snd_ca0106_pcm_pointer_playback(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) struct snd_ca0106 *emu = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) struct snd_ca0106_pcm *epcm = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) unsigned int ptr, prev_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) int channel = epcm->channel_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) int timeout = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) if (!epcm->running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) prev_ptr = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) ptr = snd_ca0106_ptr_read(emu, PLAYBACK_LIST_PTR, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) ptr = (ptr >> 3) * runtime->period_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) ptr += bytes_to_frames(runtime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) snd_ca0106_ptr_read(emu, PLAYBACK_POINTER, channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) if (ptr >= runtime->buffer_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) ptr -= runtime->buffer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) if (prev_ptr == ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) return ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) prev_ptr = ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) } while (--timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) dev_warn(emu->card->dev, "ca0106: unstable DMA pointer!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) /* pointer_capture callback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) static snd_pcm_uframes_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) snd_ca0106_pcm_pointer_capture(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) struct snd_ca0106 *emu = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) struct snd_ca0106_pcm *epcm = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) snd_pcm_uframes_t ptr, ptr1, ptr2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) int channel = epcm->channel_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) if (!epcm->running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) ptr1 = snd_ca0106_ptr_read(emu, CAPTURE_POINTER, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) ptr2 = bytes_to_frames(runtime, ptr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) ptr=ptr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) if (ptr >= runtime->buffer_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) ptr -= runtime->buffer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) dev_dbg(emu->card->dev, "ptr1 = 0x%lx, ptr2=0x%lx, ptr=0x%lx, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) "buffer_size = 0x%x, period_size = 0x%x, bits=%d, rate=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) ptr1, ptr2, ptr, (int)runtime->buffer_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) (int)runtime->period_size, (int)runtime->frame_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) (int)runtime->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) return ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) /* operators */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) static const struct snd_pcm_ops snd_ca0106_playback_front_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) .open = snd_ca0106_pcm_open_playback_front,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .close = snd_ca0106_pcm_close_playback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .prepare = snd_ca0106_pcm_prepare_playback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .trigger = snd_ca0106_pcm_trigger_playback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .pointer = snd_ca0106_pcm_pointer_playback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) static const struct snd_pcm_ops snd_ca0106_capture_0_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .open = snd_ca0106_pcm_open_0_capture,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .close = snd_ca0106_pcm_close_capture,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) .prepare = snd_ca0106_pcm_prepare_capture,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) .trigger = snd_ca0106_pcm_trigger_capture,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) .pointer = snd_ca0106_pcm_pointer_capture,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) static const struct snd_pcm_ops snd_ca0106_capture_1_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) .open = snd_ca0106_pcm_open_1_capture,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) .close = snd_ca0106_pcm_close_capture,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) .prepare = snd_ca0106_pcm_prepare_capture,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) .trigger = snd_ca0106_pcm_trigger_capture,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) .pointer = snd_ca0106_pcm_pointer_capture,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) static const struct snd_pcm_ops snd_ca0106_capture_2_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) .open = snd_ca0106_pcm_open_2_capture,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .close = snd_ca0106_pcm_close_capture,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) .prepare = snd_ca0106_pcm_prepare_capture,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) .trigger = snd_ca0106_pcm_trigger_capture,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) .pointer = snd_ca0106_pcm_pointer_capture,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) static const struct snd_pcm_ops snd_ca0106_capture_3_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .open = snd_ca0106_pcm_open_3_capture,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .close = snd_ca0106_pcm_close_capture,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .prepare = snd_ca0106_pcm_prepare_capture,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .trigger = snd_ca0106_pcm_trigger_capture,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) .pointer = snd_ca0106_pcm_pointer_capture,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) static const struct snd_pcm_ops snd_ca0106_playback_center_lfe_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .open = snd_ca0106_pcm_open_playback_center_lfe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) .close = snd_ca0106_pcm_close_playback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) .prepare = snd_ca0106_pcm_prepare_playback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) .trigger = snd_ca0106_pcm_trigger_playback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) .pointer = snd_ca0106_pcm_pointer_playback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) static const struct snd_pcm_ops snd_ca0106_playback_unknown_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) .open = snd_ca0106_pcm_open_playback_unknown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) .close = snd_ca0106_pcm_close_playback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .prepare = snd_ca0106_pcm_prepare_playback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) .trigger = snd_ca0106_pcm_trigger_playback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) .pointer = snd_ca0106_pcm_pointer_playback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) static const struct snd_pcm_ops snd_ca0106_playback_rear_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .open = snd_ca0106_pcm_open_playback_rear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .close = snd_ca0106_pcm_close_playback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) .prepare = snd_ca0106_pcm_prepare_playback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) .trigger = snd_ca0106_pcm_trigger_playback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) .pointer = snd_ca0106_pcm_pointer_playback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) static unsigned short snd_ca0106_ac97_read(struct snd_ac97 *ac97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) unsigned short reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) struct snd_ca0106 *emu = ac97->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) unsigned short val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) spin_lock_irqsave(&emu->emu_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) outb(reg, emu->port + AC97ADDRESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) val = inw(emu->port + AC97DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) spin_unlock_irqrestore(&emu->emu_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) static void snd_ca0106_ac97_write(struct snd_ac97 *ac97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) unsigned short reg, unsigned short val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) struct snd_ca0106 *emu = ac97->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) spin_lock_irqsave(&emu->emu_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) outb(reg, emu->port + AC97ADDRESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) outw(val, emu->port + AC97DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) spin_unlock_irqrestore(&emu->emu_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) static int snd_ca0106_ac97(struct snd_ca0106 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) struct snd_ac97_bus *pbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) struct snd_ac97_template ac97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) static const struct snd_ac97_bus_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) .write = snd_ca0106_ac97_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) .read = snd_ca0106_ac97_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) pbus->no_vra = 1; /* we don't need VRA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) memset(&ac97, 0, sizeof(ac97));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) ac97.private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) ac97.scaps = AC97_SCAP_NO_SPDIF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) return snd_ac97_mixer(pbus, &ac97, &chip->ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) static void ca0106_stop_chip(struct snd_ca0106 *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) static int snd_ca0106_free(struct snd_ca0106 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) if (chip->res_port != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) /* avoid access to already used hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) ca0106_stop_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) if (chip->irq >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) free_irq(chip->irq, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) // release the data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) #if 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) if (chip->buffer.area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) snd_dma_free_pages(&chip->buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) // release the i/o port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) release_and_free_resource(chip->res_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) pci_disable_device(chip->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) kfree(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) static int snd_ca0106_dev_free(struct snd_device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) struct snd_ca0106 *chip = device->device_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) return snd_ca0106_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) static irqreturn_t snd_ca0106_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) struct snd_ca0106 *chip = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) unsigned int stat76;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) struct snd_ca0106_channel *pchannel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) status = inl(chip->port + IPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) if (! status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) stat76 = snd_ca0106_ptr_read(chip, EXTENDED_INT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) dev_dbg(emu->card->dev, "interrupt status = 0x%08x, stat76=0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) status, stat76);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) dev_dbg(emu->card->dev, "ptr=0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) snd_ca0106_ptr_read(chip, PLAYBACK_POINTER, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) mask = 0x11; /* 0x1 for one half, 0x10 for the other half period. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) for(i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) pchannel = &(chip->playback_channels[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) if (stat76 & mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) /* FIXME: Select the correct substream for period elapsed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) if(pchannel->use) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) snd_pcm_period_elapsed(pchannel->epcm->substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) /* dev_dbg(emu->card->dev, "interrupt [%d] used\n", i); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) dev_dbg(emu->card->dev, "channel=%p\n", pchannel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) dev_dbg(emu->card->dev, "interrupt stat76[%d] = %08x, use=%d, channel=%d\n", i, stat76, pchannel->use, pchannel->number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) mask <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) mask = 0x110000; /* 0x1 for one half, 0x10 for the other half period. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) for(i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) pchannel = &(chip->capture_channels[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) if (stat76 & mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) /* FIXME: Select the correct substream for period elapsed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) if(pchannel->use) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) snd_pcm_period_elapsed(pchannel->epcm->substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) /* dev_dbg(emu->card->dev, "interrupt [%d] used\n", i); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) dev_dbg(emu->card->dev, "channel=%p\n", pchannel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) dev_dbg(emu->card->dev, "interrupt stat76[%d] = %08x, use=%d, channel=%d\n", i, stat76, pchannel->use, pchannel->number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) mask <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) snd_ca0106_ptr_write(chip, EXTENDED_INT, 0, stat76);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) if (chip->midi.dev_id &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) (status & (chip->midi.ipr_tx|chip->midi.ipr_rx))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) if (chip->midi.interrupt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) chip->midi.interrupt(&chip->midi, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) chip->midi.interrupt_disable(&chip->midi, chip->midi.tx_enable | chip->midi.rx_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) // acknowledge the interrupt if necessary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) outl(status, chip->port+IPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) static const struct snd_pcm_chmap_elem surround_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) { .channels = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) .map = { SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) static const struct snd_pcm_chmap_elem clfe_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) { .channels = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) .map = { SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) static const struct snd_pcm_chmap_elem side_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) { .channels = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) .map = { SNDRV_CHMAP_SL, SNDRV_CHMAP_SR } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) static int snd_ca0106_pcm(struct snd_ca0106 *emu, int device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) const struct snd_pcm_chmap_elem *map = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) err = snd_pcm_new(emu->card, "ca0106", device, 1, 1, &pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) pcm->private_data = emu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) switch (device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ca0106_playback_front_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ca0106_capture_0_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) map = snd_pcm_std_chmaps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ca0106_playback_rear_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ca0106_capture_1_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) map = surround_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ca0106_playback_center_lfe_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ca0106_capture_2_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) map = clfe_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ca0106_playback_unknown_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ca0106_capture_3_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) map = side_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) pcm->info_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) strcpy(pcm->name, "CA0106");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) for(substream = pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) substream = substream->next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) snd_pcm_set_managed_buffer(substream, SNDRV_DMA_TYPE_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) &emu->pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) 64*1024, 64*1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) for (substream = pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) substream = substream->next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) snd_pcm_set_managed_buffer(substream, SNDRV_DMA_TYPE_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) &emu->pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) 64*1024, 64*1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK, map, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) 1 << 2, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) emu->pcm[device] = pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) #define SPI_REG(reg, value) (((reg) << SPI_REG_SHIFT) | (value))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) static const unsigned int spi_dac_init[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) SPI_REG(SPI_LDA1_REG, SPI_DA_BIT_0dB), /* 0dB dig. attenuation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) SPI_REG(SPI_RDA1_REG, SPI_DA_BIT_0dB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) SPI_REG(SPI_PL_REG, SPI_PL_BIT_L_L | SPI_PL_BIT_R_R | SPI_IZD_BIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) SPI_REG(SPI_FMT_REG, SPI_FMT_BIT_I2S | SPI_IWL_BIT_24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) SPI_REG(SPI_LDA2_REG, SPI_DA_BIT_0dB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) SPI_REG(SPI_RDA2_REG, SPI_DA_BIT_0dB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) SPI_REG(SPI_LDA3_REG, SPI_DA_BIT_0dB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) SPI_REG(SPI_RDA3_REG, SPI_DA_BIT_0dB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) SPI_REG(SPI_MASTDA_REG, SPI_DA_BIT_0dB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) SPI_REG(9, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) SPI_REG(SPI_MS_REG, SPI_DACD0_BIT | SPI_DACD1_BIT | SPI_DACD2_BIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) SPI_REG(12, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) SPI_REG(SPI_LDA4_REG, SPI_DA_BIT_0dB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) SPI_REG(SPI_RDA4_REG, SPI_DA_BIT_0dB | SPI_DA_BIT_UPDATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) SPI_REG(SPI_DACD4_REG, SPI_DACD4_BIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) static const unsigned int i2c_adc_init[][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) { 0x17, 0x00 }, /* Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) { 0x07, 0x00 }, /* Timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) { 0x0b, 0x22 }, /* Interface control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) { 0x0c, 0x22 }, /* Master mode control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) { 0x0d, 0x08 }, /* Powerdown control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) { 0x0e, 0xcf }, /* Attenuation Left 0x01 = -103dB, 0xff = 24dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) { 0x0f, 0xcf }, /* Attenuation Right 0.5dB steps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) { 0x10, 0x7b }, /* ALC Control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) { 0x11, 0x00 }, /* ALC Control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) { 0x12, 0x32 }, /* ALC Control 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) { 0x13, 0x00 }, /* Noise gate control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) { 0x14, 0xa6 }, /* Limiter control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) { 0x15, ADC_MUX_LINEIN }, /* ADC Mixer control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) static void ca0106_init_chip(struct snd_ca0106 *chip, int resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) int ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) unsigned int def_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) outl(0, chip->port + INTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) * Init to 0x02109204 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) * Clock accuracy = 0 (1000ppm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) * Sample Rate = 2 (48kHz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) * Audio Channel = 1 (Left of 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) * Source Number = 0 (Unspecified)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) * Generation Status = 1 (Original for Cat Code 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) * Cat Code = 12 (Digital Signal Mixer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) * Mode = 0 (Mode 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) * Emphasis = 0 (None)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) * CP = 1 (Copyright unasserted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) * AN = 0 (Audio data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) * P = 0 (Consumer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) def_bits =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) SPCS_GENERATIONSTATUS | 0x00001200 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) 0x00000000 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) if (!resume) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) chip->spdif_str_bits[0] = chip->spdif_bits[0] = def_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) chip->spdif_str_bits[1] = chip->spdif_bits[1] = def_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) chip->spdif_str_bits[2] = chip->spdif_bits[2] = def_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) chip->spdif_str_bits[3] = chip->spdif_bits[3] = def_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) /* Only SPCS1 has been tested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) snd_ca0106_ptr_write(chip, SPCS1, 0, chip->spdif_str_bits[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) snd_ca0106_ptr_write(chip, SPCS0, 0, chip->spdif_str_bits[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) snd_ca0106_ptr_write(chip, SPCS2, 0, chip->spdif_str_bits[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) snd_ca0106_ptr_write(chip, SPCS3, 0, chip->spdif_str_bits[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) snd_ca0106_ptr_write(chip, PLAYBACK_MUTE, 0, 0x00fc0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) snd_ca0106_ptr_write(chip, CAPTURE_MUTE, 0, 0x00fc0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) /* Write 0x8000 to AC97_REC_GAIN to mute it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) outb(AC97_REC_GAIN, chip->port + AC97ADDRESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) outw(0x8000, chip->port + AC97DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) #if 0 /* FIXME: what are these? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) snd_ca0106_ptr_write(chip, SPCS0, 0, 0x2108006);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) snd_ca0106_ptr_write(chip, 0x42, 0, 0x2108006);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) snd_ca0106_ptr_write(chip, 0x43, 0, 0x2108006);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) snd_ca0106_ptr_write(chip, 0x44, 0, 0x2108006);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) /* OSS drivers set this. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) /* snd_ca0106_ptr_write(chip, SPDIF_SELECT2, 0, 0xf0f003f); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) /* Analog or Digital output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) snd_ca0106_ptr_write(chip, SPDIF_SELECT1, 0, 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) /* 0x0b000000 for digital, 0x000b0000 for analog, from win2000 drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) * Use 0x000f0000 for surround71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) snd_ca0106_ptr_write(chip, SPDIF_SELECT2, 0, 0x000f0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) chip->spdif_enable = 0; /* Set digital SPDIF output off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) /*snd_ca0106_ptr_write(chip, 0x45, 0, 0);*/ /* Analogue out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) /*snd_ca0106_ptr_write(chip, 0x45, 0, 0xf00);*/ /* Digital out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) /* goes to 0x40c80000 when doing SPDIF IN/OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) snd_ca0106_ptr_write(chip, CAPTURE_CONTROL, 0, 0x40c81000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) /* (Mute) CAPTURE feedback into PLAYBACK volume.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) * Only lower 16 bits matter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) snd_ca0106_ptr_write(chip, CAPTURE_CONTROL, 1, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) /* SPDIF IN Volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) snd_ca0106_ptr_write(chip, CAPTURE_CONTROL, 2, 0x30300000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) /* SPDIF IN Volume, 0x70 = (vol & 0x3f) | 0x40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) snd_ca0106_ptr_write(chip, CAPTURE_CONTROL, 3, 0x00700000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) snd_ca0106_ptr_write(chip, PLAYBACK_ROUTING1, 0, 0x32765410);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) snd_ca0106_ptr_write(chip, PLAYBACK_ROUTING2, 0, 0x76767676);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) snd_ca0106_ptr_write(chip, CAPTURE_ROUTING1, 0, 0x32765410);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) snd_ca0106_ptr_write(chip, CAPTURE_ROUTING2, 0, 0x76767676);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) for (ch = 0; ch < 4; ch++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) /* Only high 16 bits matter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) snd_ca0106_ptr_write(chip, CAPTURE_VOLUME1, ch, 0x30303030);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) snd_ca0106_ptr_write(chip, CAPTURE_VOLUME2, ch, 0x30303030);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) #if 0 /* Mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) snd_ca0106_ptr_write(chip, PLAYBACK_VOLUME1, ch, 0x40404040);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) snd_ca0106_ptr_write(chip, PLAYBACK_VOLUME2, ch, 0x40404040);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) snd_ca0106_ptr_write(chip, PLAYBACK_VOLUME1, ch, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) snd_ca0106_ptr_write(chip, PLAYBACK_VOLUME2, ch, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) if (chip->details->i2c_adc == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) /* Select MIC, Line in, TAD in, AUX in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) snd_ca0106_ptr_write(chip, CAPTURE_SOURCE, 0x0, 0x333300e4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) /* Default to CAPTURE_SOURCE to i2s in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) if (!resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) chip->capture_source = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) } else if (chip->details->ac97 == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) /* Default to AC97 in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) snd_ca0106_ptr_write(chip, CAPTURE_SOURCE, 0x0, 0x444400e4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) /* Default to CAPTURE_SOURCE to AC97 in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) if (!resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) chip->capture_source = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) /* Select MIC, Line in, TAD in, AUX in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) snd_ca0106_ptr_write(chip, CAPTURE_SOURCE, 0x0, 0x333300e4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) /* Default to Set CAPTURE_SOURCE to i2s in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) if (!resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) chip->capture_source = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) if (chip->details->gpio_type == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) /* The SB0438 use GPIO differently. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) /* FIXME: Still need to find out what the other GPIO bits do.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) * E.g. For digital spdif out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) outl(0x0, chip->port+GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) /* outl(0x00f0e000, chip->port+GPIO); */ /* Analog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) outl(0x005f5301, chip->port+GPIO); /* Analog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) } else if (chip->details->gpio_type == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) /* The SB0410 and SB0413 use GPIO differently. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) /* FIXME: Still need to find out what the other GPIO bits do.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) * E.g. For digital spdif out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) outl(0x0, chip->port+GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) /* outl(0x00f0e000, chip->port+GPIO); */ /* Analog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) outl(0x005f5301, chip->port+GPIO); /* Analog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) outl(0x0, chip->port+GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) outl(0x005f03a3, chip->port+GPIO); /* Analog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) /* outl(0x005f02a2, chip->port+GPIO); */ /* SPDIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) snd_ca0106_intr_enable(chip, 0x105); /* Win2000 uses 0x1e0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) /* outl(HCFG_LOCKSOUNDCACHE|HCFG_AUDIOENABLE, chip->port+HCFG); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) /* 0x1000 causes AC3 to fails. Maybe it effects 24 bit output. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) /* outl(0x00001409, chip->port+HCFG); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) /* outl(0x00000009, chip->port+HCFG); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) /* AC97 2.0, Enable outputs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) outl(HCFG_AC97 | HCFG_AUDIOENABLE, chip->port+HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) if (chip->details->i2c_adc == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) /* The SB0410 and SB0413 use I2C to control ADC. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) int size, n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) size = ARRAY_SIZE(i2c_adc_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) /* dev_dbg(emu->card->dev, "I2C:array size=0x%x\n", size); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) for (n = 0; n < size; n++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) snd_ca0106_i2c_write(chip, i2c_adc_init[n][0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) i2c_adc_init[n][1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) for (n = 0; n < 4; n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) chip->i2c_capture_volume[n][0] = 0xcf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) chip->i2c_capture_volume[n][1] = 0xcf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) chip->i2c_capture_source = 2; /* Line in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) /* Enable Line-in capture. MIC in currently untested. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) /* snd_ca0106_i2c_write(chip, ADC_MUX, ADC_MUX_LINEIN); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) if (chip->details->spi_dac) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) /* The SB0570 use SPI to control DAC. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) int size, n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) size = ARRAY_SIZE(spi_dac_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) for (n = 0; n < size; n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) int reg = spi_dac_init[n] >> SPI_REG_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) snd_ca0106_spi_write(chip, spi_dac_init[n]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) if (reg < ARRAY_SIZE(chip->spi_dac_reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) chip->spi_dac_reg[reg] = spi_dac_init[n];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) /* Enable front dac only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) snd_ca0106_pcm_power_dac(chip, PCM_FRONT_CHANNEL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) static void ca0106_stop_chip(struct snd_ca0106 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) /* disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) snd_ca0106_ptr_write(chip, BASIC_INTERRUPT, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) outl(0, chip->port + INTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) snd_ca0106_ptr_write(chip, EXTENDED_INT_MASK, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) udelay(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) /* disable audio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) /* outl(HCFG_LOCKSOUNDCACHE, chip->port + HCFG); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) outl(0, chip->port + HCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) /* FIXME: We need to stop and DMA transfers here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) * But as I am not sure how yet, we cannot from the dma pages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) * So we can fix: snd-malloc: Memory leak? pages not freed = 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) static int snd_ca0106_create(int dev, struct snd_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) struct snd_ca0106 **rchip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) struct snd_ca0106 *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) const struct snd_ca0106_details *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) static const struct snd_device_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) .dev_free = snd_ca0106_dev_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) *rchip = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) err = pci_enable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) if (dma_set_mask(&pci->dev, DMA_BIT_MASK(32)) < 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) dev_err(card->dev, "error to set 32bit mask DMA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) chip = kzalloc(sizeof(*chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) if (chip == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) chip->card = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) chip->pci = pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) chip->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) spin_lock_init(&chip->emu_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) chip->port = pci_resource_start(pci, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) chip->res_port = request_region(chip->port, 0x20, "snd_ca0106");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) if (!chip->res_port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) snd_ca0106_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) dev_err(card->dev, "cannot allocate the port\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) if (request_irq(pci->irq, snd_ca0106_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) IRQF_SHARED, KBUILD_MODNAME, chip)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) snd_ca0106_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) dev_err(card->dev, "cannot grab irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) chip->irq = pci->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) card->sync_irq = chip->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) /* This stores the periods table. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) 1024, &chip->buffer) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) snd_ca0106_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) pci_set_master(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) /* read serial */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) pci_read_config_dword(pci, PCI_SUBSYSTEM_VENDOR_ID, &chip->serial);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &chip->model);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) dev_info(card->dev, "Model %04x Rev %08x Serial %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) chip->model, pci->revision, chip->serial);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) strcpy(card->driver, "CA0106");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) strcpy(card->shortname, "CA0106");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) for (c = ca0106_chip_details; c->serial; c++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) if (subsystem[dev]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) if (c->serial == subsystem[dev])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) } else if (c->serial == chip->serial)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) chip->details = c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) if (subsystem[dev]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) dev_info(card->dev, "Sound card name=%s, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) "subsystem=0x%x. Forced to subsystem=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) c->name, chip->serial, subsystem[dev]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) sprintf(card->longname, "%s at 0x%lx irq %i",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) c->name, chip->port, chip->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) ca0106_init_chip(chip, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) snd_ca0106_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) *rchip = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) static void ca0106_midi_interrupt_enable(struct snd_ca_midi *midi, int intr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) snd_ca0106_intr_enable((struct snd_ca0106 *)(midi->dev_id), intr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) static void ca0106_midi_interrupt_disable(struct snd_ca_midi *midi, int intr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) snd_ca0106_intr_disable((struct snd_ca0106 *)(midi->dev_id), intr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) static unsigned char ca0106_midi_read(struct snd_ca_midi *midi, int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) return (unsigned char)snd_ca0106_ptr_read((struct snd_ca0106 *)(midi->dev_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) midi->port + idx, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) static void ca0106_midi_write(struct snd_ca_midi *midi, int data, int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) snd_ca0106_ptr_write((struct snd_ca0106 *)(midi->dev_id), midi->port + idx, 0, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) static struct snd_card *ca0106_dev_id_card(void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) return ((struct snd_ca0106 *)dev_id)->card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) static int ca0106_dev_id_port(void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) return ((struct snd_ca0106 *)dev_id)->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) static int snd_ca0106_midi(struct snd_ca0106 *chip, unsigned int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) struct snd_ca_midi *midi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) if (channel == CA0106_MIDI_CHAN_B) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) name = "CA0106 MPU-401 (UART) B";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) midi = &chip->midi2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) midi->tx_enable = INTE_MIDI_TX_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) midi->rx_enable = INTE_MIDI_RX_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) midi->ipr_tx = IPR_MIDI_TX_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) midi->ipr_rx = IPR_MIDI_RX_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) midi->port = MIDI_UART_B_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) name = "CA0106 MPU-401 (UART)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) midi = &chip->midi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) midi->tx_enable = INTE_MIDI_TX_A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) midi->rx_enable = INTE_MIDI_TX_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) midi->ipr_tx = IPR_MIDI_TX_A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) midi->ipr_rx = IPR_MIDI_RX_A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) midi->port = MIDI_UART_A_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) midi->reset = CA0106_MPU401_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) midi->enter_uart = CA0106_MPU401_ENTER_UART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) midi->ack = CA0106_MPU401_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) midi->input_avail = CA0106_MIDI_INPUT_AVAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) midi->output_ready = CA0106_MIDI_OUTPUT_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) midi->channel = channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) midi->interrupt_enable = ca0106_midi_interrupt_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) midi->interrupt_disable = ca0106_midi_interrupt_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) midi->read = ca0106_midi_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) midi->write = ca0106_midi_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) midi->get_dev_id_card = ca0106_dev_id_card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) midi->get_dev_id_port = ca0106_dev_id_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) midi->dev_id = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) if ((err = ca_midi_init(chip, midi, 0, name)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) static int snd_ca0106_probe(struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) const struct pci_device_id *pci_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) static int dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) struct snd_ca0106 *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) if (dev >= SNDRV_CARDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) if (!enable[dev]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) dev++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) 0, &card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) err = snd_ca0106_create(dev, card, pci, &chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) card->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) err = snd_ca0106_pcm(chip, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) if (chip->details->ac97 == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) /* The SB0410 and SB0413 do not have an AC97 chip. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) err = snd_ca0106_ac97(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) err = snd_ca0106_mixer(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) dev_dbg(card->dev, "probe for MIDI channel A ...");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) err = snd_ca0106_midi(chip, CA0106_MIDI_CHAN_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) dev_dbg(card->dev, " done.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) #ifdef CONFIG_SND_PROC_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) snd_ca0106_proc_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) err = snd_card_register(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) pci_set_drvdata(pci, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) dev++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) static void snd_ca0106_remove(struct pci_dev *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) snd_card_free(pci_get_drvdata(pci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) static int snd_ca0106_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) struct snd_ca0106 *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) if (chip->details->ac97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) snd_ac97_suspend(chip->ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) snd_ca0106_mixer_suspend(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) ca0106_stop_chip(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) static int snd_ca0106_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) struct snd_ca0106 *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) ca0106_init_chip(chip, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) if (chip->details->ac97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) snd_ac97_resume(chip->ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) snd_ca0106_mixer_resume(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) if (chip->details->spi_dac) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) for (i = 0; i < ARRAY_SIZE(chip->spi_dac_reg); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) snd_ca0106_spi_write(chip, chip->spi_dac_reg[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) snd_power_change_state(card, SNDRV_CTL_POWER_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) static SIMPLE_DEV_PM_OPS(snd_ca0106_pm, snd_ca0106_suspend, snd_ca0106_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) #define SND_CA0106_PM_OPS &snd_ca0106_pm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) #define SND_CA0106_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) // PCI IDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) static const struct pci_device_id snd_ca0106_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) { PCI_VDEVICE(CREATIVE, 0x0007), 0 }, /* Audigy LS or Live 24bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) MODULE_DEVICE_TABLE(pci, snd_ca0106_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) // pci_driver definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) static struct pci_driver ca0106_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) .name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) .id_table = snd_ca0106_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) .probe = snd_ca0106_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) .remove = snd_ca0106_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) .pm = SND_CA0106_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) module_pci_driver(ca0106_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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