^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * bt87x.c - Brooktree Bt878/Bt879 driver for ALSA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * based on btaudio.c by Gerd Knorr <kraxel@bytesex.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <sound/control.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) MODULE_DESCRIPTION("Brooktree Bt87x audio driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) MODULE_SUPPORTED_DEVICE("{{Brooktree,Bt878},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) "{Brooktree,Bt879}}");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static int index[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -2}; /* Exclude the first card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static int digital_rate[SNDRV_CARDS]; /* digital input rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static bool load_all; /* allow to load cards not the allowlist */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) module_param_array(index, int, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) MODULE_PARM_DESC(index, "Index value for Bt87x soundcard");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) module_param_array(id, charp, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) MODULE_PARM_DESC(id, "ID string for Bt87x soundcard");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) module_param_array(enable, bool, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) MODULE_PARM_DESC(enable, "Enable Bt87x soundcard");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) module_param_array(digital_rate, int, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) MODULE_PARM_DESC(digital_rate, "Digital input rate for Bt87x soundcard");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) module_param(load_all, bool, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) MODULE_PARM_DESC(load_all, "Allow to load cards not on the allowlist");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define REG_INT_STAT 0x100 /* interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define REG_INT_MASK 0x104 /* interrupt mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define REG_GPIO_DMA_CTL 0x10c /* audio control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define REG_PACKET_LEN 0x110 /* audio packet lengths */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define REG_RISC_STRT_ADD 0x114 /* RISC program start address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define REG_RISC_COUNT 0x120 /* RISC program counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* interrupt bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define INT_OFLOW (1 << 3) /* audio A/D overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define INT_RISCI (1 << 11) /* RISC instruction IRQ bit set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define INT_FBUS (1 << 12) /* FIFO overrun due to bus access latency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define INT_FTRGT (1 << 13) /* FIFO overrun due to target latency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define INT_FDSR (1 << 14) /* FIFO data stream resynchronization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define INT_PPERR (1 << 15) /* PCI parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define INT_RIPERR (1 << 16) /* RISC instruction parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define INT_PABORT (1 << 17) /* PCI master or target abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define INT_OCERR (1 << 18) /* invalid opcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define INT_SCERR (1 << 19) /* sync counter overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define INT_RISC_EN (1 << 27) /* DMA controller running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define INT_RISCS_SHIFT 28 /* RISC status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* audio control bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CTL_FIFO_ENABLE (1 << 0) /* enable audio data FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CTL_RISC_ENABLE (1 << 1) /* enable audio DMA controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CTL_PKTP_4 (0 << 2) /* packet mode FIFO trigger point - 4 DWORDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CTL_PKTP_8 (1 << 2) /* 8 DWORDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CTL_PKTP_16 (2 << 2) /* 16 DWORDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CTL_ACAP_EN (1 << 4) /* enable audio capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CTL_DA_APP (1 << 5) /* GPIO input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CTL_DA_IOM_AFE (0 << 6) /* audio A/D input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CTL_DA_IOM_DA (1 << 6) /* digital audio input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CTL_DA_SDR_SHIFT 8 /* DDF first stage decimation rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CTL_DA_SDR_MASK (0xf<< 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CTL_DA_LMT (1 << 12) /* limit audio data values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CTL_DA_ES2 (1 << 13) /* enable DDF stage 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CTL_DA_SBR (1 << 14) /* samples rounded to 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CTL_DA_DPM (1 << 15) /* data packet mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CTL_DA_LRD_SHIFT 16 /* ALRCK delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CTL_DA_MLB (1 << 21) /* MSB/LSB format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CTL_DA_LRI (1 << 22) /* left/right indication */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CTL_DA_SCE (1 << 23) /* sample clock edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CTL_A_SEL_STV (0 << 24) /* TV tuner audio input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CTL_A_SEL_SFM (1 << 24) /* FM audio input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CTL_A_SEL_SML (2 << 24) /* mic/line audio input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CTL_A_SEL_SMXC (3 << 24) /* MUX bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CTL_A_SEL_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CTL_A_SEL_MASK (3 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CTL_A_PWRDN (1 << 26) /* analog audio power-down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CTL_A_G2X (1 << 27) /* audio gain boost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CTL_A_GAIN_SHIFT 28 /* audio input gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CTL_A_GAIN_MASK (0xf<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* RISC instruction opcodes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define RISC_WRITE (0x1 << 28) /* write FIFO data to memory at address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define RISC_WRITEC (0x5 << 28) /* write FIFO data to memory at current address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define RISC_SKIP (0x2 << 28) /* skip FIFO data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define RISC_JUMP (0x7 << 28) /* jump to address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define RISC_SYNC (0x8 << 28) /* synchronize with FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* RISC instruction bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define RISC_BYTES_ENABLE (0xf << 12) /* byte enable bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define RISC_RESYNC ( 1 << 15) /* disable FDSR errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define RISC_SET_STATUS_SHIFT 16 /* set status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define RISC_RESET_STATUS_SHIFT 20 /* clear status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define RISC_IRQ ( 1 << 24) /* interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define RISC_EOL ( 1 << 26) /* end of line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define RISC_SOL ( 1 << 27) /* start of line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* SYNC status bits values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define RISC_SYNC_FM1 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define RISC_SYNC_VRO 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define ANALOG_CLOCK 1792000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #ifdef CONFIG_SND_BT87X_OVERCLOCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CLOCK_DIV_MIN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CLOCK_DIV_MIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CLOCK_DIV_MAX 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define ERROR_INTERRUPTS (INT_FBUS | INT_FTRGT | INT_PPERR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) INT_RIPERR | INT_PABORT | INT_OCERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MY_INTERRUPTS (INT_RISCI | ERROR_INTERRUPTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* SYNC, one WRITE per line, one extra WRITE per page boundary, SYNC, JUMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MAX_RISC_SIZE ((1 + 255 + (PAGE_ALIGN(255 * 4092) / PAGE_SIZE - 1) + 1 + 1) * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* Cards with configuration information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) enum snd_bt87x_boardid {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) SND_BT87X_BOARD_UNKNOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) SND_BT87X_BOARD_GENERIC, /* both an & dig interfaces, 32kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) SND_BT87X_BOARD_ANALOG, /* board with no external A/D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) SND_BT87X_BOARD_OSPREY2x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) SND_BT87X_BOARD_OSPREY440,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) SND_BT87X_BOARD_AVPHONE98,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* Card configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct snd_bt87x_board {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int dig_rate; /* Digital input sampling rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 digital_fmt; /* Register settings for digital input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) unsigned no_analog:1; /* No analog input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) unsigned no_digital:1; /* No digital input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static const struct snd_bt87x_board snd_bt87x_boards[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) [SND_BT87X_BOARD_UNKNOWN] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .dig_rate = 32000, /* just a guess */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) [SND_BT87X_BOARD_GENERIC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .dig_rate = 32000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) [SND_BT87X_BOARD_ANALOG] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .no_digital = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) [SND_BT87X_BOARD_OSPREY2x0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .dig_rate = 44100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .digital_fmt = CTL_DA_LRI | (1 << CTL_DA_LRD_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) [SND_BT87X_BOARD_OSPREY440] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .dig_rate = 32000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .digital_fmt = CTL_DA_LRI | (1 << CTL_DA_LRD_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .no_analog = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) [SND_BT87X_BOARD_AVPHONE98] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .dig_rate = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct snd_bt87x {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct pci_dev *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct snd_bt87x_board board;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) void __iomem *mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) spinlock_t reg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) unsigned long opened;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct snd_dma_buffer dma_risc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned int line_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned int lines;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u32 reg_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u32 interrupt_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int current_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int pci_parity_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) enum { DEVICE_DIGITAL, DEVICE_ANALOG };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static inline u32 snd_bt87x_readl(struct snd_bt87x *chip, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return readl(chip->mmio + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static inline void snd_bt87x_writel(struct snd_bt87x *chip, u32 reg, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) writel(value, chip->mmio + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static int snd_bt87x_create_risc(struct snd_bt87x *chip, struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) unsigned int periods, unsigned int period_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) unsigned int i, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) __le32 *risc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (chip->dma_risc.area == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) PAGE_ALIGN(MAX_RISC_SIZE), &chip->dma_risc) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) risc = (__le32 *)chip->dma_risc.area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) *risc++ = cpu_to_le32(RISC_SYNC | RISC_SYNC_FM1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) *risc++ = cpu_to_le32(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) for (i = 0; i < periods; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u32 rest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) rest = period_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u32 cmd, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) unsigned int addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) len = PAGE_SIZE - (offset % PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (len > rest)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) len = rest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) cmd = RISC_WRITE | len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (rest == period_bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u32 block = i * 16 / periods;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) cmd |= RISC_SOL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) cmd |= block << RISC_SET_STATUS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) cmd |= (~block & 0xf) << RISC_RESET_STATUS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (len == rest)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) cmd |= RISC_EOL | RISC_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) *risc++ = cpu_to_le32(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) addr = snd_pcm_sgbuf_get_addr(substream, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) *risc++ = cpu_to_le32(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) offset += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) rest -= len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) } while (rest > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) *risc++ = cpu_to_le32(RISC_SYNC | RISC_SYNC_VRO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) *risc++ = cpu_to_le32(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) *risc++ = cpu_to_le32(RISC_JUMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) *risc++ = cpu_to_le32(chip->dma_risc.addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) chip->line_bytes = period_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) chip->lines = periods;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static void snd_bt87x_free_risc(struct snd_bt87x *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (chip->dma_risc.area) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) snd_dma_free_pages(&chip->dma_risc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) chip->dma_risc.area = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static void snd_bt87x_pci_error(struct snd_bt87x *chip, unsigned int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) int pci_status = pci_status_get_and_clear_errors(chip->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (pci_status != PCI_STATUS_DETECTED_PARITY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) "Aieee - PCI error! status %#08x, PCI status %#04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) status & ERROR_INTERRUPTS, pci_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) "Aieee - PCI parity error detected!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* error 'handling' similar to aic7xxx_pci.c: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) chip->pci_parity_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (chip->pci_parity_errors > 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) "Too many PCI parity errors observed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) "Some device on this bus is generating bad parity.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) "This is an error *observed by*, not *generated by*, this card.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) "PCI parity error checking has been disabled.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) chip->interrupt_mask &= ~(INT_PPERR | INT_RIPERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) snd_bt87x_writel(chip, REG_INT_MASK, chip->interrupt_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static irqreturn_t snd_bt87x_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct snd_bt87x *chip = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) unsigned int status, irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) status = snd_bt87x_readl(chip, REG_INT_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) irq_status = status & chip->interrupt_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (!irq_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) snd_bt87x_writel(chip, REG_INT_STAT, irq_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (irq_status & ERROR_INTERRUPTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (irq_status & (INT_FBUS | INT_FTRGT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) dev_warn(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) "FIFO overrun, status %#08x\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (irq_status & INT_OCERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) dev_err(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) "internal RISC error, status %#08x\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (irq_status & (INT_PPERR | INT_RIPERR | INT_PABORT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) snd_bt87x_pci_error(chip, irq_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if ((irq_status & INT_RISCI) && (chip->reg_control & CTL_ACAP_EN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) int current_block, irq_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* assume that exactly one line has been recorded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) chip->current_line = (chip->current_line + 1) % chip->lines;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* but check if some interrupts have been skipped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) current_block = chip->current_line * 16 / chip->lines;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) irq_block = status >> INT_RISCS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (current_block != irq_block)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) chip->current_line = (irq_block * chip->lines + 15) / 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) snd_pcm_period_elapsed(chip->substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static const struct snd_pcm_hardware snd_bt87x_digital_hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .info = SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) SNDRV_PCM_INFO_BLOCK_TRANSFER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) SNDRV_PCM_INFO_BATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .rates = 0, /* set at runtime */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .buffer_bytes_max = 255 * 4092,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .period_bytes_min = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .period_bytes_max = 4092,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .periods_max = 255,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static const struct snd_pcm_hardware snd_bt87x_analog_hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .info = SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) SNDRV_PCM_INFO_BLOCK_TRANSFER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) SNDRV_PCM_INFO_BATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .rates = SNDRV_PCM_RATE_KNOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .rate_min = ANALOG_CLOCK / CLOCK_DIV_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .rate_max = ANALOG_CLOCK / CLOCK_DIV_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .channels_max = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .buffer_bytes_max = 255 * 4092,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .period_bytes_min = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .period_bytes_max = 4092,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .periods_max = 255,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static int snd_bt87x_set_digital_hw(struct snd_bt87x *chip, struct snd_pcm_runtime *runtime)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) chip->reg_control |= CTL_DA_IOM_DA | CTL_A_PWRDN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) runtime->hw = snd_bt87x_digital_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) runtime->hw.rates = snd_pcm_rate_to_rate_bit(chip->board.dig_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) runtime->hw.rate_min = chip->board.dig_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) runtime->hw.rate_max = chip->board.dig_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static int snd_bt87x_set_analog_hw(struct snd_bt87x *chip, struct snd_pcm_runtime *runtime)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static const struct snd_ratnum analog_clock = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .num = ANALOG_CLOCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .den_min = CLOCK_DIV_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .den_max = CLOCK_DIV_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .den_step = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static const struct snd_pcm_hw_constraint_ratnums constraint_rates = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .nrats = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .rats = &analog_clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) chip->reg_control &= ~(CTL_DA_IOM_DA | CTL_A_PWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) runtime->hw = snd_bt87x_analog_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return snd_pcm_hw_constraint_ratnums(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) &constraint_rates);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static int snd_bt87x_pcm_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct snd_bt87x *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (test_and_set_bit(0, &chip->opened))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (substream->pcm->device == DEVICE_DIGITAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) err = snd_bt87x_set_digital_hw(chip, runtime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) err = snd_bt87x_set_analog_hw(chip, runtime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) goto _error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) goto _error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) chip->substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) _error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) clear_bit(0, &chip->opened);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) smp_mb__after_atomic();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static int snd_bt87x_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct snd_bt87x *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) chip->reg_control |= CTL_A_PWRDN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) snd_bt87x_writel(chip, REG_GPIO_DMA_CTL, chip->reg_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) chip->substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) clear_bit(0, &chip->opened);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) smp_mb__after_atomic();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static int snd_bt87x_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct snd_pcm_hw_params *hw_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct snd_bt87x *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return snd_bt87x_create_risc(chip, substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) params_periods(hw_params),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) params_period_bytes(hw_params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static int snd_bt87x_hw_free(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct snd_bt87x *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) snd_bt87x_free_risc(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static int snd_bt87x_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct snd_bt87x *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) int decimation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) chip->reg_control &= ~(CTL_DA_SDR_MASK | CTL_DA_SBR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) decimation = (ANALOG_CLOCK + runtime->rate / 4) / runtime->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) chip->reg_control |= decimation << CTL_DA_SDR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (runtime->format == SNDRV_PCM_FORMAT_S8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) chip->reg_control |= CTL_DA_SBR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) snd_bt87x_writel(chip, REG_GPIO_DMA_CTL, chip->reg_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static int snd_bt87x_start(struct snd_bt87x *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) spin_lock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) chip->current_line = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) chip->reg_control |= CTL_FIFO_ENABLE | CTL_RISC_ENABLE | CTL_ACAP_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) snd_bt87x_writel(chip, REG_RISC_STRT_ADD, chip->dma_risc.addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) snd_bt87x_writel(chip, REG_PACKET_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) chip->line_bytes | (chip->lines << 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) snd_bt87x_writel(chip, REG_INT_MASK, chip->interrupt_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) snd_bt87x_writel(chip, REG_GPIO_DMA_CTL, chip->reg_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) spin_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static int snd_bt87x_stop(struct snd_bt87x *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) spin_lock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) chip->reg_control &= ~(CTL_FIFO_ENABLE | CTL_RISC_ENABLE | CTL_ACAP_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) snd_bt87x_writel(chip, REG_GPIO_DMA_CTL, chip->reg_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) snd_bt87x_writel(chip, REG_INT_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) snd_bt87x_writel(chip, REG_INT_STAT, MY_INTERRUPTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) spin_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static int snd_bt87x_trigger(struct snd_pcm_substream *substream, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct snd_bt87x *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return snd_bt87x_start(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return snd_bt87x_stop(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static snd_pcm_uframes_t snd_bt87x_pointer(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct snd_bt87x *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return (snd_pcm_uframes_t)bytes_to_frames(runtime, chip->current_line * chip->line_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static const struct snd_pcm_ops snd_bt87x_pcm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .open = snd_bt87x_pcm_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .close = snd_bt87x_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .hw_params = snd_bt87x_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .hw_free = snd_bt87x_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .prepare = snd_bt87x_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .trigger = snd_bt87x_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .pointer = snd_bt87x_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static int snd_bt87x_capture_volume_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) struct snd_ctl_elem_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) info->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) info->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) info->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) info->value.integer.max = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static int snd_bt87x_capture_volume_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct snd_ctl_elem_value *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct snd_bt87x *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) value->value.integer.value[0] = (chip->reg_control & CTL_A_GAIN_MASK) >> CTL_A_GAIN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static int snd_bt87x_capture_volume_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct snd_ctl_elem_value *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct snd_bt87x *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) u32 old_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) int changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) old_control = chip->reg_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) chip->reg_control = (chip->reg_control & ~CTL_A_GAIN_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) | (value->value.integer.value[0] << CTL_A_GAIN_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) snd_bt87x_writel(chip, REG_GPIO_DMA_CTL, chip->reg_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) changed = old_control != chip->reg_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static const struct snd_kcontrol_new snd_bt87x_capture_volume = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .name = "Capture Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .info = snd_bt87x_capture_volume_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .get = snd_bt87x_capture_volume_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .put = snd_bt87x_capture_volume_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define snd_bt87x_capture_boost_info snd_ctl_boolean_mono_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static int snd_bt87x_capture_boost_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct snd_ctl_elem_value *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct snd_bt87x *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) value->value.integer.value[0] = !! (chip->reg_control & CTL_A_G2X);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static int snd_bt87x_capture_boost_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct snd_ctl_elem_value *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) struct snd_bt87x *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) u32 old_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) int changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) old_control = chip->reg_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) chip->reg_control = (chip->reg_control & ~CTL_A_G2X)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) | (value->value.integer.value[0] ? CTL_A_G2X : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) snd_bt87x_writel(chip, REG_GPIO_DMA_CTL, chip->reg_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) changed = chip->reg_control != old_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static const struct snd_kcontrol_new snd_bt87x_capture_boost = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .name = "Capture Boost",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .info = snd_bt87x_capture_boost_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .get = snd_bt87x_capture_boost_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .put = snd_bt87x_capture_boost_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static int snd_bt87x_capture_source_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) struct snd_ctl_elem_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static const char *const texts[3] = {"TV Tuner", "FM", "Mic/Line"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return snd_ctl_enum_info(info, 1, 3, texts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static int snd_bt87x_capture_source_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) struct snd_ctl_elem_value *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) struct snd_bt87x *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) value->value.enumerated.item[0] = (chip->reg_control & CTL_A_SEL_MASK) >> CTL_A_SEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static int snd_bt87x_capture_source_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) struct snd_ctl_elem_value *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) struct snd_bt87x *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) u32 old_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) int changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) old_control = chip->reg_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) chip->reg_control = (chip->reg_control & ~CTL_A_SEL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) | (value->value.enumerated.item[0] << CTL_A_SEL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) snd_bt87x_writel(chip, REG_GPIO_DMA_CTL, chip->reg_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) changed = chip->reg_control != old_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static const struct snd_kcontrol_new snd_bt87x_capture_source = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .name = "Capture Source",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .info = snd_bt87x_capture_source_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .get = snd_bt87x_capture_source_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .put = snd_bt87x_capture_source_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static int snd_bt87x_free(struct snd_bt87x *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (chip->mmio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) snd_bt87x_stop(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (chip->irq >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) free_irq(chip->irq, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) iounmap(chip->mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) pci_release_regions(chip->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) pci_disable_device(chip->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) kfree(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static int snd_bt87x_dev_free(struct snd_device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) struct snd_bt87x *chip = device->device_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return snd_bt87x_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static int snd_bt87x_pcm(struct snd_bt87x *chip, int device, char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) err = snd_pcm_new(chip->card, name, device, 0, 1, &pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) pcm->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) strcpy(pcm->name, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_bt87x_pcm_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) &chip->pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) 128 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) ALIGN(255 * 4092, 1024));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static int snd_bt87x_create(struct snd_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) struct snd_bt87x **rchip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) struct snd_bt87x *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static const struct snd_device_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .dev_free = snd_bt87x_dev_free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) *rchip = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) err = pci_enable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) chip = kzalloc(sizeof(*chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if (!chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) chip->card = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) chip->pci = pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) chip->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) spin_lock_init(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if ((err = pci_request_regions(pci, "Bt87x audio")) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) kfree(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) chip->mmio = pci_ioremap_bar(pci, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (!chip->mmio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) dev_err(card->dev, "cannot remap io memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) chip->reg_control = CTL_A_PWRDN | CTL_DA_ES2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) CTL_PKTP_16 | (15 << CTL_DA_SDR_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) chip->interrupt_mask = MY_INTERRUPTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) snd_bt87x_writel(chip, REG_GPIO_DMA_CTL, chip->reg_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) snd_bt87x_writel(chip, REG_INT_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) snd_bt87x_writel(chip, REG_INT_STAT, MY_INTERRUPTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) err = request_irq(pci->irq, snd_bt87x_interrupt, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) KBUILD_MODNAME, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) dev_err(card->dev, "cannot grab irq %d\n", pci->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) chip->irq = pci->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) card->sync_irq = chip->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) pci_set_master(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) *rchip = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) snd_bt87x_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define BT_DEVICE(chip, subvend, subdev, id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) { .vendor = PCI_VENDOR_ID_BROOKTREE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .device = chip, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .subvendor = subvend, .subdevice = subdev, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .driver_data = SND_BT87X_BOARD_ ## id }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) /* driver_data is the card id for that device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static const struct pci_device_id snd_bt87x_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /* Hauppauge WinTV series */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) BT_DEVICE(PCI_DEVICE_ID_BROOKTREE_878, 0x0070, 0x13eb, GENERIC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) /* Hauppauge WinTV series */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) BT_DEVICE(PCI_DEVICE_ID_BROOKTREE_879, 0x0070, 0x13eb, GENERIC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /* Viewcast Osprey 200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) BT_DEVICE(PCI_DEVICE_ID_BROOKTREE_878, 0x0070, 0xff01, OSPREY2x0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) /* Viewcast Osprey 440 (rate is configurable via gpio) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) BT_DEVICE(PCI_DEVICE_ID_BROOKTREE_878, 0x0070, 0xff07, OSPREY440),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /* ATI TV-Wonder */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) BT_DEVICE(PCI_DEVICE_ID_BROOKTREE_878, 0x1002, 0x0001, GENERIC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /* Leadtek Winfast tv 2000xp delux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) BT_DEVICE(PCI_DEVICE_ID_BROOKTREE_878, 0x107d, 0x6606, GENERIC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /* Pinnacle PCTV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) BT_DEVICE(PCI_DEVICE_ID_BROOKTREE_878, 0x11bd, 0x0012, GENERIC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) /* Voodoo TV 200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) BT_DEVICE(PCI_DEVICE_ID_BROOKTREE_878, 0x121a, 0x3000, GENERIC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /* Askey Computer Corp. MagicTView'99 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) BT_DEVICE(PCI_DEVICE_ID_BROOKTREE_878, 0x144f, 0x3000, GENERIC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) /* AVerMedia Studio No. 103, 203, ...? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) BT_DEVICE(PCI_DEVICE_ID_BROOKTREE_878, 0x1461, 0x0003, AVPHONE98),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) /* Prolink PixelView PV-M4900 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) BT_DEVICE(PCI_DEVICE_ID_BROOKTREE_878, 0x1554, 0x4011, GENERIC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) /* Pinnacle Studio PCTV rave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) BT_DEVICE(PCI_DEVICE_ID_BROOKTREE_878, 0xbd11, 0x1200, GENERIC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) MODULE_DEVICE_TABLE(pci, snd_bt87x_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) /* cards known not to have audio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) * (DVB cards use the audio function to transfer MPEG data) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) static struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) unsigned short subvendor, subdevice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) } denylist[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) {0x0071, 0x0101}, /* Nebula Electronics DigiTV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) {0x11bd, 0x001c}, /* Pinnacle PCTV Sat */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {0x11bd, 0x0026}, /* Pinnacle PCTV SAT CI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) {0x1461, 0x0761}, /* AVermedia AverTV DVB-T */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {0x1461, 0x0771}, /* AVermedia DVB-T 771 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) {0x1822, 0x0001}, /* Twinhan VisionPlus DVB-T */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) {0x18ac, 0xd500}, /* DVICO FusionHDTV 5 Lite */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) {0x18ac, 0xdb10}, /* DVICO FusionHDTV DVB-T Lite */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) {0x18ac, 0xdb11}, /* Ultraview DVB-T Lite */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {0x270f, 0xfc00}, /* Chaintech Digitop DST-1000 DVB-S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) {0x7063, 0x2000}, /* pcHDTV HD-2000 TV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static struct pci_driver driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) /* return the id of the card, or a negative value if it's on the denylist */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static int snd_bt87x_detect_card(struct pci_dev *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) const struct pci_device_id *supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) supported = pci_match_id(snd_bt87x_ids, pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (supported && supported->driver_data > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return supported->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) for (i = 0; i < ARRAY_SIZE(denylist); ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (denylist[i].subvendor == pci->subsystem_vendor &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) denylist[i].subdevice == pci->subsystem_device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) dev_dbg(&pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) "card %#04x-%#04x:%#04x has no audio\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) pci->device, pci->subsystem_vendor, pci->subsystem_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) dev_info(&pci->dev, "unknown card %#04x-%#04x:%#04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) pci->device, pci->subsystem_vendor, pci->subsystem_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) dev_info(&pci->dev, "please mail id, board name, and, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) "if it works, the correct digital_rate option to "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) "<alsa-devel@alsa-project.org>\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return SND_BT87X_BOARD_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) static int snd_bt87x_probe(struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) const struct pci_device_id *pci_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) static int dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) struct snd_bt87x *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) enum snd_bt87x_boardid boardid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (!pci_id->driver_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) err = snd_bt87x_detect_card(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) boardid = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) boardid = pci_id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (dev >= SNDRV_CARDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) if (!enable[dev]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) ++dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) 0, &card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) err = snd_bt87x_create(card, pci, &chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) goto _error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) memcpy(&chip->board, &snd_bt87x_boards[boardid], sizeof(chip->board));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (!chip->board.no_digital) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (digital_rate[dev] > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) chip->board.dig_rate = digital_rate[dev];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) chip->reg_control |= chip->board.digital_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) err = snd_bt87x_pcm(chip, DEVICE_DIGITAL, "Bt87x Digital");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) goto _error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) if (!chip->board.no_analog) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) err = snd_bt87x_pcm(chip, DEVICE_ANALOG, "Bt87x Analog");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) goto _error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) err = snd_ctl_add(card, snd_ctl_new1(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) &snd_bt87x_capture_volume, chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) goto _error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) err = snd_ctl_add(card, snd_ctl_new1(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) &snd_bt87x_capture_boost, chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) goto _error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) err = snd_ctl_add(card, snd_ctl_new1(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) &snd_bt87x_capture_source, chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) goto _error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) dev_info(card->dev, "bt87x%d: Using board %d, %sanalog, %sdigital "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) "(rate %d Hz)\n", dev, boardid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) chip->board.no_analog ? "no " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) chip->board.no_digital ? "no " : "", chip->board.dig_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) strcpy(card->driver, "Bt87x");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) sprintf(card->shortname, "Brooktree Bt%x", pci->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) sprintf(card->longname, "%s at %#llx, irq %i",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) card->shortname, (unsigned long long)pci_resource_start(pci, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) chip->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) strcpy(card->mixername, "Bt87x");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) err = snd_card_register(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) goto _error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) pci_set_drvdata(pci, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) ++dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) _error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) static void snd_bt87x_remove(struct pci_dev *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) snd_card_free(pci_get_drvdata(pci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) /* default entries for all Bt87x cards - it's not exported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) /* driver_data is set to 0 to call detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) static const struct pci_device_id snd_bt87x_default_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) BT_DEVICE(PCI_DEVICE_ID_BROOKTREE_878, PCI_ANY_ID, PCI_ANY_ID, UNKNOWN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) BT_DEVICE(PCI_DEVICE_ID_BROOKTREE_879, PCI_ANY_ID, PCI_ANY_ID, UNKNOWN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) static struct pci_driver driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .id_table = snd_bt87x_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .probe = snd_bt87x_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .remove = snd_bt87x_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) static int __init alsa_card_bt87x_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) if (load_all)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) driver.id_table = snd_bt87x_default_ids;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) return pci_register_driver(&driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) static void __exit alsa_card_bt87x_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) pci_unregister_driver(&driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) module_init(alsa_card_bt87x_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) module_exit(alsa_card_bt87x_exit)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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