^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* azt3328.c - driver for Aztech AZF3328 based soundcards (e.g. PCI168).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2002, 2005 - 2011 by Andreas Mohr <andi AT lisas.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Framework borrowed from Bart Hartgers's als4000.c.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Driver developed on PCI168 AP(W) version (PCI rev. 10, subsystem ID 1801),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * found in a Fujitsu-Siemens PC ("Cordant", aluminum case).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Other versions are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * PCI168 A(W), sub ID 1800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * PCI168 A/AP, sub ID 8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Please give me feedback in case you try my driver with one of these!!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Keywords: Windows XP Vista 168nt4-125.zip 168win95-125.zip PCI 168 download
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * (XP/Vista do not support this card at all but every Linux distribution
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * has very good support out of the box;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * just to make sure that the right people hit this and get to know that,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * despite the high level of Internet ignorance - as usual :-P -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * about very good support for this card - on Linux!)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * NOTES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Since Aztech does not provide any chipset documentation,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * even on repeated request to various addresses,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * and the answer that was finally given was negative
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * (and I was stupid enough to manage to get hold of a PCI168 soundcard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * in the first place >:-P}),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * I was forced to base this driver on reverse engineering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * (3 weeks' worth of evenings filled with driver work).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * (and no, I did NOT go the easy way: to pick up a SB PCI128 for 9 Euros)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * It is quite likely that the AZF3328 chip is the PCI cousin of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * AZF3318 ("azt1020 pnp", "MM Pro 16") ISA chip, given very similar specs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * The AZF3328 chip (note: AZF3328, *not* AZT3328, that's just the driver name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * for compatibility reasons) from Azfin (joint-venture of Aztech and Fincitec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * Fincitec acquired by National Semiconductor in 2002, together with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * Fincitec-related company ARSmikro) has the following features:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * - compatibility & compliance:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * - Microsoft PC 97 ("PC 97 Hardware Design Guide",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * http://www.microsoft.com/whdc/archive/pcguides.mspx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * - Microsoft PC 98 Baseline Audio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * - MPU401 UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * - Sound Blaster Emulation (DOS Box)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * - builtin AC97 conformant codec (SNR over 80dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Note that "conformant" != "compliant"!! this chip's mixer register layout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * *differs* from the standard AC97 layout:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * they chose to not implement the headphone register (which is not a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * problem since it's merely optional), yet when doing this, they committed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * the grave sin of letting other registers follow immediately instead of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * keeping a headphone dummy register, thereby shifting the mixer register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * addresses illegally. So far unfortunately it looks like the very flexible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * ALSA AC97 support is still not enough to easily compensate for such a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * grave layout violation despite all tweaks and quirks mechanisms it offers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * Well, not quite: now ac97 layer is much improved (bus-specific ops!),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * thus I was able to implement support - it's actually working quite well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * An interesting item might be Aztech AMR 2800-W, since it's an AC97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * modem card which might reveal the Aztech-specific codec ID which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * we might want to pretend, too. Dito PCI168's brother, PCI368,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * where the advertising datasheet says it's AC97-based and has a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * Digital Enhanced Game Port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * - builtin genuine OPL3 - verified to work fine, 20080506
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * - full duplex 16bit playback/record at independent sampling rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * - MPU401 (+ legacy address support, claimed by one official spec sheet)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * FIXME: how to enable legacy addr??
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * - game port (legacy address support)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * - builtin DirectInput support, helps reduce CPU overhead (interrupt-driven
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * features supported). - See common term "Digital Enhanced Game Port"...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * (probably DirectInput 3.0 spec - confirm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * - builtin 3D enhancement (said to be YAMAHA Ymersion)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * - built-in General DirectX timer having a 20 bits counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * with 1us resolution (see below!)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * - I2S serial output port for external DAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * [FIXME: 3.3V or 5V level? maximum rate is 66.2kHz right?]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * - supports 33MHz PCI spec 2.1, PCI power management 1.0, compliant with ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * - supports hardware volume control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * - single chip low cost solution (128 pin QFP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * - supports programmable Sub-vendor and Sub-system ID [24C02 SEEPROM chip]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * required for Microsoft's logo compliance (FIXME: where?)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * At least the Trident 4D Wave DX has one bit somewhere
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * to enable writes to PCI subsystem VID registers, that should be it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * This might easily be in extended PCI reg space, since PCI168 also has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * some custom data starting at 0x80. What kind of config settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * are located in our extended PCI space anyway??
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * - PCI168 AP(W) card: power amplifier with 4 Watts/channel at 4 Ohms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * [TDA1517P chip]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * Note that this driver now is actually *better* than the Windows driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * since it additionally supports the card's 1MHz DirectX timer - just try
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * the following snd-seq module parameters etc.:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * - options snd-seq seq_default_timer_class=2 seq_default_timer_sclass=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * seq_default_timer_card=0 seq_client_load=1 seq_default_timer_device=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * seq_default_timer_subdevice=0 seq_default_timer_resolution=1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * - "timidity -iAv -B2,8 -Os -EFreverb=0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * - "pmidi -p 128:0 jazz.mid"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * OPL3 hardware playback testing, try something like:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * cat /proc/asound/hwdep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * aconnect -o
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * Then use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * sbiload -Dhw:x,y --opl3 /usr/share/sounds/opl3/std.o3 ......./drums.o3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * where x,y is the xx-yy number as given in hwdep.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * Then try
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * pmidi -p a:b jazz.mid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * where a:b is the client number plus 0 usually, as given by aconnect above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * Oh, and make sure to unmute the FM mixer control (doh!)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * NOTE: power use during OPL3 playback is _VERY_ high (70W --> 90W!)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * despite no CPU activity, possibly due to hindering ACPI idling somehow.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * Shouldn't be a problem of the AZF3328 chip itself, I'd hope.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * Higher PCM / FM mixer levels seem to conflict (causes crackling),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * at least sometimes. Maybe even use with hardware sequencer timer above :)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * adplay/adplug-utils might soon offer hardware-based OPL3 playback, too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * Certain PCI versions of this card are susceptible to DMA traffic underruns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * in some systems (resulting in sound crackling/clicking/popping),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * probably because they don't have a DMA FIFO buffer or so.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * Overview (PCI ID/PCI subID/PCI rev.):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * - no DMA crackling on SiS735: 0x50DC/0x1801/16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * - unknown performance: 0x50DC/0x1801/10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * (well, it's not bad on an Athlon 1800 with now very optimized IRQ handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * Crackling happens with VIA chipsets or, in my case, an SiS735, which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * supposed to be very fast and supposed to get rid of crackling much
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * better than a VIA, yet ironically I still get crackling, like many other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * people with the same chipset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * Possible remedies:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * - use speaker (amplifier) output instead of headphone output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * (in case crackling is due to overloaded output clipping)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * - plug card into a different PCI slot, preferably one that isn't shared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * too much (this helps a lot, but not completely!)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * - get rid of PCI VGA card, use AGP instead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * - upgrade or downgrade BIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * - fiddle with PCI latency settings (setpci -v -s BUSID latency_timer=XX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * Not too helpful.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * - Disable ACPI/power management/"Auto Detect RAM/PCI Clk" in BIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * BUGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * - full-duplex might *still* be problematic, however a recent test was fine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * - (non-bug) "Bass/Treble or 3D settings don't work" - they do get evaluated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * if you set PCM output switch to "pre 3D" instead of "post 3D".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * If this can't be set, then get a mixer application that Isn't Stupid (tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * (e.g. kmix, gamix) - unfortunately several are!!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * - locking is not entirely clean, especially the audio stream activity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * ints --> may be racy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * - an _unconnected_ secondary joystick at the gameport will be reported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * to be "active" (floating values, not precisely -1) due to the way we need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * to read the Digital Enhanced Game Port. Not sure whether it is fixable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * TODO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * - use PCI_VDEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * - verify driver status on x86_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * - test multi-card driver operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * - (ab)use 1MHz DirectX timer as kernel clocksource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * - test MPU401 MIDI playback etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * - add more power micro-management (disable various units of the card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * as long as they're unused, to improve audio quality and save power).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * However this requires more I/O ports which I haven't figured out yet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * and which thus might not even exist...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * The standard suspend/resume functionality could probably make use of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * some improvement, too...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * - figure out what all unknown port bits are responsible for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * - figure out some cleverly evil scheme to possibly make ALSA AC97 code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * fully accept our quite incompatible ""AC97"" mixer and thus save some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * code (but I'm not too optimistic that doing this is possible at all)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * - use MMIO (memory-mapped I/O)? Slightly faster access, e.g. for gameport.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #include <linux/bug.h> /* WARN_ONCE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #include <linux/gameport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #include <sound/control.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #include <sound/rawmidi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #include <sound/mpu401.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #include <sound/opl3.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * Config switch, to use ALSA's AC97 layer instead of old custom mixer crap.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * If the AC97 compatibility parts we needed to implement locally turn out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * to work nicely, then remove the old implementation eventually.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define AZF_USE_AC97_LAYER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #ifdef AZF_USE_AC97_LAYER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #include <sound/ac97_codec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #include "azt3328.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) MODULE_AUTHOR("Andreas Mohr <andi AT lisas.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) MODULE_DESCRIPTION("Aztech AZF3328 (PCI168)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) MODULE_SUPPORTED_DEVICE("{{Aztech,AZF3328}}");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #if IS_REACHABLE(CONFIG_GAMEPORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define SUPPORT_GAMEPORT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* === Debug settings ===
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) Further diagnostic functionality than the settings below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) does not need to be provided, since one can easily write a POSIX shell script
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) to dump the card's I/O ports (those listed in lspci -v -v):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) dump()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) local descr=$1; local addr=$2; local count=$3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) echo "${descr}: ${count} @ ${addr}:"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) dd if=/dev/port skip=`printf %d ${addr}` count=${count} bs=1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 2>/dev/null| hexdump -C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) and then use something like
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) "dump joy200 0x200 8", "dump mpu388 0x388 4", "dump joy 0xb400 8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) "dump codec00 0xa800 32", "dump mixer 0xb800 64", "dump synth 0xbc00 8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) possibly within a "while true; do ... sleep 1; done" loop.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) Tweaking ports could be done using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) VALSTRING="`printf "%02x" $value`"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) printf "\x""$VALSTRING"|dd of=/dev/port seek=`printf %d ${addr}` bs=1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 2>/dev/null
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) module_param_array(index, int, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) MODULE_PARM_DESC(index, "Index value for AZF3328 soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) module_param_array(id, charp, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) MODULE_PARM_DESC(id, "ID string for AZF3328 soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) module_param_array(enable, bool, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) MODULE_PARM_DESC(enable, "Enable AZF3328 soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static int seqtimer_scaling = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) module_param(seqtimer_scaling, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) MODULE_PARM_DESC(seqtimer_scaling, "Set 1024000Hz sequencer timer scale factor (lockup danger!). Default 128.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) enum snd_azf3328_codec_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* warning: fixed indices (also used for bitmask checks!) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) AZF_CODEC_PLAYBACK = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) AZF_CODEC_CAPTURE = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) AZF_CODEC_I2S_OUT = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct snd_azf3328_codec_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) unsigned long io_base; /* keep first! (avoid offset calc) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) unsigned int dma_base; /* helper to avoid an indirection in hotpath */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) spinlock_t *lock; /* TODO: convert to our own per-codec lock member */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) bool running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) enum snd_azf3328_codec_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct snd_azf3328 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* often-used fields towards beginning, then grouped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) unsigned long ctrl_io; /* usually 0xb000, size 128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) unsigned long game_io; /* usually 0xb400, size 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) unsigned long mpu_io; /* usually 0xb800, size 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned long opl3_io; /* usually 0xbc00, size 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) unsigned long mixer_io; /* usually 0xc000, size 64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) spinlock_t reg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct snd_timer *timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct snd_pcm *pcm[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* playback, recording and I2S out codecs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct snd_azf3328_codec_data codecs[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #ifdef AZF_USE_AC97_LAYER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct snd_ac97 *ac97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct snd_rawmidi *rmidi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #ifdef SUPPORT_GAMEPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct gameport *gameport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) u16 axes[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct pci_dev *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* register 0x6a is write-only, thus need to remember setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * If we need to add more registers here, then we might try to fold this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * into some transparent combined shadow register handling with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * CONFIG_PM register storage below, but that's slightly difficult. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) u16 shadow_reg_ctrl_6AH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* register value containers for power management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * Note: not always full I/O range preserved (similar to Win driver!) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u32 saved_regs_ctrl[AZF_ALIGN(AZF_IO_SIZE_CTRL_PM) / 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u32 saved_regs_game[AZF_ALIGN(AZF_IO_SIZE_GAME_PM) / 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u32 saved_regs_mpu[AZF_ALIGN(AZF_IO_SIZE_MPU_PM) / 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u32 saved_regs_opl3[AZF_ALIGN(AZF_IO_SIZE_OPL3_PM) / 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u32 saved_regs_mixer[AZF_ALIGN(AZF_IO_SIZE_MIXER_PM) / 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static const struct pci_device_id snd_azf3328_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) { 0x122D, 0x50DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* PCI168/3328 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) { 0x122D, 0x80DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* 3328 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) MODULE_DEVICE_TABLE(pci, snd_azf3328_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) snd_azf3328_io_reg_setb(unsigned reg, u8 mask, bool do_set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* Well, strictly spoken, the inb/outb sequence isn't atomic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) and would need locking. However we currently don't care
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) since it potentially complicates matters. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u8 prev = inb(reg), new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) new = (do_set) ? (prev|mask) : (prev & ~mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* we need to always write the new value no matter whether it differs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * or not, since some register bits don't indicate their setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) outb(new, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (new != prev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) snd_azf3328_codec_outb(const struct snd_azf3328_codec_data *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) unsigned reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) u8 value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) outb(value, codec->io_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static inline u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) snd_azf3328_codec_inb(const struct snd_azf3328_codec_data *codec, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return inb(codec->io_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) snd_azf3328_codec_outw(const struct snd_azf3328_codec_data *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) unsigned reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) u16 value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) outw(value, codec->io_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static inline u16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) snd_azf3328_codec_inw(const struct snd_azf3328_codec_data *codec, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return inw(codec->io_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) snd_azf3328_codec_outl(const struct snd_azf3328_codec_data *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) unsigned reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) u32 value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) outl(value, codec->io_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) snd_azf3328_codec_outl_multi(const struct snd_azf3328_codec_data *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) unsigned reg, const void *buffer, int count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) unsigned long addr = codec->io_base + reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) const u32 *buf = buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) outl(*buf++, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) addr += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) } while (--count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static inline u32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) snd_azf3328_codec_inl(const struct snd_azf3328_codec_data *codec, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return inl(codec->io_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) snd_azf3328_ctrl_outb(const struct snd_azf3328 *chip, unsigned reg, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) outb(value, chip->ctrl_io + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static inline u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) snd_azf3328_ctrl_inb(const struct snd_azf3328 *chip, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return inb(chip->ctrl_io + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static inline u16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) snd_azf3328_ctrl_inw(const struct snd_azf3328 *chip, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return inw(chip->ctrl_io + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) snd_azf3328_ctrl_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) outw(value, chip->ctrl_io + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) snd_azf3328_ctrl_outl(const struct snd_azf3328 *chip, unsigned reg, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) outl(value, chip->ctrl_io + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) snd_azf3328_game_outb(const struct snd_azf3328 *chip, unsigned reg, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) outb(value, chip->game_io + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) snd_azf3328_game_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) outw(value, chip->game_io + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static inline u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) snd_azf3328_game_inb(const struct snd_azf3328 *chip, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return inb(chip->game_io + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static inline u16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) snd_azf3328_game_inw(const struct snd_azf3328 *chip, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return inw(chip->game_io + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) snd_azf3328_mixer_outw(const struct snd_azf3328 *chip, unsigned reg, u16 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) outw(value, chip->mixer_io + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static inline u16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) snd_azf3328_mixer_inw(const struct snd_azf3328 *chip, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return inw(chip->mixer_io + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define AZF_MUTE_BIT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) snd_azf3328_mixer_mute_control(const struct snd_azf3328 *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) unsigned reg, bool do_mute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) unsigned long portbase = chip->mixer_io + reg + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) bool updated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* the mute bit is on the *second* (i.e. right) register of a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * left/right channel setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) updated = snd_azf3328_io_reg_setb(portbase, AZF_MUTE_BIT, do_mute);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* indicate whether it was muted before */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return (do_mute) ? !updated : updated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static inline bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) snd_azf3328_mixer_mute_control_master(const struct snd_azf3328 *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) bool do_mute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return snd_azf3328_mixer_mute_control(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) IDX_MIXER_PLAY_MASTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) do_mute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static inline bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) snd_azf3328_mixer_mute_control_pcm(const struct snd_azf3328 *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) bool do_mute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return snd_azf3328_mixer_mute_control(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) IDX_MIXER_WAVEOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) do_mute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) snd_azf3328_mixer_reset(const struct snd_azf3328 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* reset (close) mixer:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * first mute master volume, then reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) snd_azf3328_mixer_mute_control_master(chip, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #ifdef AZF_USE_AC97_LAYER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) snd_azf3328_mixer_ac97_map_unsupported(const struct snd_azf3328 *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) unsigned short reg, const char *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /* need to add some more or less clever emulation? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) dev_warn(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) "missing %s emulation for AC97 register 0x%02x!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) mode, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * Need to have _special_ AC97 mixer hardware register index mapper,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * to compensate for the issue of a rather AC97-incompatible hardware layout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define AZF_REG_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define AZF_AC97_REG_UNSUPPORTED 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define AZF_AC97_REG_REAL_IO_READ 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define AZF_AC97_REG_REAL_IO_WRITE 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define AZF_AC97_REG_REAL_IO_RW \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) (AZF_AC97_REG_REAL_IO_READ | AZF_AC97_REG_REAL_IO_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define AZF_AC97_REG_EMU_IO_READ 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define AZF_AC97_REG_EMU_IO_WRITE 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define AZF_AC97_REG_EMU_IO_RW \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) (AZF_AC97_REG_EMU_IO_READ | AZF_AC97_REG_EMU_IO_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static unsigned short
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) snd_azf3328_mixer_ac97_map_reg_idx(unsigned short reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) unsigned short azf_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) } azf_reg_mapper[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /* Especially when taking into consideration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * mono/stereo-based sequence of azf vs. AC97 control series,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * it's quite obvious that azf simply got rid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * of the AC97_HEADPHONE control at its intended offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * thus shifted _all_ controls by one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * and _then_ simply added it as an FMSYNTH control at the end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * to make up for the offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * This means we'll have to translate indices here as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * needed and then do some tiny AC97 patch action
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * (snd_ac97_rename_vol_ctl() etc.) - that's it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) { /* AC97_RESET */ IDX_MIXER_RESET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) | AZF_AC97_REG_REAL_IO_WRITE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) | AZF_AC97_REG_EMU_IO_READ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) { /* AC97_MASTER */ IDX_MIXER_PLAY_MASTER },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* note large shift: AC97_HEADPHONE to IDX_MIXER_FMSYNTH! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) { /* AC97_HEADPHONE */ IDX_MIXER_FMSYNTH },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) { /* AC97_MASTER_MONO */ IDX_MIXER_MODEMOUT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) { /* AC97_MASTER_TONE */ IDX_MIXER_BASSTREBLE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) { /* AC97_PC_BEEP */ IDX_MIXER_PCBEEP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) { /* AC97_PHONE */ IDX_MIXER_MODEMIN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) { /* AC97_MIC */ IDX_MIXER_MIC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) { /* AC97_LINE */ IDX_MIXER_LINEIN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) { /* AC97_CD */ IDX_MIXER_CDAUDIO },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) { /* AC97_VIDEO */ IDX_MIXER_VIDEO },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) { /* AC97_AUX */ IDX_MIXER_AUX },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) { /* AC97_PCM */ IDX_MIXER_WAVEOUT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) { /* AC97_REC_SEL */ IDX_MIXER_REC_SELECT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) { /* AC97_REC_GAIN */ IDX_MIXER_REC_VOLUME },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) { /* AC97_REC_GAIN_MIC */ AZF_AC97_REG_EMU_IO_RW },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) { /* AC97_GENERAL_PURPOSE */ IDX_MIXER_ADVCTL2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) { /* AC97_3D_CONTROL */ IDX_MIXER_ADVCTL1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) unsigned short reg_azf = AZF_AC97_REG_UNSUPPORTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /* azf3328 supports the low-numbered and low-spec:ed range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) of AC97 regs only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (reg <= AC97_3D_CONTROL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) unsigned short reg_idx = reg / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) reg_azf = azf_reg_mapper[reg_idx].azf_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* a translation-only entry means it's real read/write: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (!(reg_azf & ~AZF_REG_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) reg_azf |= AZF_AC97_REG_REAL_IO_RW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) case AC97_POWERDOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) reg_azf = AZF_AC97_REG_EMU_IO_RW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) case AC97_EXTENDED_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) reg_azf = AZF_AC97_REG_EMU_IO_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) case AC97_EXTENDED_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /* I don't know what the h*ll AC97 layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * would consult this _extended_ register for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * given a base-AC97-advertised card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) * but let's just emulate it anyway :-P
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) reg_azf = AZF_AC97_REG_EMU_IO_RW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) case AC97_VENDOR_ID1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) case AC97_VENDOR_ID2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) reg_azf = AZF_AC97_REG_EMU_IO_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return reg_azf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static const unsigned short
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) azf_emulated_ac97_caps =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) AC97_BC_DEDICATED_MIC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) AC97_BC_BASS_TREBLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /* Headphone is an FM Synth control here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) AC97_BC_HEADPHONE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /* no AC97_BC_LOUDNESS! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /* mask 0x7c00 is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) vendor-specific 3D enhancement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) vendor indicator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) Since there actually _is_ an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) entry for Aztech Labs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) (13), make damn sure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) to indicate it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) (13 << 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static const unsigned short
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) azf_emulated_ac97_powerdown =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /* pretend everything to be active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) AC97_PD_ADC_STATUS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) AC97_PD_DAC_STATUS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) AC97_PD_MIXER_STATUS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) AC97_PD_VREF_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * Emulated, _inofficial_ vendor ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * (there might be some devices such as the MR 2800-W
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * which could reveal the real Aztech AC97 ID).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * We choose to use "AZT" prefix, and then use 1 to indicate PCI168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * (better don't use 0x68 since there's a PCI368 as well).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static const unsigned int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) azf_emulated_ac97_vendor_id = 0x415a5401;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static unsigned short
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) snd_azf3328_mixer_ac97_read(struct snd_ac97 *ac97, unsigned short reg_ac97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) const struct snd_azf3328 *chip = ac97->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) unsigned short reg_azf = snd_azf3328_mixer_ac97_map_reg_idx(reg_ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) unsigned short reg_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) bool unsupported = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) dev_dbg(chip->card->dev, "snd_azf3328_mixer_ac97_read reg_ac97 %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) reg_ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (reg_azf & AZF_AC97_REG_UNSUPPORTED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) unsupported = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (reg_azf & AZF_AC97_REG_REAL_IO_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) reg_val = snd_azf3328_mixer_inw(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) reg_azf & AZF_REG_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * Proceed with dummy I/O read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * to ensure compatible timing where this may matter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * (ALSA AC97 layer usually doesn't call I/O functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) * due to intelligent I/O caching anyway)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * Choose a mixer register that's thoroughly unrelated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * to common audio (try to minimize distortion).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) snd_azf3328_mixer_inw(chip, IDX_MIXER_SOMETHING30H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (reg_azf & AZF_AC97_REG_EMU_IO_READ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) switch (reg_ac97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) case AC97_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) reg_val |= azf_emulated_ac97_caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) case AC97_POWERDOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) reg_val |= azf_emulated_ac97_powerdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) case AC97_EXTENDED_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) case AC97_EXTENDED_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /* AFAICS we simply can't support anything: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) reg_val |= 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) case AC97_VENDOR_ID1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) reg_val = azf_emulated_ac97_vendor_id >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) case AC97_VENDOR_ID2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) reg_val = azf_emulated_ac97_vendor_id & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) unsupported = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (unsupported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) snd_azf3328_mixer_ac97_map_unsupported(chip, reg_ac97, "read");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) return reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) snd_azf3328_mixer_ac97_write(struct snd_ac97 *ac97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) unsigned short reg_ac97, unsigned short val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) const struct snd_azf3328 *chip = ac97->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) unsigned short reg_azf = snd_azf3328_mixer_ac97_map_reg_idx(reg_ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) bool unsupported = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) "snd_azf3328_mixer_ac97_write reg_ac97 %u val %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) reg_ac97, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (reg_azf & AZF_AC97_REG_UNSUPPORTED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) unsupported = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (reg_azf & AZF_AC97_REG_REAL_IO_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) snd_azf3328_mixer_outw(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) reg_azf & AZF_REG_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (reg_azf & AZF_AC97_REG_EMU_IO_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) switch (reg_ac97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) case AC97_REC_GAIN_MIC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) case AC97_POWERDOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) case AC97_EXTENDED_STATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) * Silently swallow these writes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * Since for most registers our card doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) * actually support a comparable feature,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) * this is exactly what we should do here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) * The AC97 layer's I/O caching probably
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) * automatically takes care of all the rest...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) * (remembers written values etc.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) unsupported = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (unsupported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) snd_azf3328_mixer_ac97_map_unsupported(chip, reg_ac97, "write");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) snd_azf3328_mixer_new(struct snd_azf3328 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) struct snd_ac97_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) struct snd_ac97_template ac97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) static const struct snd_ac97_bus_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .write = snd_azf3328_mixer_ac97_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .read = snd_azf3328_mixer_ac97_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) memset(&ac97, 0, sizeof(ac97));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) ac97.scaps = AC97_SCAP_SKIP_MODEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) | AC97_SCAP_AUDIO /* we support audio! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) | AC97_SCAP_NO_SPDIF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) ac97.private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) ac97.pci = chip->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * ALSA's AC97 layer has terrible init crackling issues,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) * unfortunately, and since it makes use of AC97_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) * there's no use trying to mute Master Playback proactively.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) rc = snd_ac97_bus(chip->card, 0, &ops, NULL, &bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (!rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) rc = snd_ac97_mixer(bus, &ac97, &chip->ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) * Make sure to complain loudly in case of AC97 init failure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) * since failure may happen quite often,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * due to this card being a very quirky AC97 "lookalike".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) dev_err(chip->card->dev, "AC97 init failed, err %d!\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) /* If we return an error here, then snd_card_free() should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) * free up any ac97 codecs that got created, as well as the bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #else /* AZF_USE_AC97_LAYER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) snd_azf3328_mixer_write_volume_gradually(const struct snd_azf3328 *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) unsigned reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) unsigned char dst_vol_left,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) unsigned char dst_vol_right,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) int chan_sel, int delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) unsigned long portbase = chip->mixer_io + reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) unsigned char curr_vol_left = 0, curr_vol_right = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) int left_change = 0, right_change = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (chan_sel & SET_CHAN_LEFT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) curr_vol_left = inb(portbase + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /* take care of muting flag contained in left channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (curr_vol_left & AZF_MUTE_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) dst_vol_left |= AZF_MUTE_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) dst_vol_left &= ~AZF_MUTE_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) left_change = (curr_vol_left > dst_vol_left) ? -1 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (chan_sel & SET_CHAN_RIGHT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) curr_vol_right = inb(portbase + 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) right_change = (curr_vol_right > dst_vol_right) ? -1 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (left_change) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (curr_vol_left != dst_vol_left) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) curr_vol_left += left_change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) outb(curr_vol_left, portbase + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) left_change = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) if (right_change) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (curr_vol_right != dst_vol_right) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) curr_vol_right += right_change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) /* during volume change, the right channel is crackling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) * somewhat more than the left channel, unfortunately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) * This seems to be a hardware issue. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) outb(curr_vol_right, portbase + 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) right_change = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) if (delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) mdelay(delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) } while ((left_change) || (right_change));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) * general mixer element
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) struct azf3328_mixer_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) unsigned reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) unsigned int lchan_shift, rchan_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) unsigned int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) unsigned int invert: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) unsigned int stereo: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) unsigned int enum_c: 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #define COMPOSE_MIXER_REG(reg,lchan_shift,rchan_shift,mask,invert,stereo,enum_c) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) ((reg) | (lchan_shift << 8) | (rchan_shift << 12) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) (mask << 16) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) (invert << 24) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) (stereo << 25) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) (enum_c << 26))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) static void snd_azf3328_mixer_reg_decode(struct azf3328_mixer_reg *r, unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) r->reg = val & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) r->lchan_shift = (val >> 8) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) r->rchan_shift = (val >> 12) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) r->mask = (val >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) r->invert = (val >> 24) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) r->stereo = (val >> 25) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) r->enum_c = (val >> 26) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) * mixer switches/volumes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #define AZF3328_MIXER_SWITCH(xname, reg, shift, invert) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .info = snd_azf3328_info_mixer, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0x1, invert, 0, 0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #define AZF3328_MIXER_VOL_STEREO(xname, reg, mask, invert) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .info = snd_azf3328_info_mixer, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .private_value = COMPOSE_MIXER_REG(reg, 8, 0, mask, invert, 1, 0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) #define AZF3328_MIXER_VOL_MONO(xname, reg, mask, is_right_chan) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .info = snd_azf3328_info_mixer, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .private_value = COMPOSE_MIXER_REG(reg, is_right_chan ? 0 : 8, 0, mask, 1, 0, 0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) #define AZF3328_MIXER_VOL_SPECIAL(xname, reg, mask, shift, invert) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .info = snd_azf3328_info_mixer, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .private_value = COMPOSE_MIXER_REG(reg, shift, 0, mask, invert, 0, 0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) #define AZF3328_MIXER_ENUM(xname, reg, enum_c, shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .info = snd_azf3328_info_mixer_enum, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .get = snd_azf3328_get_mixer_enum, .put = snd_azf3328_put_mixer_enum, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0, 0, 0, enum_c), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) snd_azf3328_info_mixer(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) struct azf3328_mixer_reg reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) snd_azf3328_mixer_reg_decode(®, kcontrol->private_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) uinfo->type = reg.mask == 1 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) uinfo->count = reg.stereo + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) uinfo->value.integer.max = reg.mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) snd_azf3328_get_mixer(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) struct azf3328_mixer_reg reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) u16 oreg, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) snd_azf3328_mixer_reg_decode(®, kcontrol->private_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) oreg = snd_azf3328_mixer_inw(chip, reg.reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) val = (oreg >> reg.lchan_shift) & reg.mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) if (reg.invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) val = reg.mask - val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) ucontrol->value.integer.value[0] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) if (reg.stereo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) val = (oreg >> reg.rchan_shift) & reg.mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (reg.invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) val = reg.mask - val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) ucontrol->value.integer.value[1] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) "get: %02x is %04x -> vol %02lx|%02lx (shift %02d|%02d, mask %02x, inv. %d, stereo %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) reg.reg, oreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) ucontrol->value.integer.value[0], ucontrol->value.integer.value[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) reg.lchan_shift, reg.rchan_shift, reg.mask, reg.invert, reg.stereo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) snd_azf3328_put_mixer(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) struct azf3328_mixer_reg reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) u16 oreg, nreg, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) snd_azf3328_mixer_reg_decode(®, kcontrol->private_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) oreg = snd_azf3328_mixer_inw(chip, reg.reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) val = ucontrol->value.integer.value[0] & reg.mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) if (reg.invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) val = reg.mask - val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) nreg = oreg & ~(reg.mask << reg.lchan_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) nreg |= (val << reg.lchan_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) if (reg.stereo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) val = ucontrol->value.integer.value[1] & reg.mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) if (reg.invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) val = reg.mask - val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) nreg &= ~(reg.mask << reg.rchan_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) nreg |= (val << reg.rchan_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) if (reg.mask >= 0x07) /* it's a volume control, so better take care */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) snd_azf3328_mixer_write_volume_gradually(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) chip, reg.reg, nreg >> 8, nreg & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) /* just set both channels, doesn't matter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) SET_CHAN_LEFT|SET_CHAN_RIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) snd_azf3328_mixer_outw(chip, reg.reg, nreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) "put: %02x to %02lx|%02lx, oreg %04x; shift %02d|%02d -> nreg %04x; after: %04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) reg.reg, ucontrol->value.integer.value[0], ucontrol->value.integer.value[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) oreg, reg.lchan_shift, reg.rchan_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) nreg, snd_azf3328_mixer_inw(chip, reg.reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) return (nreg != oreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) snd_azf3328_info_mixer_enum(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) static const char * const texts1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) "Mic1", "Mic2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) static const char * const texts2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) "Mix", "Mic"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) static const char * const texts3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) "Mic", "CD", "Video", "Aux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) "Line", "Mix", "Mix Mono", "Phone"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) static const char * const texts4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) "pre 3D", "post 3D"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) struct azf3328_mixer_reg reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) const char * const *p = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) snd_azf3328_mixer_reg_decode(®, kcontrol->private_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (reg.reg == IDX_MIXER_ADVCTL2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) switch(reg.lchan_shift) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) case 8: /* modem out sel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) p = texts1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) case 9: /* mono sel source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) p = texts2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) case 15: /* PCM Out Path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) p = texts4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) } else if (reg.reg == IDX_MIXER_REC_SELECT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) p = texts3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) return snd_ctl_enum_info(uinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) (reg.reg == IDX_MIXER_REC_SELECT) ? 2 : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) reg.enum_c, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) snd_azf3328_get_mixer_enum(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) struct azf3328_mixer_reg reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) unsigned short val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) snd_azf3328_mixer_reg_decode(®, kcontrol->private_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) val = snd_azf3328_mixer_inw(chip, reg.reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (reg.reg == IDX_MIXER_REC_SELECT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) ucontrol->value.enumerated.item[0] = (val >> 8) & (reg.enum_c - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) ucontrol->value.enumerated.item[1] = (val >> 0) & (reg.enum_c - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) ucontrol->value.enumerated.item[0] = (val >> reg.lchan_shift) & (reg.enum_c - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) "get_enum: %02x is %04x -> %d|%d (shift %02d, enum_c %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) reg.reg, val, ucontrol->value.enumerated.item[0], ucontrol->value.enumerated.item[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) reg.lchan_shift, reg.enum_c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) snd_azf3328_put_mixer_enum(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) struct azf3328_mixer_reg reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) u16 oreg, nreg, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) snd_azf3328_mixer_reg_decode(®, kcontrol->private_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) oreg = snd_azf3328_mixer_inw(chip, reg.reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) val = oreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) if (reg.reg == IDX_MIXER_REC_SELECT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) ucontrol->value.enumerated.item[1] > reg.enum_c - 1U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) val = (ucontrol->value.enumerated.item[0] << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) (ucontrol->value.enumerated.item[1] << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) val &= ~((reg.enum_c - 1) << reg.lchan_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) val |= (ucontrol->value.enumerated.item[0] << reg.lchan_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) snd_azf3328_mixer_outw(chip, reg.reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) nreg = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) "put_enum: %02x to %04x, oreg %04x\n", reg.reg, val, oreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) return (nreg != oreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) static const struct snd_kcontrol_new snd_azf3328_mixer_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) AZF3328_MIXER_SWITCH("Master Playback Switch", IDX_MIXER_PLAY_MASTER, 15, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) AZF3328_MIXER_VOL_STEREO("Master Playback Volume", IDX_MIXER_PLAY_MASTER, 0x1f, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) AZF3328_MIXER_SWITCH("PCM Playback Switch", IDX_MIXER_WAVEOUT, 15, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) AZF3328_MIXER_VOL_STEREO("PCM Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) IDX_MIXER_WAVEOUT, 0x1f, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) AZF3328_MIXER_SWITCH("PCM 3D Bypass Playback Switch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) IDX_MIXER_ADVCTL2, 7, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) AZF3328_MIXER_SWITCH("FM Playback Switch", IDX_MIXER_FMSYNTH, 15, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) AZF3328_MIXER_VOL_STEREO("FM Playback Volume", IDX_MIXER_FMSYNTH, 0x1f, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) AZF3328_MIXER_SWITCH("CD Playback Switch", IDX_MIXER_CDAUDIO, 15, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) AZF3328_MIXER_VOL_STEREO("CD Playback Volume", IDX_MIXER_CDAUDIO, 0x1f, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) AZF3328_MIXER_SWITCH("Capture Switch", IDX_MIXER_REC_VOLUME, 15, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) AZF3328_MIXER_VOL_STEREO("Capture Volume", IDX_MIXER_REC_VOLUME, 0x0f, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) AZF3328_MIXER_ENUM("Capture Source", IDX_MIXER_REC_SELECT, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) AZF3328_MIXER_SWITCH("Mic Playback Switch", IDX_MIXER_MIC, 15, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) AZF3328_MIXER_VOL_MONO("Mic Playback Volume", IDX_MIXER_MIC, 0x1f, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) AZF3328_MIXER_SWITCH("Mic Boost (+20dB)", IDX_MIXER_MIC, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) AZF3328_MIXER_SWITCH("Line Playback Switch", IDX_MIXER_LINEIN, 15, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) AZF3328_MIXER_VOL_STEREO("Line Playback Volume", IDX_MIXER_LINEIN, 0x1f, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) AZF3328_MIXER_SWITCH("Beep Playback Switch", IDX_MIXER_PCBEEP, 15, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) AZF3328_MIXER_VOL_SPECIAL("Beep Playback Volume", IDX_MIXER_PCBEEP, 0x0f, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) AZF3328_MIXER_SWITCH("Video Playback Switch", IDX_MIXER_VIDEO, 15, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) AZF3328_MIXER_VOL_STEREO("Video Playback Volume", IDX_MIXER_VIDEO, 0x1f, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) AZF3328_MIXER_SWITCH("Aux Playback Switch", IDX_MIXER_AUX, 15, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) AZF3328_MIXER_VOL_STEREO("Aux Playback Volume", IDX_MIXER_AUX, 0x1f, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) AZF3328_MIXER_SWITCH("Modem Playback Switch", IDX_MIXER_MODEMOUT, 15, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) AZF3328_MIXER_VOL_MONO("Modem Playback Volume", IDX_MIXER_MODEMOUT, 0x1f, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) AZF3328_MIXER_SWITCH("Modem Capture Switch", IDX_MIXER_MODEMIN, 15, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) AZF3328_MIXER_VOL_MONO("Modem Capture Volume", IDX_MIXER_MODEMIN, 0x1f, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) AZF3328_MIXER_ENUM("Mic Select", IDX_MIXER_ADVCTL2, 2, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) AZF3328_MIXER_ENUM("Mono Output Select", IDX_MIXER_ADVCTL2, 2, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) AZF3328_MIXER_ENUM("PCM Output Route", IDX_MIXER_ADVCTL2, 2, 15), /* PCM Out Path, place in front since it controls *both* 3D and Bass/Treble! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) AZF3328_MIXER_VOL_SPECIAL("Tone Control - Treble", IDX_MIXER_BASSTREBLE, 0x07, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) AZF3328_MIXER_VOL_SPECIAL("Tone Control - Bass", IDX_MIXER_BASSTREBLE, 0x07, 9, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) AZF3328_MIXER_SWITCH("3D Control - Switch", IDX_MIXER_ADVCTL2, 13, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) AZF3328_MIXER_VOL_SPECIAL("3D Control - Width", IDX_MIXER_ADVCTL1, 0x07, 1, 0), /* "3D Width" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) AZF3328_MIXER_VOL_SPECIAL("3D Control - Depth", IDX_MIXER_ADVCTL1, 0x03, 8, 0), /* "Hifi 3D" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) #if MIXER_TESTING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) AZF3328_MIXER_SWITCH("0", IDX_MIXER_ADVCTL2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) AZF3328_MIXER_SWITCH("1", IDX_MIXER_ADVCTL2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) AZF3328_MIXER_SWITCH("2", IDX_MIXER_ADVCTL2, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) AZF3328_MIXER_SWITCH("3", IDX_MIXER_ADVCTL2, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) AZF3328_MIXER_SWITCH("4", IDX_MIXER_ADVCTL2, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) AZF3328_MIXER_SWITCH("5", IDX_MIXER_ADVCTL2, 5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) AZF3328_MIXER_SWITCH("6", IDX_MIXER_ADVCTL2, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) AZF3328_MIXER_SWITCH("7", IDX_MIXER_ADVCTL2, 7, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) AZF3328_MIXER_SWITCH("8", IDX_MIXER_ADVCTL2, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) AZF3328_MIXER_SWITCH("9", IDX_MIXER_ADVCTL2, 9, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) AZF3328_MIXER_SWITCH("10", IDX_MIXER_ADVCTL2, 10, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) AZF3328_MIXER_SWITCH("11", IDX_MIXER_ADVCTL2, 11, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) AZF3328_MIXER_SWITCH("12", IDX_MIXER_ADVCTL2, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) AZF3328_MIXER_SWITCH("13", IDX_MIXER_ADVCTL2, 13, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) AZF3328_MIXER_SWITCH("14", IDX_MIXER_ADVCTL2, 14, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) AZF3328_MIXER_SWITCH("15", IDX_MIXER_ADVCTL2, 15, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) static const u16 snd_azf3328_init_values[][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) { IDX_MIXER_PLAY_MASTER, MIXER_MUTE_MASK|0x1f1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) { IDX_MIXER_MODEMOUT, MIXER_MUTE_MASK|0x1f1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) { IDX_MIXER_BASSTREBLE, 0x0000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) { IDX_MIXER_PCBEEP, MIXER_MUTE_MASK|0x1f1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) { IDX_MIXER_MODEMIN, MIXER_MUTE_MASK|0x1f1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) { IDX_MIXER_MIC, MIXER_MUTE_MASK|0x001f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) { IDX_MIXER_LINEIN, MIXER_MUTE_MASK|0x1f1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) { IDX_MIXER_CDAUDIO, MIXER_MUTE_MASK|0x1f1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) { IDX_MIXER_VIDEO, MIXER_MUTE_MASK|0x1f1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) { IDX_MIXER_AUX, MIXER_MUTE_MASK|0x1f1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) { IDX_MIXER_WAVEOUT, MIXER_MUTE_MASK|0x1f1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) { IDX_MIXER_FMSYNTH, MIXER_MUTE_MASK|0x1f1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) { IDX_MIXER_REC_VOLUME, MIXER_MUTE_MASK|0x0707 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) snd_azf3328_mixer_new(struct snd_azf3328 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) const struct snd_kcontrol_new *sw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) if (snd_BUG_ON(!chip || !chip->card))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) card = chip->card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) /* mixer reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) /* mute and zero volume channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) for (idx = 0; idx < ARRAY_SIZE(snd_azf3328_init_values); ++idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) snd_azf3328_mixer_outw(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) snd_azf3328_init_values[idx][0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) snd_azf3328_init_values[idx][1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) /* add mixer controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) sw = snd_azf3328_mixer_controls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) for (idx = 0; idx < ARRAY_SIZE(snd_azf3328_mixer_controls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) ++idx, ++sw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) if ((err = snd_ctl_add(chip->card, snd_ctl_new1(sw, chip))) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) snd_component_add(card, "AZF3328 mixer");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) strcpy(card->mixername, "AZF3328 mixer");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) #endif /* AZF_USE_AC97_LAYER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) snd_azf3328_codec_setfmt(struct snd_azf3328_codec_data *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) enum azf_freq_t bitrate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) unsigned int format_width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) unsigned int channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) u16 val = 0xff00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) u8 freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) switch (bitrate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) case AZF_FREQ_4000: freq = SOUNDFORMAT_FREQ_SUSPECTED_4000; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) case AZF_FREQ_4800: freq = SOUNDFORMAT_FREQ_SUSPECTED_4800; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) case AZF_FREQ_5512:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) /* the AZF3328 names it "5510" for some strange reason */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) freq = SOUNDFORMAT_FREQ_5510; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) case AZF_FREQ_6620: freq = SOUNDFORMAT_FREQ_6620; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) case AZF_FREQ_8000: freq = SOUNDFORMAT_FREQ_8000; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) case AZF_FREQ_9600: freq = SOUNDFORMAT_FREQ_9600; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) case AZF_FREQ_11025: freq = SOUNDFORMAT_FREQ_11025; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) case AZF_FREQ_13240: freq = SOUNDFORMAT_FREQ_SUSPECTED_13240; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) case AZF_FREQ_16000: freq = SOUNDFORMAT_FREQ_16000; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) case AZF_FREQ_22050: freq = SOUNDFORMAT_FREQ_22050; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) case AZF_FREQ_32000: freq = SOUNDFORMAT_FREQ_32000; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) snd_printk(KERN_WARNING "unknown bitrate %d, assuming 44.1kHz!\n", bitrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) case AZF_FREQ_44100: freq = SOUNDFORMAT_FREQ_44100; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) case AZF_FREQ_48000: freq = SOUNDFORMAT_FREQ_48000; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) case AZF_FREQ_66200: freq = SOUNDFORMAT_FREQ_SUSPECTED_66200; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) /* val = 0xff07; 3m27.993s (65301Hz; -> 64000Hz???) hmm, 66120, 65967, 66123 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) /* val = 0xff09; 17m15.098s (13123,478Hz; -> 12000Hz???) hmm, 13237.2Hz? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) /* val = 0xff0a; 47m30.599s (4764,891Hz; -> 4800Hz???) yup, 4803Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) /* val = 0xff0c; 57m0.510s (4010,263Hz; -> 4000Hz???) yup, 4003Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) /* val = 0xff05; 5m11.556s (... -> 44100Hz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) /* val = 0xff03; 10m21.529s (21872,463Hz; -> 22050Hz???) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) /* val = 0xff0f; 20m41.883s (10937,993Hz; -> 11025Hz???) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) /* val = 0xff0d; 41m23.135s (5523,600Hz; -> 5512Hz???) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) /* val = 0xff0e; 28m30.777s (8017Hz; -> 8000Hz???) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) val |= freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) if (channels == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) val |= SOUNDFORMAT_FLAG_2CHANNELS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) if (format_width == 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) val |= SOUNDFORMAT_FLAG_16BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) spin_lock_irqsave(codec->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) /* set bitrate/format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) snd_azf3328_codec_outw(codec, IDX_IO_CODEC_SOUNDFORMAT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) /* changing the bitrate/format settings switches off the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) * audio output with an annoying click in case of 8/16bit format change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) * (maybe shutting down DAC/ADC?), thus immediately
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) * do some tweaking to reenable it and get rid of the clicking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) * (FIXME: yes, it works, but what exactly am I doing here?? :)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) * FIXME: does this have some side effects for full-duplex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) * or other dramatic side effects? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) /* do it for non-capture codecs only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) if (codec->type != AZF_CODEC_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) snd_azf3328_codec_inw(codec, IDX_IO_CODEC_DMA_FLAGS) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) DMA_RUN_SOMETHING1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) DMA_RUN_SOMETHING2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) SOMETHING_ALMOST_ALWAYS_SET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) DMA_EPILOGUE_SOMETHING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) DMA_SOMETHING_ELSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) spin_unlock_irqrestore(codec->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) snd_azf3328_codec_setfmt_lowpower(struct snd_azf3328_codec_data *codec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) /* choose lowest frequency for low power consumption.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) * While this will cause louder noise due to rather coarse frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) * it should never matter since output should always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) * get disabled properly when idle anyway. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) snd_azf3328_codec_setfmt(codec, AZF_FREQ_4000, 8, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) snd_azf3328_ctrl_reg_6AH_update(struct snd_azf3328 *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) unsigned bitmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) bool enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) bool do_mask = !enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) if (do_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) chip->shadow_reg_ctrl_6AH |= bitmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) chip->shadow_reg_ctrl_6AH &= ~bitmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) "6AH_update mask 0x%04x do_mask %d: val 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) bitmask, do_mask, chip->shadow_reg_ctrl_6AH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) snd_azf3328_ctrl_outw(chip, IDX_IO_6AH, chip->shadow_reg_ctrl_6AH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) snd_azf3328_ctrl_enable_codecs(struct snd_azf3328 *chip, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) dev_dbg(chip->card->dev, "codec_enable %d\n", enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) /* no idea what exactly is being done here, but I strongly assume it's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) * PM related */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) snd_azf3328_ctrl_reg_6AH_update(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) chip, IO_6A_PAUSE_PLAYBACK_BIT8, enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) snd_azf3328_ctrl_codec_activity(struct snd_azf3328 *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) enum snd_azf3328_codec_type codec_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) bool enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) struct snd_azf3328_codec_data *codec = &chip->codecs[codec_type];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) bool need_change = (codec->running != enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) "codec_activity: %s codec, enable %d, need_change %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) codec->name, enable, need_change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) if (need_change) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) enum snd_azf3328_codec_type other1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) enum snd_azf3328_codec_type other2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) } peer_codecs[3] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) { { AZF_CODEC_CAPTURE, AZF_CODEC_I2S_OUT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) { AZF_CODEC_PLAYBACK, AZF_CODEC_I2S_OUT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) { AZF_CODEC_PLAYBACK, AZF_CODEC_CAPTURE } };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) bool call_function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) /* if enable codec, call enable_codecs func
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) to enable codec supply... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) call_function = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) /* ...otherwise call enable_codecs func
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) (which globally shuts down operation of codecs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) only in case the other codecs are currently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) not active either! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) call_function =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) ((!chip->codecs[peer_codecs[codec_type].other1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) && (!chip->codecs[peer_codecs[codec_type].other2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) .running));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) if (call_function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) snd_azf3328_ctrl_enable_codecs(chip, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) /* ...and adjust clock, too
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) * (reduce noise and power consumption) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) if (!enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) snd_azf3328_codec_setfmt_lowpower(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) codec->running = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) snd_azf3328_codec_setdmaa(struct snd_azf3328 *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) struct snd_azf3328_codec_data *codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) unsigned long addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) unsigned int period_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) unsigned int buffer_bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) WARN_ONCE(period_bytes & 1, "odd period length!?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) WARN_ONCE(buffer_bytes != 2 * period_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) "missed our input expectations! %u vs. %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) buffer_bytes, period_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) if (!codec->running) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) /* AZF3328 uses a two buffer pointer DMA transfer approach */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) /* width 32bit (prevent overflow): */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) u32 area_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) struct codec_setup_io {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) u32 dma_start_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) u32 dma_start_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) u32 dma_lengths;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) } __attribute__((packed)) setup_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) area_length = buffer_bytes/2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) setup_io.dma_start_1 = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) setup_io.dma_start_2 = addr+area_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) "setdma: buffers %08x[%u] / %08x[%u], %u, %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) setup_io.dma_start_1, area_length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) setup_io.dma_start_2, area_length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) period_bytes, buffer_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) /* Hmm, are we really supposed to decrement this by 1??
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) Most definitely certainly not: configuring full length does
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) work properly (i.e. likely better), and BTW we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) violated possibly differing frame sizes with this...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) area_length--; |* max. index *|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) /* build combined I/O buffer length word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) setup_io.dma_lengths = (area_length << 16) | (area_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) spin_lock_irqsave(codec->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) snd_azf3328_codec_outl_multi(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) codec, IDX_IO_CODEC_DMA_START_1, &setup_io, 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) spin_unlock_irqrestore(codec->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) snd_azf3328_pcm_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) struct snd_azf3328_codec_data *codec = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) unsigned int size = snd_pcm_lib_buffer_bytes(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) unsigned int count = snd_pcm_lib_period_bytes(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) codec->dma_base = runtime->dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) snd_azf3328_codec_setfmt(codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) runtime->rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) snd_pcm_format_width(runtime->format),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) runtime->channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) snd_azf3328_codec_setdmaa(chip, codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) runtime->dma_addr, count, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) snd_azf3328_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) struct snd_azf3328_codec_data *codec = runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) int result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) u16 flags1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) bool previously_muted = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) bool is_main_mixer_playback_codec = (AZF_CODEC_PLAYBACK == codec->type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) dev_dbg(chip->card->dev, "START PCM %s\n", codec->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) if (is_main_mixer_playback_codec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) /* mute WaveOut (avoid clicking during setup) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) previously_muted =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) snd_azf3328_mixer_mute_control_pcm(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) chip, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) snd_azf3328_codec_setfmt(codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) runtime->rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) snd_pcm_format_width(runtime->format),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) runtime->channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) spin_lock(codec->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) /* first, remember current value: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) flags1 = snd_azf3328_codec_inw(codec, IDX_IO_CODEC_DMA_FLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) /* stop transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) flags1 &= ~DMA_RESUME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) /* FIXME: clear interrupts or what??? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) snd_azf3328_codec_outw(codec, IDX_IO_CODEC_IRQTYPE, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) spin_unlock(codec->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) snd_azf3328_codec_setdmaa(chip, codec, runtime->dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) snd_pcm_lib_period_bytes(substream),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) snd_pcm_lib_buffer_bytes(substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) spin_lock(codec->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) #ifdef WIN9X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) /* FIXME: enable playback/recording??? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) flags1 |= DMA_RUN_SOMETHING1 | DMA_RUN_SOMETHING2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) /* start transfer again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) /* FIXME: what is this value (0x0010)??? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) flags1 |= DMA_RESUME | DMA_EPILOGUE_SOMETHING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) #else /* NT4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) DMA_RUN_SOMETHING1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) DMA_RUN_SOMETHING1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) DMA_RUN_SOMETHING2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) DMA_RESUME |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) SOMETHING_ALMOST_ALWAYS_SET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) DMA_EPILOGUE_SOMETHING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) DMA_SOMETHING_ELSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) spin_unlock(codec->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) snd_azf3328_ctrl_codec_activity(chip, codec->type, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) if (is_main_mixer_playback_codec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) /* now unmute WaveOut */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) if (!previously_muted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) snd_azf3328_mixer_mute_control_pcm(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) chip, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) dev_dbg(chip->card->dev, "PCM STARTED %s\n", codec->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) dev_dbg(chip->card->dev, "PCM RESUME %s\n", codec->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) /* resume codec if we were active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) spin_lock(codec->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) if (codec->running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) snd_azf3328_codec_inw(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) codec, IDX_IO_CODEC_DMA_FLAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) ) | DMA_RESUME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) spin_unlock(codec->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) dev_dbg(chip->card->dev, "PCM STOP %s\n", codec->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) if (is_main_mixer_playback_codec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) /* mute WaveOut (avoid clicking during setup) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) previously_muted =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) snd_azf3328_mixer_mute_control_pcm(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) chip, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) spin_lock(codec->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) /* first, remember current value: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) flags1 = snd_azf3328_codec_inw(codec, IDX_IO_CODEC_DMA_FLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) /* stop transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) flags1 &= ~DMA_RESUME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) /* hmm, is this really required? we're resetting the same bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) * immediately thereafter... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) flags1 |= DMA_RUN_SOMETHING1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) flags1 &= ~DMA_RUN_SOMETHING1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS, flags1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) spin_unlock(codec->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) snd_azf3328_ctrl_codec_activity(chip, codec->type, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) if (is_main_mixer_playback_codec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) /* now unmute WaveOut */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) if (!previously_muted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) snd_azf3328_mixer_mute_control_pcm(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) chip, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) dev_dbg(chip->card->dev, "PCM STOPPED %s\n", codec->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) dev_dbg(chip->card->dev, "PCM SUSPEND %s\n", codec->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) /* make sure codec is stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) snd_azf3328_codec_outw(codec, IDX_IO_CODEC_DMA_FLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) snd_azf3328_codec_inw(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) codec, IDX_IO_CODEC_DMA_FLAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) ) & ~DMA_RESUME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) WARN(1, "FIXME: SNDRV_PCM_TRIGGER_PAUSE_PUSH NIY!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) WARN(1, "FIXME: SNDRV_PCM_TRIGGER_PAUSE_RELEASE NIY!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) WARN(1, "FIXME: unknown trigger mode!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) static snd_pcm_uframes_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) snd_azf3328_pcm_pointer(struct snd_pcm_substream *substream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) const struct snd_azf3328_codec_data *codec =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) unsigned long result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) snd_pcm_uframes_t frmres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) result = snd_azf3328_codec_inl(codec, IDX_IO_CODEC_DMA_CURRPOS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) /* calculate offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) #ifdef QUERY_HARDWARE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) result -= snd_azf3328_codec_inl(codec, IDX_IO_CODEC_DMA_START_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) result -= codec->dma_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) frmres = bytes_to_frames( substream->runtime, result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) dev_dbg(substream->pcm->card->dev, "%08li %s @ 0x%8lx, frames %8ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) jiffies, codec->name, result, frmres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) return frmres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) /******************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) #ifdef SUPPORT_GAMEPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) snd_azf3328_gameport_irq_enable(struct snd_azf3328 *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) bool enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) snd_azf3328_io_reg_setb(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) chip->game_io+IDX_GAME_HWCONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) GAME_HWCFG_IRQ_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) snd_azf3328_gameport_legacy_address_enable(struct snd_azf3328 *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) bool enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) snd_azf3328_io_reg_setb(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) chip->game_io+IDX_GAME_HWCONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) GAME_HWCFG_LEGACY_ADDRESS_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) snd_azf3328_gameport_set_counter_frequency(struct snd_azf3328 *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) unsigned int freq_cfg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) snd_azf3328_io_reg_setb(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) chip->game_io+IDX_GAME_HWCONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) (freq_cfg & 1) != 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) snd_azf3328_io_reg_setb(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) chip->game_io+IDX_GAME_HWCONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) (freq_cfg & 2) != 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) snd_azf3328_gameport_axis_circuit_enable(struct snd_azf3328 *chip, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) snd_azf3328_ctrl_reg_6AH_update(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) chip, IO_6A_SOMETHING2_GAMEPORT, enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) snd_azf3328_gameport_interrupt(struct snd_azf3328 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) * skeleton handler only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) * (we do not want axis reading in interrupt handler - too much load!)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) dev_dbg(chip->card->dev, "gameport irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) /* this should ACK the gameport IRQ properly, hopefully. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) snd_azf3328_game_inw(chip, IDX_GAME_AXIS_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) snd_azf3328_gameport_open(struct gameport *gameport, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) struct snd_azf3328 *chip = gameport_get_port_data(gameport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) dev_dbg(chip->card->dev, "gameport_open, mode %d\n", mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) case GAMEPORT_MODE_COOKED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) case GAMEPORT_MODE_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) res = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) snd_azf3328_gameport_set_counter_frequency(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) GAME_HWCFG_ADC_COUNTER_FREQ_STD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) snd_azf3328_gameport_axis_circuit_enable(chip, (res == 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) snd_azf3328_gameport_close(struct gameport *gameport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) struct snd_azf3328 *chip = gameport_get_port_data(gameport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) dev_dbg(chip->card->dev, "gameport_close\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) snd_azf3328_gameport_set_counter_frequency(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) GAME_HWCFG_ADC_COUNTER_FREQ_1_200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) snd_azf3328_gameport_axis_circuit_enable(chip, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) snd_azf3328_gameport_cooked_read(struct gameport *gameport,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) int *axes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) int *buttons
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) struct snd_azf3328 *chip = gameport_get_port_data(gameport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) if (snd_BUG_ON(!chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) val = snd_azf3328_game_inb(chip, IDX_GAME_LEGACY_COMPATIBLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) *buttons = (~(val) >> 4) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) /* ok, this one is a bit dirty: cooked_read is being polled by a timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) * thus we're atomic and cannot actively wait in here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) * (which would be useful for us since it probably would be better
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) * to trigger a measurement in here, then wait a short amount of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) * time until it's finished, then read values of _this_ measurement).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) * Thus we simply resort to reading values if they're available already
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) * and trigger the next measurement.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) val = snd_azf3328_game_inb(chip, IDX_GAME_AXES_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) if (val & GAME_AXES_SAMPLING_READY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) for (i = 0; i < ARRAY_SIZE(chip->axes); ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) /* configure the axis to read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) val = (i << 4) | 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) snd_azf3328_game_outb(chip, IDX_GAME_AXES_CONFIG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) chip->axes[i] = snd_azf3328_game_inw(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) chip, IDX_GAME_AXIS_VALUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) /* trigger next sampling of axes, to be evaluated the next time we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) * enter this function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) /* for some very, very strange reason we cannot enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) * Measurement Ready monitoring for all axes here,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) * at least not when only one joystick connected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) val = 0x03; /* we're able to monitor axes 1 and 2 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) snd_azf3328_game_outb(chip, IDX_GAME_AXES_CONFIG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) snd_azf3328_game_outw(chip, IDX_GAME_AXIS_VALUE, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) for (i = 0; i < ARRAY_SIZE(chip->axes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) axes[i] = chip->axes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) if (axes[i] == 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) axes[i] = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) dev_dbg(chip->card->dev, "cooked_read: axes %d %d %d %d buttons %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) axes[0], axes[1], axes[2], axes[3], *buttons);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) snd_azf3328_gameport(struct snd_azf3328 *chip, int dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) struct gameport *gp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) chip->gameport = gp = gameport_allocate_port();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) if (!gp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) dev_err(chip->card->dev, "cannot alloc memory for gameport\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) gameport_set_name(gp, "AZF3328 Gameport");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) gameport_set_dev_parent(gp, &chip->pci->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) gp->io = chip->game_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) gameport_set_port_data(gp, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) gp->open = snd_azf3328_gameport_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) gp->close = snd_azf3328_gameport_close;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) gp->fuzz = 16; /* seems ok */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) gp->cooked_read = snd_azf3328_gameport_cooked_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) /* DISABLE legacy address: we don't need it! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) snd_azf3328_gameport_legacy_address_enable(chip, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) snd_azf3328_gameport_set_counter_frequency(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) GAME_HWCFG_ADC_COUNTER_FREQ_1_200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) snd_azf3328_gameport_axis_circuit_enable(chip, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) gameport_register_port(chip->gameport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) snd_azf3328_gameport_free(struct snd_azf3328 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) if (chip->gameport) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) gameport_unregister_port(chip->gameport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) chip->gameport = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) snd_azf3328_gameport_irq_enable(chip, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) snd_azf3328_gameport(struct snd_azf3328 *chip, int dev) { return -ENOSYS; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) snd_azf3328_gameport_free(struct snd_azf3328 *chip) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) snd_azf3328_gameport_interrupt(struct snd_azf3328 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) dev_warn(chip->card->dev, "huh, game port IRQ occurred!?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) #endif /* SUPPORT_GAMEPORT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) /******************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) snd_azf3328_irq_log_unknown_type(struct snd_azf3328 *chip, u8 which)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) "unknown IRQ type (%x) occurred, please report!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) which);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) snd_azf3328_pcm_interrupt(struct snd_azf3328 *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) const struct snd_azf3328_codec_data *first_codec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) u8 status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) u8 which;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) enum snd_azf3328_codec_type codec_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) const struct snd_azf3328_codec_data *codec = first_codec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) for (codec_type = AZF_CODEC_PLAYBACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) codec_type <= AZF_CODEC_I2S_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) ++codec_type, ++codec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) /* skip codec if there's no interrupt for it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) if (!(status & (1 << codec_type)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) spin_lock(codec->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) which = snd_azf3328_codec_inb(codec, IDX_IO_CODEC_IRQTYPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) /* ack all IRQ types immediately */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) snd_azf3328_codec_outb(codec, IDX_IO_CODEC_IRQTYPE, which);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) spin_unlock(codec->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) if (codec->substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) snd_pcm_period_elapsed(codec->substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) dev_dbg(chip->card->dev, "%s period done (#%x), @ %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) codec->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) which,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) snd_azf3328_codec_inl(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) codec, IDX_IO_CODEC_DMA_CURRPOS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) dev_warn(chip->card->dev, "irq handler problem!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) if (which & IRQ_SOMETHING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) snd_azf3328_irq_log_unknown_type(chip, which);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) snd_azf3328_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) struct snd_azf3328 *chip = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) static unsigned long irq_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) status = snd_azf3328_ctrl_inb(chip, IDX_IO_IRQSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) /* fast path out, to ease interrupt sharing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) if (!(status &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) (IRQ_PLAYBACK|IRQ_RECORDING|IRQ_I2S_OUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) |IRQ_GAMEPORT|IRQ_MPU401|IRQ_TIMER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) return IRQ_NONE; /* must be interrupt for another device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) "irq_count %ld! IDX_IO_IRQSTATUS %04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) irq_count++ /* debug-only */,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) if (status & IRQ_TIMER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) /* dev_dbg(chip->card->dev, "timer %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) snd_azf3328_codec_inl(chip, IDX_IO_TIMER_VALUE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) & TIMER_VALUE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) ); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) if (chip->timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) snd_timer_interrupt(chip->timer, chip->timer->sticks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) /* ACK timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) spin_lock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) snd_azf3328_ctrl_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) spin_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) dev_dbg(chip->card->dev, "timer IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) if (status & (IRQ_PLAYBACK|IRQ_RECORDING|IRQ_I2S_OUT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) snd_azf3328_pcm_interrupt(chip, chip->codecs, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) if (status & IRQ_GAMEPORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) snd_azf3328_gameport_interrupt(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) /* MPU401 has less critical IRQ requirements
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) * than timer and playback/recording, right? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) if (status & IRQ_MPU401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) /* hmm, do we have to ack the IRQ here somehow?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) * If so, then I don't know how yet... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) dev_dbg(chip->card->dev, "MPU401 IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) /*****************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) /* as long as we think we have identical snd_pcm_hardware parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) for playback, capture and i2s out, we can use the same physical struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) since the struct is simply being copied into a member.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) static const struct snd_pcm_hardware snd_azf3328_hardware =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) /* FIXME!! Correct? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) .info = SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) SNDRV_PCM_INFO_MMAP_VALID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) .formats = SNDRV_PCM_FMTBIT_S8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) SNDRV_PCM_FMTBIT_U8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) SNDRV_PCM_FMTBIT_S16_LE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) SNDRV_PCM_FMTBIT_U16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) .rates = SNDRV_PCM_RATE_5512 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) SNDRV_PCM_RATE_8000_48000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) SNDRV_PCM_RATE_KNOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) .rate_min = AZF_FREQ_4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) .rate_max = AZF_FREQ_66200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) .buffer_bytes_max = (64*1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) .period_bytes_min = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) .period_bytes_max = (32*1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) /* We simply have two DMA areas (instead of a list of descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) such as other cards); I believe that this is a fixed hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) attribute and there isn't much driver magic to be done to expand it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) Thus indicate that we have at least and at most 2 periods. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) .periods_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) /* FIXME: maybe that card actually has a FIFO?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) * Hmm, it seems newer revisions do have one, but we still don't know
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) * its size... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) .fifo_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) static const unsigned int snd_azf3328_fixed_rates[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) AZF_FREQ_4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) AZF_FREQ_4800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) AZF_FREQ_5512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) AZF_FREQ_6620,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) AZF_FREQ_8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) AZF_FREQ_9600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) AZF_FREQ_11025,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) AZF_FREQ_13240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) AZF_FREQ_16000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) AZF_FREQ_22050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) AZF_FREQ_32000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) AZF_FREQ_44100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) AZF_FREQ_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) AZF_FREQ_66200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) static const struct snd_pcm_hw_constraint_list snd_azf3328_hw_constraints_rates = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) .count = ARRAY_SIZE(snd_azf3328_fixed_rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) .list = snd_azf3328_fixed_rates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) .mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) /*****************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) snd_azf3328_pcm_open(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) enum snd_azf3328_codec_type codec_type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) struct snd_azf3328_codec_data *codec = &chip->codecs[codec_type];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) codec->substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) /* same parameters for all our codecs - at least we think so... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) runtime->hw = snd_azf3328_hardware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) &snd_azf3328_hw_constraints_rates);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) runtime->private_data = codec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) snd_azf3328_pcm_playback_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) return snd_azf3328_pcm_open(substream, AZF_CODEC_PLAYBACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) snd_azf3328_pcm_capture_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) return snd_azf3328_pcm_open(substream, AZF_CODEC_CAPTURE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) snd_azf3328_pcm_i2s_out_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) return snd_azf3328_pcm_open(substream, AZF_CODEC_I2S_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) snd_azf3328_pcm_close(struct snd_pcm_substream *substream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) struct snd_azf3328_codec_data *codec =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) codec->substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) /******************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) static const struct snd_pcm_ops snd_azf3328_playback_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) .open = snd_azf3328_pcm_playback_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) .close = snd_azf3328_pcm_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) .prepare = snd_azf3328_pcm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) .trigger = snd_azf3328_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) .pointer = snd_azf3328_pcm_pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) static const struct snd_pcm_ops snd_azf3328_capture_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) .open = snd_azf3328_pcm_capture_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) .close = snd_azf3328_pcm_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) .prepare = snd_azf3328_pcm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) .trigger = snd_azf3328_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) .pointer = snd_azf3328_pcm_pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) static const struct snd_pcm_ops snd_azf3328_i2s_out_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) .open = snd_azf3328_pcm_i2s_out_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) .close = snd_azf3328_pcm_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) .prepare = snd_azf3328_pcm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) .trigger = snd_azf3328_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) .pointer = snd_azf3328_pcm_pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) snd_azf3328_pcm(struct snd_azf3328 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) /* pcm devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) enum { AZF_PCMDEV_STD, AZF_PCMDEV_I2S_OUT, NUM_AZF_PCMDEVS };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) err = snd_pcm_new(chip->card, "AZF3328 DSP", AZF_PCMDEV_STD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) 1, 1, &pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) &snd_azf3328_playback_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) &snd_azf3328_capture_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) pcm->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) pcm->info_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) strcpy(pcm->name, chip->card->shortname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) /* same pcm object for playback/capture (see snd_pcm_new() above) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) chip->pcm[AZF_CODEC_PLAYBACK] = pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) chip->pcm[AZF_CODEC_CAPTURE] = pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) 64*1024, 64*1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) err = snd_pcm_new(chip->card, "AZF3328 I2S OUT", AZF_PCMDEV_I2S_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) 1, 0, &pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) &snd_azf3328_i2s_out_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) pcm->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) pcm->info_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) strcpy(pcm->name, chip->card->shortname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) chip->pcm[AZF_CODEC_I2S_OUT] = pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) 64*1024, 64*1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) /******************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) /*** NOTE: the physical timer resolution actually is 1024000 ticks per second
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) *** (probably derived from main crystal via a divider of 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) *** but announcing those attributes to user-space would make programs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) *** configure the timer to a 1 tick value, resulting in an absolutely fatal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) *** timer IRQ storm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) *** Thus I chose to announce a down-scaled virtual timer to the outside and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) *** calculate real timer countdown values internally.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) *** (the scale factor can be set via module parameter "seqtimer_scaling").
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) ***/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) snd_azf3328_timer_start(struct snd_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) struct snd_azf3328 *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) unsigned int delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) chip = snd_timer_chip(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) delay = ((timer->sticks * seqtimer_scaling) - 1) & TIMER_VALUE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) if (delay < 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) /* uhoh, that's not good, since user-space won't know about
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) * this timing tweak
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) * (we need to do it to avoid a lockup, though) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) dev_dbg(chip->card->dev, "delay was too low (%d)!\n", delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) delay = 49; /* minimum time is 49 ticks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) dev_dbg(chip->card->dev, "setting timer countdown value %d\n", delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) delay |= TIMER_COUNTDOWN_ENABLE | TIMER_IRQ_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) snd_azf3328_ctrl_outl(chip, IDX_IO_TIMER_VALUE, delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) snd_azf3328_timer_stop(struct snd_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) struct snd_azf3328 *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) chip = snd_timer_chip(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) /* disable timer countdown and interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) /* Hmm, should we write TIMER_IRQ_ACK here?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) YES indeed, otherwise a rogue timer operation - which prompts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) ALSA(?) to call repeated stop() in vain, but NOT start() -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) will never end (value 0x03 is kept shown in control byte).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) Simply manually poking 0x04 _once_ immediately successfully stops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) the hardware/ALSA interrupt activity. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) snd_azf3328_ctrl_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) snd_azf3328_timer_precise_resolution(struct snd_timer *timer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) unsigned long *num, unsigned long *den)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) *num = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) *den = 1024000 / seqtimer_scaling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) static struct snd_timer_hardware snd_azf3328_timer_hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) .flags = SNDRV_TIMER_HW_AUTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) .resolution = 977, /* 1000000/1024000 = 0.9765625us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) .ticks = 1024000, /* max tick count, defined by the value register; actually it's not 1024000, but 1048576, but we don't care */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) .start = snd_azf3328_timer_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) .stop = snd_azf3328_timer_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) .precise_resolution = snd_azf3328_timer_precise_resolution,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) snd_azf3328_timer(struct snd_azf3328 *chip, int device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) struct snd_timer *timer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) struct snd_timer_id tid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) tid.dev_class = SNDRV_TIMER_CLASS_CARD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) tid.card = chip->card->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) tid.device = device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) tid.subdevice = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) snd_azf3328_timer_hw.resolution *= seqtimer_scaling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) snd_azf3328_timer_hw.ticks /= seqtimer_scaling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) err = snd_timer_new(chip->card, "AZF3328", &tid, &timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) strcpy(timer->name, "AZF3328 timer");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) timer->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) timer->hw = snd_azf3328_timer_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) chip->timer = timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) snd_azf3328_timer_stop(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) /******************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) snd_azf3328_free(struct snd_azf3328 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) if (chip->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) goto __end_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) snd_azf3328_mixer_reset(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) snd_azf3328_timer_stop(chip->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) snd_azf3328_gameport_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) __end_hw:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) if (chip->irq >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) free_irq(chip->irq, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) pci_release_regions(chip->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) pci_disable_device(chip->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) kfree(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) snd_azf3328_dev_free(struct snd_device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) struct snd_azf3328 *chip = device->device_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) return snd_azf3328_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) /* check whether a bit can be modified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) snd_azf3328_test_bit(unsigned unsigned reg, int bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) unsigned char val, valoff, valon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) val = inb(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) outb(val & ~(1 << bit), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) valoff = inb(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) outb(val|(1 << bit), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) valon = inb(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) outb(val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) printk(KERN_DEBUG "reg %04x bit %d: %02x %02x %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) reg, bit, val, valoff, valon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) snd_azf3328_debug_show_ports(const struct snd_azf3328 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) u16 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) "ctrl_io 0x%lx, game_io 0x%lx, mpu_io 0x%lx, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) "opl3_io 0x%lx, mixer_io 0x%lx, irq %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) chip->ctrl_io, chip->game_io, chip->mpu_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) chip->opl3_io, chip->mixer_io, chip->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) "game %02x %02x %02x %02x %02x %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) snd_azf3328_game_inb(chip, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) snd_azf3328_game_inb(chip, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) snd_azf3328_game_inb(chip, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) snd_azf3328_game_inb(chip, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) snd_azf3328_game_inb(chip, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) snd_azf3328_game_inb(chip, 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) for (tmp = 0; tmp < 0x07; tmp += 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) "mpu_io 0x%04x\n", inb(chip->mpu_io + tmp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) for (tmp = 0; tmp <= 0x07; tmp += 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) "0x%02x: game200 0x%04x, game208 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) tmp, inb(0x200 + tmp), inb(0x208 + tmp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) for (tmp = 0; tmp <= 0x01; tmp += 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) "0x%02x: mpu300 0x%04x, mpu310 0x%04x, mpu320 0x%04x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) "mpu330 0x%04x opl388 0x%04x opl38c 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) tmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) inb(0x300 + tmp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) inb(0x310 + tmp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) inb(0x320 + tmp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) inb(0x330 + tmp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) inb(0x388 + tmp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) inb(0x38c + tmp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) for (tmp = 0; tmp < AZF_IO_SIZE_CTRL; tmp += 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) "ctrl 0x%02x: 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) tmp, snd_azf3328_ctrl_inw(chip, tmp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) for (tmp = 0; tmp < AZF_IO_SIZE_MIXER; tmp += 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) "mixer 0x%02x: 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) tmp, snd_azf3328_mixer_inw(chip, tmp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) snd_azf3328_create(struct snd_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) unsigned long device_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) struct snd_azf3328 **rchip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) struct snd_azf3328 *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) static const struct snd_device_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) .dev_free = snd_azf3328_dev_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) u8 dma_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) enum snd_azf3328_codec_type codec_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) struct snd_azf3328_codec_data *codec_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) *rchip = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) err = pci_enable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) chip = kzalloc(sizeof(*chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) if (chip == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) spin_lock_init(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) chip->card = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) chip->pci = pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) chip->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) /* check if we can restrict PCI DMA transfers to 24 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) if (dma_set_mask(&pci->dev, DMA_BIT_MASK(24)) < 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(24)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) dev_err(card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) "architecture does not support 24bit PCI busmaster DMA\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) err = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) err = pci_request_regions(pci, "Aztech AZF3328");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) chip->ctrl_io = pci_resource_start(pci, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) chip->game_io = pci_resource_start(pci, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) chip->mpu_io = pci_resource_start(pci, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) chip->opl3_io = pci_resource_start(pci, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) chip->mixer_io = pci_resource_start(pci, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) codec_setup = &chip->codecs[AZF_CODEC_PLAYBACK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) codec_setup->io_base = chip->ctrl_io + AZF_IO_OFFS_CODEC_PLAYBACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) codec_setup->lock = &chip->reg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) codec_setup->type = AZF_CODEC_PLAYBACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) codec_setup->name = "PLAYBACK";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) codec_setup = &chip->codecs[AZF_CODEC_CAPTURE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) codec_setup->io_base = chip->ctrl_io + AZF_IO_OFFS_CODEC_CAPTURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) codec_setup->lock = &chip->reg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) codec_setup->type = AZF_CODEC_CAPTURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) codec_setup->name = "CAPTURE";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) codec_setup = &chip->codecs[AZF_CODEC_I2S_OUT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) codec_setup->io_base = chip->ctrl_io + AZF_IO_OFFS_CODEC_I2S_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) codec_setup->lock = &chip->reg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) codec_setup->type = AZF_CODEC_I2S_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) codec_setup->name = "I2S_OUT";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) if (request_irq(pci->irq, snd_azf3328_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) IRQF_SHARED, KBUILD_MODNAME, chip)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) chip->irq = pci->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) card->sync_irq = chip->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) pci_set_master(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) snd_azf3328_debug_show_ports(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) /* create mixer interface & switches */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) err = snd_azf3328_mixer_new(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) /* standard codec init stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) /* default DMA init value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) dma_init = DMA_RUN_SOMETHING2|DMA_EPILOGUE_SOMETHING|DMA_SOMETHING_ELSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) for (codec_type = AZF_CODEC_PLAYBACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) codec_type <= AZF_CODEC_I2S_OUT; ++codec_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) struct snd_azf3328_codec_data *codec =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) &chip->codecs[codec_type];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) /* shutdown codecs to reduce power / noise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) /* have ...ctrl_codec_activity() act properly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) codec->running = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) snd_azf3328_ctrl_codec_activity(chip, codec_type, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) spin_lock_irq(codec->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) snd_azf3328_codec_outb(codec, IDX_IO_CODEC_DMA_FLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) dma_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) spin_unlock_irq(codec->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) *rchip = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) out_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) if (chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) snd_azf3328_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) snd_azf3328_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) static int dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) struct snd_azf3328 *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) struct snd_opl3 *opl3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) if (dev >= SNDRV_CARDS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) if (!enable[dev]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) dev++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) err = -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) 0, &card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) strcpy(card->driver, "AZF3328");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) strcpy(card->shortname, "Aztech AZF3328 (PCI168)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) err = snd_azf3328_create(card, pci, pci_id->driver_data, &chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) card->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) /* chose to use MPU401_HW_AZT2320 ID instead of MPU401_HW_MPU401,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) since our hardware ought to be similar, thus use same ID. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) err = snd_mpu401_uart_new(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) card, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) MPU401_HW_AZT2320, chip->mpu_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) -1, &chip->rmidi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) dev_err(card->dev, "no MPU-401 device at 0x%lx?\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) chip->mpu_io
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) err = snd_azf3328_timer(chip, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) err = snd_azf3328_pcm(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) if (snd_opl3_create(card, chip->opl3_io, chip->opl3_io+2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) OPL3_HW_AUTO, 1, &opl3) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) dev_err(card->dev, "no OPL3 device at 0x%lx-0x%lx?\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) chip->opl3_io, chip->opl3_io+2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) /* need to use IDs 1, 2 since ID 0 is snd_azf3328_timer above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) err = snd_opl3_timer_new(opl3, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) err = snd_opl3_hwdep_new(opl3, 0, 1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) opl3->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) sprintf(card->longname, "%s at 0x%lx, irq %i",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) card->shortname, chip->ctrl_io, chip->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) err = snd_card_register(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) #ifdef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) dev_info(card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) "Sound driver for Aztech AZF3328-based soundcards such as PCI168.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) dev_info(card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) "Hardware was completely undocumented, unfortunately.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) dev_info(card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) "Feel free to contact andi AT lisas.de for bug reports etc.!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) dev_info(card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) "User-scalable sequencer timer set to %dHz (1024000Hz / %d).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) 1024000 / seqtimer_scaling, seqtimer_scaling);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) snd_azf3328_gameport(chip, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) pci_set_drvdata(pci, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) dev++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) out_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) dev_err(card->dev, "something failed, exiting\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) snd_azf3328_remove(struct pci_dev *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) snd_card_free(pci_get_drvdata(pci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) snd_azf3328_suspend_regs(const struct snd_azf3328 *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) unsigned long io_addr, unsigned count, u32 *saved_regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) unsigned reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) for (reg = 0; reg < count; ++reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) *saved_regs = inl(io_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) dev_dbg(chip->card->dev, "suspend: io 0x%04lx: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) io_addr, *saved_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) ++saved_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) io_addr += sizeof(*saved_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) snd_azf3328_resume_regs(const struct snd_azf3328 *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) const u32 *saved_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) unsigned long io_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) unsigned count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) unsigned reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) for (reg = 0; reg < count; ++reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) outl(*saved_regs, io_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) "resume: io 0x%04lx: 0x%08x --> 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) io_addr, *saved_regs, inl(io_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) ++saved_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) io_addr += sizeof(*saved_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) snd_azf3328_suspend_ac97(struct snd_azf3328 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) #ifdef AZF_USE_AC97_LAYER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) snd_ac97_suspend(chip->ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) snd_azf3328_suspend_regs(chip, chip->mixer_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) ARRAY_SIZE(chip->saved_regs_mixer), chip->saved_regs_mixer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) /* make sure to disable master volume etc. to prevent looping sound */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) snd_azf3328_mixer_mute_control_master(chip, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) snd_azf3328_mixer_mute_control_pcm(chip, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) #endif /* AZF_USE_AC97_LAYER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) snd_azf3328_resume_ac97(const struct snd_azf3328 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) #ifdef AZF_USE_AC97_LAYER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) snd_ac97_resume(chip->ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) snd_azf3328_resume_regs(chip, chip->saved_regs_mixer, chip->mixer_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) ARRAY_SIZE(chip->saved_regs_mixer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) /* unfortunately with 32bit transfers, IDX_MIXER_PLAY_MASTER (0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) and IDX_MIXER_RESET (offset 0x00) get touched at the same time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) resulting in a mixer reset condition persisting until _after_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) master vol was restored. Thus master vol needs an extra restore. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) outw(((u16 *)chip->saved_regs_mixer)[1], chip->mixer_io + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) #endif /* AZF_USE_AC97_LAYER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) snd_azf3328_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) struct snd_azf3328 *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) u16 *saved_regs_ctrl_u16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) snd_azf3328_suspend_ac97(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) snd_azf3328_suspend_regs(chip, chip->ctrl_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) ARRAY_SIZE(chip->saved_regs_ctrl), chip->saved_regs_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) /* manually store the one currently relevant write-only reg, too */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) saved_regs_ctrl_u16 = (u16 *)chip->saved_regs_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) saved_regs_ctrl_u16[IDX_IO_6AH / 2] = chip->shadow_reg_ctrl_6AH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) snd_azf3328_suspend_regs(chip, chip->game_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) ARRAY_SIZE(chip->saved_regs_game), chip->saved_regs_game);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) snd_azf3328_suspend_regs(chip, chip->mpu_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) ARRAY_SIZE(chip->saved_regs_mpu), chip->saved_regs_mpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) snd_azf3328_suspend_regs(chip, chip->opl3_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) ARRAY_SIZE(chip->saved_regs_opl3), chip->saved_regs_opl3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) snd_azf3328_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) const struct snd_azf3328 *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) snd_azf3328_resume_regs(chip, chip->saved_regs_game, chip->game_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) ARRAY_SIZE(chip->saved_regs_game));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) snd_azf3328_resume_regs(chip, chip->saved_regs_mpu, chip->mpu_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) ARRAY_SIZE(chip->saved_regs_mpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) snd_azf3328_resume_regs(chip, chip->saved_regs_opl3, chip->opl3_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) ARRAY_SIZE(chip->saved_regs_opl3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) snd_azf3328_resume_ac97(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) snd_azf3328_resume_regs(chip, chip->saved_regs_ctrl, chip->ctrl_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) ARRAY_SIZE(chip->saved_regs_ctrl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) snd_power_change_state(card, SNDRV_CTL_POWER_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) static SIMPLE_DEV_PM_OPS(snd_azf3328_pm, snd_azf3328_suspend, snd_azf3328_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) #define SND_AZF3328_PM_OPS &snd_azf3328_pm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) #define SND_AZF3328_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) static struct pci_driver azf3328_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) .name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) .id_table = snd_azf3328_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) .probe = snd_azf3328_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) .remove = snd_azf3328_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) .pm = SND_AZF3328_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) module_pci_driver(azf3328_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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