^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2008 Cedric Bregardis <cedric.bregardis@free.fr> and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Jean-Christian Hassler <jhassler@free.fr>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This file is part of the Audiowerk2 ALSA driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* SAA7146 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define PCI_BT_A 0x4C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define IICTFR 0x8C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define IICSTA 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define BaseA1_in 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define ProtA1_in 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PageA1_in 0x9C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define BaseA1_out 0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define ProtA1_out 0xA4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PageA1_out 0xA8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define BaseA2_in 0xAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ProtA2_in 0xB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PageA2_in 0xB4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define BaseA2_out 0xB8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ProtA2_out 0xBC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PageA2_out 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IER 0xDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define GPIO_CTRL 0xE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ACON1 0xF4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ACON2 0xF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MC1 0xFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MC2 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ISR 0x10C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PSR 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SSR 0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PCI_ADP1 0x12C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PCI_ADP2 0x130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PCI_ADP3 0x134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PCI_ADP4 0x138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define LEVEL_REP 0x140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define FB_BUFFER1 0x144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define FB_BUFFER2 0x148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TSL1 0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TSL2 0x1C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ME (1UL << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define LIMIT (1UL << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PV (1UL << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* PSR/ISR/IER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PPEF (1UL << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PABO (1UL << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IIC_S (1UL << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IIC_E (1UL << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define A2_in (1UL << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define A2_out (1UL << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define A1_in (1UL << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define A1_out (1UL << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define AFOU (1UL << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PIN3 (1UL << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PIN2 (1UL << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PIN1 (1UL << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PIN0 (1UL << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ECS (1UL << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define EC3S (1UL << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define EC0S (1UL << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* SSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PRQ (1UL << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PMA (1UL << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define IIC_EA (1UL << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define IIC_EW (1UL << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define IIC_ER (1UL << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define IIC_EL (1UL << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define IIC_EF (1UL << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define AF2_in (1UL << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define AF2_out (1UL << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define AF1_in (1UL << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define AF1_out (1UL << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define EC5S (1UL << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define EC4S (1UL << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define EC2S (1UL << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define EC1S (1UL << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* PCI_BT_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define BurstA1_in (1UL << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define ThreshA1_in (1UL << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define BurstA1_out (1UL << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define ThreshA1_out (1UL << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define BurstA2_in (1UL << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define ThreshA2_in (1UL << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define BurstA2_out (1UL << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ThreshA2_out (1UL << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* MC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MRST_N (1UL << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define EAP (1UL << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define EI2C (1UL << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define TR_E_A2_OUT (1UL << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TR_E_A2_IN (1UL << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TR_E_A1_OUT (1UL << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define TR_E_A1_IN (1UL << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* MC2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define UPLD_IIC (1UL << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* ACON1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define AUDIO_MODE (1UL << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MAXLEVEL (1UL << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define A1_SWAP (1UL << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define A2_SWAP (1UL << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define WS0_CTRL (1UL << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define WS0_SYNC (1UL << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define WS1_CTRL (1UL << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define WS1_SYNC (1UL << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define WS2_CTRL (1UL << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define WS2_SYNC (1UL << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define WS3_CTRL (1UL << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define WS3_SYNC (1UL << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define WS4_CTRL (1UL << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define WS4_SYNC (1UL << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* ACON2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define A1_CLKSRC (1UL << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define A2_CLKSRC (1UL << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define INVERT_BCLK1 (1UL << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define INVERT_BCLK2 (1UL << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define BCLK1_OEN (1UL << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define BCLK2_OEN (1UL << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* IICSTA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define IICCC (1UL << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define ABORT (1UL << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SPERR (1UL << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define APERR (1UL << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define DTERR (1UL << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define DRERR (1UL << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define AL (1UL << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define ERR (1UL << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define BUSY (1UL << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* IICTFR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define BYTE2 (1UL << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define BYTE1 (1UL << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define BYTE0 (1UL << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define ATRR2 (1UL << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define ATRR1 (1UL << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define ATRR0 (1UL << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define ERR (1UL << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define BUSY (1UL << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define START 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CONT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define STOP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define NOP 0
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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