^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2008 Cedric Bregardis <cedric.bregardis@free.fr> and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Jean-Christian Hassler <jhassler@free.fr>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 1998 Emagic Soft- und Hardware GmbH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2002 Martijn Sipkema
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This file is part of the Audiowerk2 ALSA driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define TSL_WS0 (1UL << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define TSL_WS1 (1UL << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define TSL_WS2 (1UL << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define TSL_WS3 (1UL << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define TSL_WS4 (1UL << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define TSL_DIS_A1 (1UL << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TSL_SDW_A1 (1UL << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TSL_SIB_A1 (1UL << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TSL_SF_A1 (1UL << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TSL_LF_A1 (1UL << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TSL_BSEL_A1 (1UL << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TSL_DOD_A1 (1UL << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TSL_LOW_A1 (1UL << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TSL_DIS_A2 (1UL << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TSL_SDW_A2 (1UL << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TSL_SIB_A2 (1UL << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TSL_SF_A2 (1UL << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TSL_LF_A2 (1UL << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TSL_BSEL_A2 (1UL << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TSL_DOD_A2 (1UL << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TSL_LOW_A2 (1UL << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TSL_EOS (1UL << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* Audiowerk8 hardware setup: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* WS0, SD4, TSL1 - Analog/ digital in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* WS1, SD0, TSL1 - Analog out #1, digital out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* WS2, SD2, TSL1 - Analog out #2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* WS3, SD1, TSL2 - Analog out #3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* WS4, SD3, TSL2 - Analog out #4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Audiowerk8 timing: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Timeslot: | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* A1_INPUT: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* SD4: <_ADC-L_>-------<_ADC-R_>-------< */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* WS0: _______________/---------------\_ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* A1_OUTPUT: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* SD0: <_1-L___>-------<_1-R___>-------< */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* WS1: _______________/---------------\_ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* SD2: >-------<_2-L___>-------<_2-R___> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* WS2: -------\_______________/--------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* A2_OUTPUT: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* SD1: <_3-L___>-------<_3-R___>-------< */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* WS3: _______________/---------------\_ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* SD3: >-------<_4-L___>-------<_4-R___> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* WS4: -------\_______________/--------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static const int tsl1[8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 1 * TSL_SDW_A1 | 3 * TSL_BSEL_A1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1 | TSL_LF_A1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 1 * TSL_SDW_A1 | 2 * TSL_BSEL_A1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 0 * TSL_SDW_A1 | 3 * TSL_BSEL_A1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 0 * TSL_SDW_A1 | 2 * TSL_BSEL_A1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 1 * TSL_SDW_A1 | 1 * TSL_BSEL_A1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1 | TSL_WS1 | TSL_WS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 1 * TSL_SDW_A1 | 0 * TSL_BSEL_A1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1 | TSL_WS1 | TSL_WS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 0 * TSL_SDW_A1 | 1 * TSL_BSEL_A1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1 | TSL_WS1 | TSL_WS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 0 * TSL_SDW_A1 | 0 * TSL_BSEL_A1 | 0 * TSL_DIS_A1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 0 * TSL_DOD_A1 | TSL_WS1 | TSL_WS0 | TSL_SF_A1 | TSL_EOS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static const int tsl2[8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 0 * TSL_SDW_A2 | 3 * TSL_BSEL_A2 | 2 * TSL_DOD_A2 | TSL_LF_A2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 0 * TSL_SDW_A2 | 2 * TSL_BSEL_A2 | 2 * TSL_DOD_A2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) 0 * TSL_SDW_A2 | 3 * TSL_BSEL_A2 | 2 * TSL_DOD_A2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) 0 * TSL_SDW_A2 | 2 * TSL_BSEL_A2 | 2 * TSL_DOD_A2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) 0 * TSL_SDW_A2 | 1 * TSL_BSEL_A2 | 2 * TSL_DOD_A2 | TSL_WS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) 0 * TSL_SDW_A2 | 0 * TSL_BSEL_A2 | 2 * TSL_DOD_A2 | TSL_WS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) 0 * TSL_SDW_A2 | 1 * TSL_BSEL_A2 | 2 * TSL_DOD_A2 | TSL_WS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) 0 * TSL_SDW_A2 | 0 * TSL_BSEL_A2 | 2 * TSL_DOD_A2 | TSL_WS2 | TSL_EOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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