^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2008 Cedric Bregardis <cedric.bregardis@free.fr> and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Jean-Christian Hassler <jhassler@free.fr>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This file is part of the Audiowerk2 ALSA driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define AW2_SAA7146_M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "saa7146.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "aw2-saa7146.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "aw2-tsl.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define WRITEREG(value, addr) writel((value), chip->base_addr + (addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define READREG(addr) readl(chip->base_addr + (addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static struct snd_aw2_saa7146_cb_param
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) arr_substream_it_playback_cb[NB_STREAM_PLAYBACK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static struct snd_aw2_saa7146_cb_param
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) arr_substream_it_capture_cb[NB_STREAM_CAPTURE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static int snd_aw2_saa7146_get_limit(int size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* chip-specific destructor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int snd_aw2_saa7146_free(struct snd_aw2_saa7146 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* disable all irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) WRITEREG(0, IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* reset saa7146 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) WRITEREG((MRST_N << 16), MC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Unset base addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) chip->base_addr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) void snd_aw2_saa7146_setup(struct snd_aw2_saa7146 *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) void __iomem *pci_base_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* set PCI burst/threshold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) Burst length definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) VALUE BURST LENGTH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 000 1 Dword
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 001 2 Dwords
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 010 4 Dwords
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 011 8 Dwords
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 100 16 Dwords
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 101 32 Dwords
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 110 64 Dwords
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 111 128 Dwords
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) Threshold definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) VALUE WRITE MODE READ MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 00 1 Dword of valid data 1 empty Dword
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 01 4 Dwords of valid data 4 empty Dwords
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 10 8 Dwords of valid data 8 empty Dwords
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 11 16 Dwords of valid data 16 empty Dwords */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned int acon2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned int acon1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Set base addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) chip->base_addr = pci_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* disable all irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) WRITEREG(0, IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* reset saa7146 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) WRITEREG((MRST_N << 16), MC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* enable audio interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) acon1 |= A1_SWAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) acon1 |= A2_SWAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* WS0_CTRL, WS0_SYNC: input TSL1, I2S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* At initialization WS1 and WS2 are disabled (configured as input) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) acon1 |= 0 * WS1_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) acon1 |= 0 * WS2_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* WS4 is not used. So it must not restart A2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) This is why it is configured as output (force to low) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) acon1 |= 3 * WS4_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* WS3_CTRL, WS3_SYNC: output TSL2, I2S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) acon1 |= 2 * WS3_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* A1 and A2 are active and asynchronous */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) acon1 |= 3 * AUDIO_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) WRITEREG(acon1, ACON1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* The following comes from original windows driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) It is needed to have a correct behavior of input and output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) simultenously, but I don't know why ! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) WRITEREG(3 * (BurstA1_in) + 3 * (ThreshA1_in) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 3 * (BurstA1_out) + 3 * (ThreshA1_out) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 3 * (BurstA2_out) + 3 * (ThreshA2_out), PCI_BT_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* enable audio port pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) WRITEREG((EAP << 16) | EAP, MC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* enable I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) WRITEREG((EI2C << 16) | EI2C, MC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) WRITEREG(A1_out | A2_out | A1_in | IIC_S | IIC_E, IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* audio configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) acon2 = A2_CLKSRC | BCLK1_OEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) WRITEREG(acon2, ACON2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* By default use analog input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) snd_aw2_saa7146_use_digital_input(chip, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* TSL setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) for (i = 0; i < 8; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) WRITEREG(tsl1[i], TSL1 + (i * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) WRITEREG(tsl2[i], TSL2 + (i * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) void snd_aw2_saa7146_pcm_init_playback(struct snd_aw2_saa7146 *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int stream_number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned long dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) unsigned long period_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned long buffer_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) unsigned long dw_page, dw_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* Configure DMA for substream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) Configuration informations: ALSA has allocated continuous memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) pages. So we don't need to use MMU of saa7146.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* No MMU -> nothing to do with PageA1, we only configure the limit of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) PageAx_out register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* Disable MMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) dw_page = (0L << 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Configure Limit for DMA access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) The limit register defines an address limit, which generates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) an interrupt if passed by the actual PCI address pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) '0001' means an interrupt will be generated if the lower
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 6 bits (64 bytes) of the PCI address are zero. '0010'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) defines a limit of 128 bytes, '0011' one of 256 bytes, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) so on up to 1 Mbyte defined by '1111'. This interrupt range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) can be calculated as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) Range = 2^(5 + Limit) bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) dw_limit = snd_aw2_saa7146_get_limit(period_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) dw_page |= (dw_limit << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (stream_number == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) WRITEREG(dw_page, PageA2_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Base address for DMA transfert. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* This address has been reserved by ALSA. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* This is a physical address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) WRITEREG(dma_addr, BaseA2_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* Define upper limit for DMA access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) WRITEREG(dma_addr + buffer_size, ProtA2_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) } else if (stream_number == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) WRITEREG(dw_page, PageA1_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* Base address for DMA transfert. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* This address has been reserved by ALSA. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* This is a physical address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) WRITEREG(dma_addr, BaseA1_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* Define upper limit for DMA access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) WRITEREG(dma_addr + buffer_size, ProtA1_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) pr_err("aw2: snd_aw2_saa7146_pcm_init_playback: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) "Substream number is not 0 or 1 -> not managed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) void snd_aw2_saa7146_pcm_init_capture(struct snd_aw2_saa7146 *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int stream_number, unsigned long dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) unsigned long period_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned long buffer_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) unsigned long dw_page, dw_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Configure DMA for substream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) Configuration informations: ALSA has allocated continuous memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) pages. So we don't need to use MMU of saa7146.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* No MMU -> nothing to do with PageA1, we only configure the limit of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) PageAx_out register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* Disable MMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) dw_page = (0L << 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* Configure Limit for DMA access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) The limit register defines an address limit, which generates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) an interrupt if passed by the actual PCI address pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) '0001' means an interrupt will be generated if the lower
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 6 bits (64 bytes) of the PCI address are zero. '0010'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) defines a limit of 128 bytes, '0011' one of 256 bytes, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) so on up to 1 Mbyte defined by '1111'. This interrupt range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) can be calculated as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) Range = 2^(5 + Limit) bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) dw_limit = snd_aw2_saa7146_get_limit(period_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) dw_page |= (dw_limit << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (stream_number == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) WRITEREG(dw_page, PageA1_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* Base address for DMA transfert. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* This address has been reserved by ALSA. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* This is a physical address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) WRITEREG(dma_addr, BaseA1_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Define upper limit for DMA access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) WRITEREG(dma_addr + buffer_size, ProtA1_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) pr_err("aw2: snd_aw2_saa7146_pcm_init_capture: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) "Substream number is not 0 -> not managed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) void snd_aw2_saa7146_define_it_playback_callback(unsigned int stream_number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) snd_aw2_saa7146_it_cb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) p_it_callback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) void *p_callback_param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (stream_number < NB_STREAM_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) arr_substream_it_playback_cb[stream_number].p_it_callback =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) (snd_aw2_saa7146_it_cb) p_it_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) arr_substream_it_playback_cb[stream_number].p_callback_param =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) (void *)p_callback_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) void snd_aw2_saa7146_define_it_capture_callback(unsigned int stream_number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) snd_aw2_saa7146_it_cb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) p_it_callback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) void *p_callback_param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (stream_number < NB_STREAM_CAPTURE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) arr_substream_it_capture_cb[stream_number].p_it_callback =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) (snd_aw2_saa7146_it_cb) p_it_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) arr_substream_it_capture_cb[stream_number].p_callback_param =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) (void *)p_callback_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) void snd_aw2_saa7146_pcm_trigger_start_playback(struct snd_aw2_saa7146 *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) int stream_number)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) unsigned int acon1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* In aw8 driver, dma transfert is always active. It is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) started and stopped in a larger "space" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) acon1 = READREG(ACON1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (stream_number == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) WRITEREG((TR_E_A2_OUT << 16) | TR_E_A2_OUT, MC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* WS2_CTRL, WS2_SYNC: output TSL2, I2S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) acon1 |= 2 * WS2_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) WRITEREG(acon1, ACON1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) } else if (stream_number == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) WRITEREG((TR_E_A1_OUT << 16) | TR_E_A1_OUT, MC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* WS1_CTRL, WS1_SYNC: output TSL1, I2S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) acon1 |= 1 * WS1_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) WRITEREG(acon1, ACON1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) void snd_aw2_saa7146_pcm_trigger_stop_playback(struct snd_aw2_saa7146 *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int stream_number)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) unsigned int acon1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) acon1 = READREG(ACON1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (stream_number == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* WS2_CTRL, WS2_SYNC: output TSL2, I2S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) acon1 &= ~(3 * WS2_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) WRITEREG(acon1, ACON1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) WRITEREG((TR_E_A2_OUT << 16), MC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) } else if (stream_number == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* WS1_CTRL, WS1_SYNC: output TSL1, I2S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) acon1 &= ~(3 * WS1_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) WRITEREG(acon1, ACON1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) WRITEREG((TR_E_A1_OUT << 16), MC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) void snd_aw2_saa7146_pcm_trigger_start_capture(struct snd_aw2_saa7146 *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) int stream_number)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* In aw8 driver, dma transfert is always active. It is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) started and stopped in a larger "space" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (stream_number == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) WRITEREG((TR_E_A1_IN << 16) | TR_E_A1_IN, MC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) void snd_aw2_saa7146_pcm_trigger_stop_capture(struct snd_aw2_saa7146 *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int stream_number)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (stream_number == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) WRITEREG((TR_E_A1_IN << 16), MC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) irqreturn_t snd_aw2_saa7146_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) unsigned int isr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) __always_unused unsigned int iicsta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct snd_aw2_saa7146 *chip = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) isr = READREG(ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (!isr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) WRITEREG(isr, ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (isr & (IIC_S | IIC_E)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) iicsta = READREG(IICSTA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) WRITEREG(0x100, IICSTA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (isr & A1_out) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (arr_substream_it_playback_cb[1].p_it_callback != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) arr_substream_it_playback_cb[1].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) p_it_callback(arr_substream_it_playback_cb[1].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) p_callback_param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (isr & A2_out) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (arr_substream_it_playback_cb[0].p_it_callback != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) arr_substream_it_playback_cb[0].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) p_it_callback(arr_substream_it_playback_cb[0].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) p_callback_param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (isr & A1_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (arr_substream_it_capture_cb[0].p_it_callback != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) arr_substream_it_capture_cb[0].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) p_it_callback(arr_substream_it_capture_cb[0].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) p_callback_param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) unsigned int snd_aw2_saa7146_get_hw_ptr_playback(struct snd_aw2_saa7146 *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) int stream_number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) unsigned char *start_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) unsigned int buffer_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) long pci_adp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) size_t ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (stream_number == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) pci_adp = READREG(PCI_ADP3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) ptr = pci_adp - (long)start_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (ptr == buffer_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (stream_number == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) pci_adp = READREG(PCI_ADP1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) ptr = pci_adp - (size_t) start_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (ptr == buffer_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) unsigned int snd_aw2_saa7146_get_hw_ptr_capture(struct snd_aw2_saa7146 *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) int stream_number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) unsigned char *start_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) unsigned int buffer_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) size_t pci_adp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) size_t ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (stream_number == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) pci_adp = READREG(PCI_ADP2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) ptr = pci_adp - (size_t) start_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (ptr == buffer_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) void snd_aw2_saa7146_use_digital_input(struct snd_aw2_saa7146 *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) int use_digital)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* FIXME: switch between analog and digital input does not always work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) It can produce a kind of white noise. It seams that received data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) are inverted sometime (endian inversion). Why ? I don't know, maybe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) a problem of synchronization... However for the time being I have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) not found the problem. Workaround: switch again (and again) between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) digital and analog input until it works. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (use_digital)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) WRITEREG(0x40, GPIO_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) WRITEREG(0x50, GPIO_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) int snd_aw2_saa7146_is_using_digital_input(struct snd_aw2_saa7146 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) unsigned int reg_val = READREG(GPIO_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if ((reg_val & 0xFF) == 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static int snd_aw2_saa7146_get_limit(int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) int limitsize = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) int limit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) while (limitsize < size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) limitsize *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) limit++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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