^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * WT register offsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Wed Oct 22 13:50:20 2003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2003 mjander
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * mjander@users.sourceforge.org
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef _AU88X0_WT_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _AU88X0_WT_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* WT channels are grouped in banks. Each bank has 0x20 channels. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* Bank register address boundary is 0x8000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define NR_WT_PB 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* WT bank base register (as dword address). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define WT_BAR(x) (((x)&0xffe0)<<0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define WT_BANK(x) (x>>5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* WT Bank registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define WT_CTRL(bank) (((((bank)&1)<<0xd) + 0x00)<<2) /* 0x0000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define WT_SRAMP(bank) (((((bank)&1)<<0xd) + 0x01)<<2) /* 0x0004 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define WT_DSREG(bank) (((((bank)&1)<<0xd) + 0x02)<<2) /* 0x0008 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define WT_MRAMP(bank) (((((bank)&1)<<0xd) + 0x03)<<2) /* 0x000c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define WT_GMODE(bank) (((((bank)&1)<<0xd) + 0x04)<<2) /* 0x0010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define WT_ARAMP(bank) (((((bank)&1)<<0xd) + 0x05)<<2) /* 0x0014 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* WT Voice registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define WT_STEREO(voice) ((WT_BAR(voice)+ 0x20 +(((voice)&0x1f)>>1))<<2) /* 0x0080 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define WT_MUTE(voice) ((WT_BAR(voice)+ 0x40 +((voice)&0x1f))<<2) /* 0x0100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define WT_RUN(voice) ((WT_BAR(voice)+ 0x60 +((voice)&0x1f))<<2) /* 0x0180 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Some kind of parameters. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* PARM0, PARM1 : Filter (0xFF000000), SampleRate (0x0000FFFF) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* PARM2, PARM3 : Still unknown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define WT_PARM(x,y) (((WT_BAR(x))+ 0x80 +(((x)&0x1f)<<2)+(y))<<2) /* 0x0200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define WT_DELAY(x,y) (((WT_BAR(x))+ 0x100 +(((x)&0x1f)<<2)+(y))<<2) /* 0x0400 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Numeric indexes used by SetReg() and GetReg() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) run = 0, /* 0 W 1:run 0:stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) parm0, /* 1 W filter, samplerate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) parm1, /* 2 W filter, samplerate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) parm2, /* 3 W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) parm3, /* 4 RW volume. This value is calculated using floating point ops. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) sramp, /* 5 W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) mute, /* 6 W 1:mute, 0:unmute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) gmode, /* 7 RO Looks like only bit0 is used. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) aramp, /* 8 W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) mramp, /* 9 W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ctrl, /* a W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) delay, /* b W All 4 values are written at once with same value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) dsreg, /* c (R)W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) } wt_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u32 parm0; /* this_1E4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 parm1; /* this_1E8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 parm2; /* this_1EC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u32 parm3; /* this_1F0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 this_1D0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) } wt_voice_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #endif /* _AU88X0_WT_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* End of file */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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