Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Someday its supposed to make use of the WT DMA engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * for a Wavetable synthesizer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include "au88x0.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include "au88x0_wt.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) static void vortex_fifo_setwtvalid(vortex_t * vortex, int fifo, int en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) static void vortex_connection_adb_mixin(vortex_t * vortex, int en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 					unsigned char channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 					unsigned char source,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 					unsigned char mixin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) static void vortex_connection_mixin_mix(vortex_t * vortex, int en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 					unsigned char mixin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 					unsigned char mix, int a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) static void vortex_fifo_wtinitialize(vortex_t * vortex, int fifo, int j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) static int vortex_wt_SetReg(vortex_t * vortex, unsigned char reg, int wt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 			    u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) /* WT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) /* Put 2 WT channels together for one stereo interlaced channel. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) static void vortex_wt_setstereo(vortex_t * vortex, u32 wt, u32 stereo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	//temp = hwread(vortex->mmio, 0x80 + ((wt >> 0x5)<< 0xf) + (((wt & 0x1f) >> 1) << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	temp = hwread(vortex->mmio, WT_STEREO(wt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	temp = (temp & 0xfe) | (stereo & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	//hwwrite(vortex->mmio, 0x80 + ((wt >> 0x5)<< 0xf) + (((wt & 0x1f) >> 1) << 2), temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	hwwrite(vortex->mmio, WT_STEREO(wt), temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) /* Join to mixdown route. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) static void vortex_wt_setdsout(vortex_t * vortex, u32 wt, int en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	/* There is one DSREG register for each bank (32 voices each). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	temp = hwread(vortex->mmio, WT_DSREG((wt >= 0x20) ? 1 : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	if (en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		temp |= (1 << (wt & 0x1f));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		temp &= ~(1 << (wt & 0x1f));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	hwwrite(vortex->mmio, WT_DSREG((wt >= 0x20) ? 1 : 0), temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) /* Setup WT route. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) static int vortex_wt_allocroute(vortex_t * vortex, int wt, int nr_ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	wt_voice_t *voice = &(vortex->wt_voice[wt]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	//FIXME: WT audio routing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	if (nr_ch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		vortex_fifo_wtinitialize(vortex, wt, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		vortex_fifo_setwtvalid(vortex, wt, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		vortex_wt_setstereo(vortex, wt, nr_ch - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	} else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		vortex_fifo_setwtvalid(vortex, wt, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	/* Set mixdown mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	vortex_wt_setdsout(vortex, wt, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	/* Set other parameter registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	hwwrite(vortex->mmio, WT_SRAMP(0), 0x880000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	//hwwrite(vortex->mmio, WT_GMODE(0), 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #ifdef CHIP_AU8830
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	hwwrite(vortex->mmio, WT_SRAMP(1), 0x880000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	//hwwrite(vortex->mmio, WT_GMODE(1), 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	hwwrite(vortex->mmio, WT_PARM(wt, 0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	hwwrite(vortex->mmio, WT_PARM(wt, 1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	hwwrite(vortex->mmio, WT_PARM(wt, 2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	temp = hwread(vortex->mmio, WT_PARM(wt, 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	dev_dbg(vortex->card->dev, "WT PARM3: %x\n", temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	//hwwrite(vortex->mmio, WT_PARM(wt, 3), temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	hwwrite(vortex->mmio, WT_DELAY(wt, 0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	hwwrite(vortex->mmio, WT_DELAY(wt, 1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	hwwrite(vortex->mmio, WT_DELAY(wt, 2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	hwwrite(vortex->mmio, WT_DELAY(wt, 3), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	dev_dbg(vortex->card->dev, "WT GMODE: %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		hwread(vortex->mmio, WT_GMODE(wt)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	hwwrite(vortex->mmio, WT_PARM(wt, 2), 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	hwwrite(vortex->mmio, WT_PARM(wt, 3), 0xcff1c810);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	voice->parm0 = voice->parm1 = 0xcfb23e2f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	hwwrite(vortex->mmio, WT_PARM(wt, 0), voice->parm0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	hwwrite(vortex->mmio, WT_PARM(wt, 1), voice->parm1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	dev_dbg(vortex->card->dev, "WT GMODE 2 : %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		hwread(vortex->mmio, WT_GMODE(wt)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static void vortex_wt_connect(vortex_t * vortex, int en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	int i, ii, mix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define NR_WTROUTES 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #ifdef CHIP_AU8830
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define NR_WTBLOCKS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define NR_WTBLOCKS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	for (i = 0; i < NR_WTBLOCKS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		for (ii = 0; ii < NR_WTROUTES; ii++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 			mix =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 			    vortex_adb_checkinout(vortex,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 						  vortex->fixed_res, en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 						  VORTEX_RESOURCE_MIXIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 			vortex->mixwt[(i * NR_WTROUTES) + ii] = mix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			vortex_route(vortex, en, 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 				     ADB_WTOUT(i, ii + 0x20), ADB_MIXIN(mix));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 			vortex_connection_mixin_mix(vortex, en, mix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 						    vortex->mixplayb[ii % 2], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			if (VORTEX_IS_QUAD(vortex))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 				vortex_connection_mixin_mix(vortex, en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 							    mix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 							    vortex->mixplayb[2 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 								     (ii % 2)], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	for (i = 0; i < NR_WT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		hwwrite(vortex->mmio, WT_RUN(i), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* Read WT Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int vortex_wt_GetReg(vortex_t * vortex, char reg, int wt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	//int eax, esi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	if (reg == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		return hwread(vortex->mmio, WT_PARM(wt, 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	if (reg == 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		return hwread(vortex->mmio, WT_GMODE(wt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* WT hardware abstraction layer generic register interface. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) vortex_wt_SetReg2(vortex_t * vortex, unsigned char reg, int wt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		  u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	   int eax, edx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	   if (wt >= NR_WT)  // 0x40 -> NR_WT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	   return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	   if ((reg - 0x20) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	   if ((reg - 0x21) != 0) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	   return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	   eax = ((((b & 0xff) << 0xb) + (edx & 0xff)) << 4) + 0x208; // param 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	   } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	   eax = ((((b & 0xff) << 0xb) + (edx & 0xff)) << 4) + 0x20a; // param 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	   }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	   hwwrite(vortex->mmio, eax, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /*public: static void __thiscall CWTHal::SetReg(unsigned char,int,unsigned long) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) vortex_wt_SetReg(vortex_t * vortex, unsigned char reg, int wt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		 u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	int ecx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	if ((reg == 5) || ((reg >= 7) && (reg <= 10)) || (reg == 0xc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		if (wt >= (NR_WT / NR_WT_PB)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			dev_warn(vortex->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 				 "WT SetReg: bank out of range. reg=0x%x, wt=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 				 reg, wt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		if (wt >= NR_WT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 			dev_err(vortex->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 				"WT SetReg: voice out of range\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	if (reg > 0xc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		/* Voice specific parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	case 0:		/* running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		pr_debug( "vortex: WT SetReg(0x%x) = 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		       WT_RUN(wt), (int)val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		hwwrite(vortex->mmio, WT_RUN(wt), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		return 0xc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	case 1:		/* param 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		pr_debug( "vortex: WT SetReg(0x%x) = 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		       WT_PARM(wt,0), (int)val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		hwwrite(vortex->mmio, WT_PARM(wt, 0), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		return 0xc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	case 2:		/* param 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		pr_debug( "vortex: WT SetReg(0x%x) = 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		       WT_PARM(wt,1), (int)val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		hwwrite(vortex->mmio, WT_PARM(wt, 1), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		return 0xc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	case 3:		/* param 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		pr_debug( "vortex: WT SetReg(0x%x) = 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		       WT_PARM(wt,2), (int)val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		hwwrite(vortex->mmio, WT_PARM(wt, 2), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		return 0xc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	case 4:		/* param 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		pr_debug( "vortex: WT SetReg(0x%x) = 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		       WT_PARM(wt,3), (int)val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		hwwrite(vortex->mmio, WT_PARM(wt, 3), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		return 0xc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	case 6:		/* mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		pr_debug( "vortex: WT SetReg(0x%x) = 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		       WT_MUTE(wt), (int)val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		hwwrite(vortex->mmio, WT_MUTE(wt), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		return 0xc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	case 0xb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 			/* delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		pr_debug( "vortex: WT SetReg(0x%x) = 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		       WT_DELAY(wt,0), (int)val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		hwwrite(vortex->mmio, WT_DELAY(wt, 3), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		hwwrite(vortex->mmio, WT_DELAY(wt, 2), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		hwwrite(vortex->mmio, WT_DELAY(wt, 1), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		hwwrite(vortex->mmio, WT_DELAY(wt, 0), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		return 0xc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		/* Global WT block parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	case 5:		/* sramp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		ecx = WT_SRAMP(wt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	case 8:		/* aramp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		ecx = WT_ARAMP(wt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	case 9:		/* mramp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		ecx = WT_MRAMP(wt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	case 0xa:		/* ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		ecx = WT_CTRL(wt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	case 0xc:		/* ds_reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		ecx = WT_DSREG(wt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	pr_debug( "vortex: WT SetReg(0x%x) = 0x%08x\n", ecx, (int)val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	hwwrite(vortex->mmio, ecx, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static void vortex_wt_init(vortex_t * vortex)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	u32 var4, var8, varc, var10 = 0, edi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	var10 &= 0xFFFFFFE3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	var10 |= 0x22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	var10 &= 0xFFFFFEBF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	var10 |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	var10 |= 0x200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	var10 &= 0xfffffffe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	var10 &= 0xfffffbff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	var10 |= 0x1800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	// var10 = 0x1AA2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	var4 = 0x10000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	varc = 0x00830000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	var8 = 0x00830000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	/* Init Bank registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	for (edi = 0; edi < (NR_WT / NR_WT_PB); edi++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		vortex_wt_SetReg(vortex, 0xc, edi, 0);	/* ds_reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		vortex_wt_SetReg(vortex, 0xa, edi, var10);	/* ctrl  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		vortex_wt_SetReg(vortex, 0x9, edi, var4);	/* mramp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		vortex_wt_SetReg(vortex, 0x8, edi, varc);	/* aramp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		vortex_wt_SetReg(vortex, 0x5, edi, var8);	/* sramp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	/* Init Voice registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	for (edi = 0; edi < NR_WT; edi++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		vortex_wt_SetReg(vortex, 0x4, edi, 0);	/* param 3 0x20c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		vortex_wt_SetReg(vortex, 0x3, edi, 0);	/* param 2 0x208 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		vortex_wt_SetReg(vortex, 0x2, edi, 0);	/* param 1 0x204 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		vortex_wt_SetReg(vortex, 0x1, edi, 0);	/* param 0 0x200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		vortex_wt_SetReg(vortex, 0xb, edi, 0);	/* delay 0x400 - 0x40c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	var10 |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	for (edi = 0; edi < (NR_WT / NR_WT_PB); edi++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		vortex_wt_SetReg(vortex, 0xa, edi, var10);	/* ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* Extract of CAdbTopology::SetVolume(struct _ASPVOLUME *) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static void vortex_wt_SetVolume(vortex_t * vortex, int wt, int vol[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	wt_voice_t *voice = &(vortex->wt_voice[wt]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	int ecx = vol[1], eax = vol[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	/* This is pure guess */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	voice->parm0 &= 0xff00ffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	voice->parm0 |= (vol[0] & 0xff) << 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	voice->parm1 &= 0xff00ffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	voice->parm1 |= (vol[1] & 0xff) << 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	/* This is real */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	hwwrite(vortex, WT_PARM(wt, 0), voice->parm0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	hwwrite(vortex, WT_PARM(wt, 1), voice->parm0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	if (voice->this_1D0 & 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		eax >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		ecx = eax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		if (ecx < 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 			ecx = 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		voice->parm3 &= 0xFFFFC07F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		voice->parm3 |= (ecx & 0x7f) << 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		voice->parm3 &= 0xFFFFFF80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		voice->parm3 |= (eax & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		voice->parm3 &= 0xFFE03FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		voice->parm3 |= (eax & 0xFE00) << 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	hwwrite(vortex, WT_PARM(wt, 3), voice->parm3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* Extract of CAdbTopology::SetFrequency(unsigned long arg_0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static void vortex_wt_SetFrequency(vortex_t * vortex, int wt, unsigned int sr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	wt_voice_t *voice = &(vortex->wt_voice[wt]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	u32 eax, edx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	//FIXME: 64 bit operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	eax = ((sr << 0xf) * 0x57619F1) & 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	edx = (((sr << 0xf) * 0x57619F1)) >> 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	edx >>= 0xa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	edx <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	if (edx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		if (edx & 0x0FFF80000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 			eax = 0x7fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 			edx <<= 0xd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 			eax = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 			while ((edx & 0x80000000) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 				edx <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 				eax--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 				if (eax == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 					break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 			if (eax)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 				edx <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 			eax <<= 0xc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 			edx >>= 0x14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 			eax |= edx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	} else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		eax = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	voice->parm0 &= 0xffff0001;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	voice->parm0 |= (eax & 0x7fff) << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	voice->parm1 = voice->parm0 | 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	// Wt: this_1D4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	//AuWt::WriteReg((ulong)(this_1DC<<4)+0x200, (ulong)this_1E4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	//AuWt::WriteReg((ulong)(this_1DC<<4)+0x204, (ulong)this_1E8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	hwwrite(vortex->mmio, WT_PARM(wt, 0), voice->parm0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	hwwrite(vortex->mmio, WT_PARM(wt, 1), voice->parm1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* End of File */