^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Vortex PCM ALSA driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Supports ADB and WT DMA. Unfortunately, WT channels do not run yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * It remains stuck,and DMA transfers do not happen.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <sound/asoundef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "au88x0.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define VORTEX_PCM_TYPE(x) (x->name[40])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* hardware definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static const struct snd_pcm_hardware snd_vortex_playback_hw_adb = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) .info =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) (SNDRV_PCM_INFO_MMAP | /* SNDRV_PCM_INFO_RESUME | */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) SNDRV_PCM_INFO_MMAP_VALID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .formats =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .rates = SNDRV_PCM_RATE_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .rate_min = 5000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .buffer_bytes_max = 0x10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .period_bytes_min = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .period_bytes_max = 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .periods_max = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #ifndef CHIP_AU8820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static const struct snd_pcm_hardware snd_vortex_playback_hw_a3d = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .info =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) (SNDRV_PCM_INFO_MMAP | /* SNDRV_PCM_INFO_RESUME | */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) SNDRV_PCM_INFO_MMAP_VALID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .formats =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .rates = SNDRV_PCM_RATE_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .rate_min = 5000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .channels_max = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .buffer_bytes_max = 0x10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .period_bytes_min = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .period_bytes_max = 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .periods_max = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static const struct snd_pcm_hardware snd_vortex_playback_hw_spdif = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .info =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) (SNDRV_PCM_INFO_MMAP | /* SNDRV_PCM_INFO_RESUME | */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) SNDRV_PCM_INFO_MMAP_VALID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .formats =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE | SNDRV_PCM_FMTBIT_MU_LAW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) SNDRV_PCM_FMTBIT_A_LAW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .rates =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .rate_min = 32000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .buffer_bytes_max = 0x10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .period_bytes_min = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .period_bytes_max = 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .periods_max = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #ifndef CHIP_AU8810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static const struct snd_pcm_hardware snd_vortex_playback_hw_wt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .info = (SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP_VALID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_CONTINUOUS, // SNDRV_PCM_RATE_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .rate_min = 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .buffer_bytes_max = 0x10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .period_bytes_min = 0x0400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .period_bytes_max = 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .periods_max = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #ifdef CHIP_AU8830
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static const unsigned int au8830_channels[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 1, 2, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static const struct snd_pcm_hw_constraint_list hw_constraints_au8830_channels = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .count = ARRAY_SIZE(au8830_channels),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .list = au8830_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static void vortex_notify_pcm_vol_change(struct snd_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct snd_kcontrol *kctl, int activate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (activate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) kctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) kctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) snd_ctl_notify(card, SNDRV_CTL_EVENT_MASK_VALUE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) SNDRV_CTL_EVENT_MASK_INFO, &(kctl->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* open callback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int snd_vortex_pcm_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) vortex_t *vortex = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Force equal size periods */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if ((err =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) snd_pcm_hw_constraint_integer(runtime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Avoid PAGE_SIZE boundary to fall inside of a period. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if ((err =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) snd_pcm_hw_constraint_pow2(runtime, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) SNDRV_PCM_HW_PARAM_PERIOD_BYTES)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) snd_pcm_hw_constraint_step(runtime, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (VORTEX_PCM_TYPE(substream->pcm) != VORTEX_PCM_WT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #ifndef CHIP_AU8820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (VORTEX_PCM_TYPE(substream->pcm) == VORTEX_PCM_A3D) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) runtime->hw = snd_vortex_playback_hw_a3d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (VORTEX_PCM_TYPE(substream->pcm) == VORTEX_PCM_SPDIF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) runtime->hw = snd_vortex_playback_hw_spdif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) switch (vortex->spdif_sr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) case 32000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) runtime->hw.rates = SNDRV_PCM_RATE_32000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) case 44100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) runtime->hw.rates = SNDRV_PCM_RATE_44100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) case 48000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) runtime->hw.rates = SNDRV_PCM_RATE_48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (VORTEX_PCM_TYPE(substream->pcm) == VORTEX_PCM_ADB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) || VORTEX_PCM_TYPE(substream->pcm) == VORTEX_PCM_I2S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) runtime->hw = snd_vortex_playback_hw_adb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #ifdef CHIP_AU8830
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) VORTEX_IS_QUAD(vortex) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) VORTEX_PCM_TYPE(substream->pcm) == VORTEX_PCM_ADB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) runtime->hw.channels_max = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) snd_pcm_hw_constraint_list(runtime, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) SNDRV_PCM_HW_PARAM_CHANNELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) &hw_constraints_au8830_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) substream->runtime->private_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #ifndef CHIP_AU8810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) runtime->hw = snd_vortex_playback_hw_wt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) substream->runtime->private_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* close callback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static int snd_vortex_pcm_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) //vortex_t *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) stream_t *stream = (stream_t *) substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) // the hardware-specific codes will be here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (stream != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) stream->substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) stream->nr_ch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) substream->runtime->private_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* hw_params callback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) snd_vortex_pcm_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct snd_pcm_hw_params *hw_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) vortex_t *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) stream_t *stream = (stream_t *) (substream->runtime->private_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) pr_info( "Vortex: periods %d, period_bytes %d, channels = %d\n", params_periods(hw_params),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) params_period_bytes(hw_params), params_channels(hw_params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) spin_lock_irq(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) // Make audio routes and config buffer DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (VORTEX_PCM_TYPE(substream->pcm) != VORTEX_PCM_WT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int dma, type = VORTEX_PCM_TYPE(substream->pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* Dealloc any routes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (stream != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) vortex_adb_allocroute(chip, stream->dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) stream->nr_ch, stream->dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) stream->type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) substream->number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* Alloc routes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) dma =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) vortex_adb_allocroute(chip, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) params_channels(hw_params),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) substream->stream, type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) substream->number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (dma < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) spin_unlock_irq(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) stream = substream->runtime->private_data = &chip->dma_adb[dma];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) stream->substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* Setup Buffers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) vortex_adbdma_setbuffers(chip, dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) params_period_bytes(hw_params),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) params_periods(hw_params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (VORTEX_PCM_TYPE(substream->pcm) == VORTEX_PCM_ADB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) chip->pcm_vol[substream->number].active = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) vortex_notify_pcm_vol_change(chip->card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) chip->pcm_vol[substream->number].kctl, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #ifndef CHIP_AU8810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* if (stream != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) vortex_wt_allocroute(chip, substream->number, 0); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) vortex_wt_allocroute(chip, substream->number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) params_channels(hw_params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) stream = substream->runtime->private_data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) &chip->dma_wt[substream->number];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) stream->dma = substream->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) stream->substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) vortex_wtdma_setbuffers(chip, substream->number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) params_period_bytes(hw_params),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) params_periods(hw_params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) spin_unlock_irq(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* hw_free callback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int snd_vortex_pcm_hw_free(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) vortex_t *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) stream_t *stream = (stream_t *) (substream->runtime->private_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) spin_lock_irq(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) // Delete audio routes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (VORTEX_PCM_TYPE(substream->pcm) != VORTEX_PCM_WT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (stream != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (VORTEX_PCM_TYPE(substream->pcm) == VORTEX_PCM_ADB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) chip->pcm_vol[substream->number].active = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) vortex_notify_pcm_vol_change(chip->card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) chip->pcm_vol[substream->number].kctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) vortex_adb_allocroute(chip, stream->dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) stream->nr_ch, stream->dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) stream->type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) substream->number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #ifndef CHIP_AU8810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (stream != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) vortex_wt_allocroute(chip, stream->dma, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) substream->runtime->private_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) spin_unlock_irq(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* prepare callback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static int snd_vortex_pcm_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) vortex_t *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) stream_t *stream = (stream_t *) substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int dma = stream->dma, fmt, dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) // set up the hardware with the current configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) dir = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) dir = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) fmt = vortex_alsafmt_aspfmt(runtime->format, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) spin_lock_irq(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (VORTEX_PCM_TYPE(substream->pcm) != VORTEX_PCM_WT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) vortex_adbdma_setmode(chip, dma, 1, dir, fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) runtime->channels == 1 ? 0 : 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) vortex_adbdma_setstartbuffer(chip, dma, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (VORTEX_PCM_TYPE(substream->pcm) != VORTEX_PCM_SPDIF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) vortex_adb_setsrc(chip, dma, runtime->rate, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #ifndef CHIP_AU8810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) vortex_wtdma_setmode(chip, dma, 1, fmt, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) // FIXME: Set rate (i guess using vortex_wt_writereg() somehow).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) vortex_wtdma_setstartbuffer(chip, dma, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) spin_unlock_irq(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* trigger callback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int snd_vortex_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) vortex_t *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) stream_t *stream = (stream_t *) substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) int dma = stream->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) spin_lock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) // do something to start the PCM engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) //printk(KERN_INFO "vortex: start %d\n", dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) stream->fifo_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (VORTEX_PCM_TYPE(substream->pcm) != VORTEX_PCM_WT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) vortex_adbdma_resetup(chip, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) vortex_adbdma_startfifo(chip, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #ifndef CHIP_AU8810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) dev_info(chip->card->dev, "wt start %d\n", dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) vortex_wtdma_startfifo(chip, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) // do something to stop the PCM engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) //printk(KERN_INFO "vortex: stop %d\n", dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) stream->fifo_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (VORTEX_PCM_TYPE(substream->pcm) != VORTEX_PCM_WT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) vortex_adbdma_stopfifo(chip, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #ifndef CHIP_AU8810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) dev_info(chip->card->dev, "wt stop %d\n", dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) vortex_wtdma_stopfifo(chip, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) //printk(KERN_INFO "vortex: pause %d\n", dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (VORTEX_PCM_TYPE(substream->pcm) != VORTEX_PCM_WT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) vortex_adbdma_pausefifo(chip, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #ifndef CHIP_AU8810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) vortex_wtdma_pausefifo(chip, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) //printk(KERN_INFO "vortex: resume %d\n", dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (VORTEX_PCM_TYPE(substream->pcm) != VORTEX_PCM_WT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) vortex_adbdma_resumefifo(chip, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #ifndef CHIP_AU8810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) vortex_wtdma_resumefifo(chip, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) spin_unlock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) spin_unlock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* pointer callback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static snd_pcm_uframes_t snd_vortex_pcm_pointer(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) vortex_t *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) stream_t *stream = (stream_t *) substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) int dma = stream->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) snd_pcm_uframes_t current_ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) spin_lock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (VORTEX_PCM_TYPE(substream->pcm) != VORTEX_PCM_WT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) current_ptr = vortex_adbdma_getlinearpos(chip, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #ifndef CHIP_AU8810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) current_ptr = vortex_wtdma_getlinearpos(chip, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) //printk(KERN_INFO "vortex: pointer = 0x%x\n", current_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) spin_unlock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) current_ptr = bytes_to_frames(substream->runtime, current_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (current_ptr >= substream->runtime->buffer_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) current_ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return current_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* operators */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static const struct snd_pcm_ops snd_vortex_playback_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .open = snd_vortex_pcm_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .close = snd_vortex_pcm_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .hw_params = snd_vortex_pcm_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .hw_free = snd_vortex_pcm_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .prepare = snd_vortex_pcm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .trigger = snd_vortex_pcm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .pointer = snd_vortex_pcm_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * definitions of capture are omitted here...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static const char * const vortex_pcm_prettyname[VORTEX_PCM_LAST] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) CARD_NAME " ADB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) CARD_NAME " SPDIF",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) CARD_NAME " A3D",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) CARD_NAME " WT",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) CARD_NAME " I2S",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static const char * const vortex_pcm_name[VORTEX_PCM_LAST] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) "adb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) "spdif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) "a3d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) "wt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) "i2s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* SPDIF kcontrol */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static int snd_vortex_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static int snd_vortex_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ucontrol->value.iec958.status[0] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) ucontrol->value.iec958.status[1] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ucontrol->value.iec958.status[2] = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static int snd_vortex_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) vortex_t *vortex = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) ucontrol->value.iec958.status[0] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) ucontrol->value.iec958.status[1] = IEC958_AES1_CON_ORIGINAL|IEC958_AES1_CON_DIGDIGCONV_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ucontrol->value.iec958.status[2] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) switch (vortex->spdif_sr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) case 32000: ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS_32000; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) case 44100: ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS_44100; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) case 48000: ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS_48000; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static int snd_vortex_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) vortex_t *vortex = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) int spdif_sr = 48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) switch (ucontrol->value.iec958.status[3] & IEC958_AES3_CON_FS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) case IEC958_AES3_CON_FS_32000: spdif_sr = 32000; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) case IEC958_AES3_CON_FS_44100: spdif_sr = 44100; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) case IEC958_AES3_CON_FS_48000: spdif_sr = 48000; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (spdif_sr == vortex->spdif_sr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) vortex->spdif_sr = spdif_sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) vortex_spdif_init(vortex, vortex->spdif_sr, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* spdif controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static const struct snd_kcontrol_new snd_vortex_mixer_spdif[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .info = snd_vortex_spdif_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .get = snd_vortex_spdif_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .put = snd_vortex_spdif_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .access = SNDRV_CTL_ELEM_ACCESS_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .info = snd_vortex_spdif_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .get = snd_vortex_spdif_mask_get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* subdevice PCM Volume control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static int snd_vortex_pcm_vol_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) vortex_t *vortex = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) uinfo->count = (VORTEX_IS_QUAD(vortex) ? 4 : 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) uinfo->value.integer.min = -128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) uinfo->value.integer.max = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static int snd_vortex_pcm_vol_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) vortex_t *vortex = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) int subdev = kcontrol->id.subdevice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct pcm_vol *p = &vortex->pcm_vol[subdev];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) int max_chn = (VORTEX_IS_QUAD(vortex) ? 4 : 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) for (i = 0; i < max_chn; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ucontrol->value.integer.value[i] = p->vol[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static int snd_vortex_pcm_vol_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) int changed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) int mixin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) unsigned char vol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) vortex_t *vortex = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) int subdev = kcontrol->id.subdevice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct pcm_vol *p = &vortex->pcm_vol[subdev];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) int max_chn = (VORTEX_IS_QUAD(vortex) ? 4 : 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) for (i = 0; i < max_chn; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (p->vol[i] != ucontrol->value.integer.value[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) p->vol[i] = ucontrol->value.integer.value[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (p->active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) switch (vortex->dma_adb[p->dma].nr_ch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) mixin = p->mixin[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) mixin = p->mixin[(i < 2) ? i : (i - 2)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) mixin = p->mixin[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) vol = p->vol[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) vortex_mix_setinputvolumebyte(vortex,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) vortex->mixplayb[i], mixin, vol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) changed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static const DECLARE_TLV_DB_MINMAX(vortex_pcm_vol_db_scale, -9600, 2400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static const struct snd_kcontrol_new snd_vortex_pcm_vol = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .name = "PCM Playback Volume",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) SNDRV_CTL_ELEM_ACCESS_TLV_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) SNDRV_CTL_ELEM_ACCESS_INACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .info = snd_vortex_pcm_vol_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .get = snd_vortex_pcm_vol_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .put = snd_vortex_pcm_vol_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .tlv = { .p = vortex_pcm_vol_db_scale },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* create a pcm device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static int snd_vortex_new_pcm(vortex_t *chip, int idx, int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) struct snd_kcontrol *kctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) int err, nr_capt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (!chip || idx < 0 || idx >= VORTEX_PCM_LAST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /* idx indicates which kind of PCM device. ADB, SPDIF, I2S and A3D share the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * same dma engine. WT uses it own separate dma engine which can't capture. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (idx == VORTEX_PCM_ADB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) nr_capt = nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) nr_capt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) err = snd_pcm_new(chip->card, vortex_pcm_prettyname[idx], idx, nr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) nr_capt, &pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) snprintf(pcm->name, sizeof(pcm->name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) "%s %s", CARD_NAME_SHORT, vortex_pcm_name[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) chip->pcm[idx] = pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) // This is an evil hack, but it saves a lot of duplicated code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) VORTEX_PCM_TYPE(pcm) = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) pcm->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /* set operators */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) &snd_vortex_playback_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (idx == VORTEX_PCM_ADB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) &snd_vortex_playback_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /* pre-allocation of Scatter-Gather buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) &chip->pci_dev->dev, 0x10000, 0x10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) switch (VORTEX_PCM_TYPE(pcm)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) case VORTEX_PCM_ADB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) snd_pcm_std_chmaps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) VORTEX_IS_QUAD(chip) ? 4 : 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_CAPTURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) snd_pcm_std_chmaps, 2, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #ifdef CHIP_AU8830
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) case VORTEX_PCM_A3D:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) snd_pcm_std_chmaps, 1, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (VORTEX_PCM_TYPE(pcm) == VORTEX_PCM_SPDIF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) for (i = 0; i < ARRAY_SIZE(snd_vortex_mixer_spdif); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) kctl = snd_ctl_new1(&snd_vortex_mixer_spdif[i], chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (!kctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if ((err = snd_ctl_add(chip->card, kctl)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (VORTEX_PCM_TYPE(pcm) == VORTEX_PCM_ADB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) for (i = 0; i < NR_PCM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) chip->pcm_vol[i].active = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) chip->pcm_vol[i].dma = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) kctl = snd_ctl_new1(&snd_vortex_pcm_vol, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (!kctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) chip->pcm_vol[i].kctl = kctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) kctl->id.device = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) kctl->id.subdevice = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) err = snd_ctl_add(chip->card, kctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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