^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef AU88X0_EQ_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define AU88X0_EQ_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * au88x0_eq.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Definitions and constant data for the Aureal Hardware EQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Sun Jun 8 18:23:38 2003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Author: Manuel Jander (mjander@users.sourceforge.net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) u16 LeftCoefs[50]; //0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) u16 RightCoefs[50]; // 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) u16 LeftGains[10]; //0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) u16 RightGains[10]; //0xe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) } auxxEqCoeffSet_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) s32 this04; /* How many filters for each side (default = 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) s32 this08; /* inited to cero. Stereo flag? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) } eqhw_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) eqhw_t this04; /* CHwEq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u16 this08; /* Bad codec flag ? SetBypassGain: bypass gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u16 this0a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u16 this0c; /* SetBypassGain: bypass gain when this28 is not set. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u16 this0e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) s32 this10; /* How many gains are used for each side (right or left). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u16 this14_array[10]; /* SetLeftGainsTarget: Left (and right?) EQ gains */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) s32 this28; /* flag related to EQ enabled or not. Gang flag ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) s32 this54; /* SetBypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) s32 this58;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) s32 this5c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /*0x60 */ auxxEqCoeffSet_t coefset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* 50 u16 word each channel. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u16 this130[20]; /* Left and Right gains */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) } eqlzr_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #endif