^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /***************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * au88x0_a3d.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Fri Jul 18 14:16:03 2003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2003 mjander
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * mjander@users.sourceforge.net
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) ****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifndef _AU88X0_A3D_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define _AU88X0_A3D_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) //#include <openal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define HRTF_SZ 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DLINE_SZ 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CTRLID_HRTF 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CTRLID_ITD 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CTRLID_ILD 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CTRLID_FILTER 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CTRLID_GAINS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* 3D parameter structs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) typedef unsigned short int a3d_Hrtf_t[HRTF_SZ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) typedef unsigned short int a3d_ItdDline_t[DLINE_SZ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) typedef unsigned short int a3d_atmos_t[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) typedef unsigned short int a3d_LRGains_t[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) typedef unsigned short int a3d_Itd_t[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) typedef unsigned short int a3d_Ild_t[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) void *vortex; // Formerly CAsp4HwIO*, now vortex_t*.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned int source; /* this_04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned int slice; /* this_08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) a3d_Hrtf_t hrtf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) a3d_Itd_t itd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) a3d_Ild_t ild;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) a3d_ItdDline_t dline;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) a3d_atmos_t filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) } a3dsrc_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* First Register bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define A3D_A_HrtfCurrent 0x18000 /* 56 ULONG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define A3D_A_GainCurrent 0x180E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define A3D_A_GainTarget 0x180E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define A3D_A_A12Current 0x180E8 /* Atmospheric current. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define A3D_A_A21Target 0x180EC /* Atmospheric target */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define A3D_A_B01Current 0x180F0 /* Atmospheric current */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define A3D_A_B10Target 0x180F4 /* Atmospheric target */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define A3D_A_B2Current 0x180F8 /* Atmospheric current */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define A3D_A_B2Target 0x180FC /* Atmospheric target */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define A3D_A_HrtfTarget 0x18100 /* 56 ULONG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define A3D_A_ITDCurrent 0x181E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define A3D_A_ITDTarget 0x181E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define A3D_A_HrtfDelayLine 0x181E8 /* 56 ULONG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define A3D_A_ITDDelayLine 0x182C8 /* 40/45 ULONG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define A3D_A_HrtfTrackTC 0x1837C /* Time Constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define A3D_A_GainTrackTC 0x18380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define A3D_A_CoeffTrackTC 0x18384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define A3D_A_ITDTrackTC 0x18388
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define A3D_A_x1 0x1838C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define A3D_A_x2 0x18390
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define A3D_A_y1 0x18394
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define A3D_A_y2 0x18398
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define A3D_A_HrtfOutL 0x1839C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define A3D_A_HrtfOutR 0x183A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define A3D_A_TAIL 0x183A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Second register bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define A3D_B_HrtfCurrent 0x19000 /* 56 ULONG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define A3D_B_GainCurrent 0x190E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define A3D_B_GainTarget 0x190E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define A3D_B_A12Current 0x190E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define A3D_B_A21Target 0x190EC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define A3D_B_B01Current 0x190F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define A3D_B_B10Target 0x190F4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define A3D_B_B2Current 0x190F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define A3D_B_B2Target 0x190FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define A3D_B_HrtfTarget 0x19100 /* 56 ULONG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define A3D_B_ITDCurrent 0x191E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define A3D_B_ITDTarget 0x191E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define A3D_B_HrtfDelayLine 0x191E8 /* 56 ULONG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define A3D_B_TAIL 0x192C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* There are 4 slices, 4 a3d each = 16 a3d sources. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define A3D_SLICE_BANK_A 0x18000 /* 4 sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define A3D_SLICE_BANK_B 0x19000 /* 4 sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define A3D_SLICE_VDBDest 0x19C00 /* 8 ULONG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define A3D_SLICE_VDBSource 0x19C20 /* 4 ULONG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define A3D_SLICE_ABReg 0x19C30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define A3D_SLICE_CReg 0x19C34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define A3D_SLICE_Control 0x19C38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define A3D_SLICE_DebugReserved 0x19C3c /* Dangerous! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define A3D_SLICE_Pointers 0x19C40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define A3D_SLICE_TAIL 0x1A000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) // Slice size: 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) // Source size: 0x3A4, 0x2C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Address generator macro. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define a3d_addrA(slice,source,reg) (((slice)<<0xd)+((source)*0x3A4)+(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define a3d_addrB(slice,source,reg) (((slice)<<0xd)+((source)*0x2C8)+(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define a3d_addrS(slice,reg) (((slice)<<0xd)+(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) //#define a3d_addr(slice,source,reg) (((reg)>=0x19000) ? a3d_addr2((slice),(source),(reg)) : a3d_addr1((slice),(source),(reg)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #endif /* _AU88X0_A3D_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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