Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #ifndef __SOUND_AU88X0_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #define __SOUND_AU88X0_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <sound/rawmidi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <sound/mpu401.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <sound/hwdep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <sound/ac97_codec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <sound/tlv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #ifndef CHIP_AU8820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include "au88x0_eq.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include "au88x0_a3d.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #ifndef CHIP_AU8810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include "au88x0_wt.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define	hwread(x,y) readl((x)+(y))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define	hwwrite(x,y,z) writel((z),(x)+(y))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) /* Vortex MPU401 defines. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define	MIDI_CLOCK_DIV		0x61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /* Standart MPU401 defines. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define	MPU401_RESET		0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define	MPU401_ENTER_UART	0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define	MPU401_ACK		0xfe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) // Get src register value to convert from x to y.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define	SRC_RATIO(x,y)		((((x<<15)/y) + 1)/2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) /* FIFO software state constants. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define FIFO_STOP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define FIFO_START 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define FIFO_PAUSE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) /* IRQ flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define IRQ_ERR_MASK	0x00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define IRQ_FATAL	0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define IRQ_PARITY	0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define IRQ_REG		0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define IRQ_FIFO	0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define IRQ_DMA		0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define IRQ_PCMOUT	0x0020	/* PCM OUT page crossing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define IRQ_TIMER	0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define IRQ_MIDI	0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define IRQ_MODEM	0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) /* ADB Resource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define VORTEX_RESOURCE_DMA	0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define VORTEX_RESOURCE_SRC	0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define VORTEX_RESOURCE_MIXIN	0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define VORTEX_RESOURCE_MIXOUT	0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define VORTEX_RESOURCE_A3D	0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define VORTEX_RESOURCE_LAST	0x00000005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) /* codec io: VORTEX_CODEC_IO bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define VORTEX_CODEC_ID_SHIFT	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define VORTEX_CODEC_WRITE	0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define VORTEX_CODEC_ADDSHIFT 	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define VORTEX_CODEC_ADDMASK	0x7f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define VORTEX_CODEC_DATSHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define VORTEX_CODEC_DATMASK	0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) /* Check for SDAC bit in "Extended audio ID" AC97 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) //#define VORTEX_IS_QUAD(x) (((x)->codec == NULL) ?  0 : ((x)->codec->ext_id&0x80))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define VORTEX_IS_QUAD(x) ((x)->isquad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) /* Check if chip has bug. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define IS_BAD_CHIP(x) (\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	(x->rev == 0xfe && x->device == PCI_DEVICE_ID_AUREAL_VORTEX_2) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	(x->rev == 0xfe && x->device == PCI_DEVICE_ID_AUREAL_ADVANTAGE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) /* PCM devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define VORTEX_PCM_ADB		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define VORTEX_PCM_SPDIF	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define VORTEX_PCM_A3D		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define VORTEX_PCM_WT		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define VORTEX_PCM_I2S		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define VORTEX_PCM_LAST		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define MIX_CAPT(x) (vortex->mixcapt[x])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define MIX_PLAYB(x) (vortex->mixplayb[x])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define MIX_SPDIF(x) (vortex->mixspdif[x])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define NR_WTPB 0x20		/* WT channels per each bank. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define NR_PCM	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) struct pcm_vol {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	struct snd_kcontrol *kctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	int active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	int dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	int mixin[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	int vol[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Structs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	//int this_08;          /* Still unknown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	int fifo_enabled;	/* this_24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	int fifo_status;	/* this_1c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	u32 dma_ctrl;		/* this_78 (ADB), this_7c (WT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	int dma_unknown;	/* this_74 (ADB), this_78 (WT). WDM: +8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	int cfg0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	int cfg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	int nr_ch;		/* Nr of PCM channels in use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	int type;		/* Output type (ac97, a3d, spdif, i2s, dsp) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	int dma;		/* Hardware DMA index. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	int dir;		/* Stream Direction. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	u32 resources[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	/* Virtual page extender stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	int nr_periods;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	int period_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	int period_real;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	int period_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	struct snd_pcm_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) } stream_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) typedef struct snd_vortex vortex_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct snd_vortex {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	/* ALSA structs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	struct snd_pcm *pcm[VORTEX_PCM_LAST];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	struct snd_rawmidi *rmidi;	/* Legacy Midi interface. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	struct snd_ac97 *codec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	/* Stream structs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	stream_t dma_adb[NR_ADB];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	int spdif_sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #ifndef CHIP_AU8810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	stream_t dma_wt[NR_WT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	wt_voice_t wt_voice[NR_WT];	/* WT register cache. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	char mixwt[(NR_WT / NR_WTPB) * 6];	/* WT mixin objects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	/* Global resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	s8 mixcapt[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	s8 mixplayb[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #ifndef CHIP_AU8820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	s8 mixspdif[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	s8 mixa3d[2];	/* mixers which collect all a3d streams. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	s8 mixxtlk[2];	/* crosstalk canceler mixer inputs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	u32 fixed_res[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #ifndef CHIP_AU8820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	/* Hardware equalizer structs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	eqlzr_t eq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	/* A3D structs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	a3dsrc_t a3d[NR_A3D];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	/* Xtalk canceler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	int xt_mode;		/* 1: speakers, 0:headphones. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	struct pcm_vol pcm_vol[NR_PCM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	int isquad;		/* cache of extended ID codec flag. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	/* Gameport stuff. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	struct gameport *gameport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	/* PCI hardware resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	unsigned long io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	void __iomem *mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	/* PCI device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	struct pci_dev *pci_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	u16 vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	u16 device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	u8 rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* Functions. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* SRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static void vortex_adb_setsrc(vortex_t * vortex, int adbdma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			      unsigned int cvrt, int dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* DMA Engines. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static void vortex_adbdma_setbuffers(vortex_t * vortex, int adbdma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 				     int size, int count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static void vortex_adbdma_setmode(vortex_t * vortex, int adbdma, int ie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 				  int dir, int fmt, int d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 				  u32 offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static void vortex_adbdma_setstartbuffer(vortex_t * vortex, int adbdma, int sb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #ifndef CHIP_AU8810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static void vortex_wtdma_setbuffers(vortex_t * vortex, int wtdma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 				    int size, int count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static void vortex_wtdma_setmode(vortex_t * vortex, int wtdma, int ie, int fmt, int d,	/*int e, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 				 u32 offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static void vortex_wtdma_setstartbuffer(vortex_t * vortex, int wtdma, int sb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static void vortex_adbdma_startfifo(vortex_t * vortex, int adbdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) //static void vortex_adbdma_stopfifo(vortex_t *vortex, int adbdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static void vortex_adbdma_pausefifo(vortex_t * vortex, int adbdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static void vortex_adbdma_resumefifo(vortex_t * vortex, int adbdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static inline int vortex_adbdma_getlinearpos(vortex_t * vortex, int adbdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static void vortex_adbdma_resetup(vortex_t *vortex, int adbdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #ifndef CHIP_AU8810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static void vortex_wtdma_startfifo(vortex_t * vortex, int wtdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static void vortex_wtdma_stopfifo(vortex_t * vortex, int wtdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static void vortex_wtdma_pausefifo(vortex_t * vortex, int wtdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static void vortex_wtdma_resumefifo(vortex_t * vortex, int wtdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static inline int vortex_wtdma_getlinearpos(vortex_t * vortex, int wtdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* global stuff. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static void vortex_codec_init(vortex_t * vortex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static void vortex_codec_write(struct snd_ac97 * codec, unsigned short addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 			       unsigned short data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static unsigned short vortex_codec_read(struct snd_ac97 * codec, unsigned short addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static void vortex_spdif_init(vortex_t * vortex, int spdif_sr, int spdif_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static int vortex_core_init(vortex_t * card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static int vortex_core_shutdown(vortex_t * card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static void vortex_enable_int(vortex_t * card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static irqreturn_t vortex_interrupt(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static int vortex_alsafmt_aspfmt(snd_pcm_format_t alsafmt, vortex_t *v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* Connection  stuff. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static void vortex_connect_default(vortex_t * vortex, int en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static int vortex_adb_allocroute(vortex_t * vortex, int dma, int nr_ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 				 int dir, int type, int subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static char vortex_adb_checkinout(vortex_t * vortex, int resmap[], int out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 				  int restype);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #ifndef CHIP_AU8810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static int vortex_wt_allocroute(vortex_t * vortex, int dma, int nr_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static void vortex_wt_connect(vortex_t * vortex, int en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static void vortex_wt_init(vortex_t * vortex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static void vortex_route(vortex_t * vortex, int en, unsigned char channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 			 unsigned char source, unsigned char dest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static void vortex_routes(vortex_t * vortex, int en, unsigned char channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 			  unsigned char source, unsigned char dest0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 			  unsigned char dest1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static void vortex_connection_mixin_mix(vortex_t * vortex, int en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 					unsigned char mixin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 					unsigned char mix, int a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static void vortex_mix_setinputvolumebyte(vortex_t * vortex,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 					  unsigned char mix, int mixin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 					  unsigned char vol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static void vortex_mix_setvolumebyte(vortex_t * vortex, unsigned char mix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 				     unsigned char vol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* A3D functions. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #ifndef CHIP_AU8820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static void vortex_Vort3D_enable(vortex_t * v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static void vortex_Vort3D_disable(vortex_t * v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static void vortex_Vort3D_connect(vortex_t * vortex, int en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static void vortex_Vort3D_InitializeSource(a3dsrc_t *a, int en, vortex_t *v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* Driver stuff. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static int vortex_gameport_register(vortex_t * card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static void vortex_gameport_unregister(vortex_t * card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #ifndef CHIP_AU8820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static int vortex_eq_init(vortex_t * vortex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static int vortex_eq_free(vortex_t * vortex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* ALSA stuff. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static int snd_vortex_new_pcm(vortex_t * vortex, int idx, int nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static int snd_vortex_mixer(vortex_t * vortex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static int snd_vortex_midi(vortex_t * vortex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #endif