Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)     Aureal Vortex Soundcard driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)     IO addr collected from asp4core.vxd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)     function    address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)     0005D5A0    13004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)     00080674    14004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)     00080AFF    12818
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define CHIP_AU8830
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define CARD_NAME "Aureal Vortex 2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define CARD_NAME_SHORT "au8830"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define NR_ADB 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define NR_SRC 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define NR_A3D 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define NR_MIXIN 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define NR_MIXOUT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define NR_WT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) /* ADBDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define VORTEX_ADBDMA_STAT 0x27e00	/* read only, subbuffer, DMA pos */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define		POS_MASK 0x00000fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define     POS_SHIFT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define 	ADB_SUBBUF_MASK 0x00003000	/* ADB only. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define     ADB_SUBBUF_SHIFT 0xc	/* ADB only. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define VORTEX_ADBDMA_CTRL 0x27a00	/* write only; format, flags, DMA pos */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define		OFFSET_MASK 0x00000fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define     OFFSET_SHIFT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define		IE_MASK 0x00001000	/* interrupt enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define     IE_SHIFT 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define     DIR_MASK 0x00002000	/* Direction. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define     DIR_SHIFT 0xd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define		FMT_MASK 0x0003c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define		FMT_SHIFT 0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define		ADB_FIFO_EN_SHIFT	0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define		ADB_FIFO_EN			(1 << 0x15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) // The ADB masks and shift also are valid for the wtdma, except if specified otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define VORTEX_ADBDMA_BUFCFG0 0x27800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define VORTEX_ADBDMA_BUFCFG1 0x27804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define VORTEX_ADBDMA_BUFBASE 0x27400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define VORTEX_ADBDMA_START 0x27c00	/* Which subbuffer starts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define VORTEX_ADBDMA_STATUS 0x27A90	/* stored at AdbDma->this_10 / 2 DWORD in size. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) /* Starting at the MSB, each pair of bits seem to be the current DMA page. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) /* This current page bits are consistent (same value) with VORTEX_ADBDMA_STAT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) /* DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define VORTEX_ENGINE_CTRL 0x27ae8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define 	ENGINE_INIT 0x1380000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) /* WTDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define VORTEX_WTDMA_CTRL 0x27900	/* format, DMA pos */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define VORTEX_WTDMA_STAT 0x27d00	/* DMA subbuf, DMA pos */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define     WT_SUBBUF_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define     WT_SUBBUF_SHIFT 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define VORTEX_WTDMA_BUFBASE 0x27000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define VORTEX_WTDMA_BUFCFG0 0x27600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define VORTEX_WTDMA_BUFCFG1 0x27604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define VORTEX_WTDMA_START 0x27b00	/* which subbuffer is first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) /* ADB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define VORTEX_ADB_SR 0x28400	/* Samplerates enable/disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define VORTEX_ADB_RTBASE 0x28000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define VORTEX_ADB_RTBASE_COUNT 173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define VORTEX_ADB_CHNBASE 0x282b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define VORTEX_ADB_CHNBASE_COUNT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define 	ROUTE_MASK	0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define		SOURCE_MASK	0xff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define     ADB_MASK   0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define		ADB_SHIFT 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) /* ADB address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define		OFFSET_ADBDMA	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define		OFFSET_ADBDMAB	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define		OFFSET_SRCIN	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define		OFFSET_SRCOUT	0x20	/* ch 0x11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define		OFFSET_MIXIN	0x50	/* ch 0x11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define		OFFSET_MIXOUT	0x30	/* ch 0x11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define		OFFSET_CODECIN	0x70 /* ch 0x11 */	/* adb source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define		OFFSET_CODECOUT	0x88 /* ch 0x11 */	/* adb target */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define		OFFSET_SPORTIN	0x78	/* ch 0x13 ADB source. 2 routes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define		OFFSET_SPORTOUT	0x90	/* ch 0x13 ADB sink. 2 routes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define		OFFSET_SPDIFIN	0x7A	/* ch 0x14 ADB source. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define		OFFSET_SPDIFOUT	0x92	/* ch 0x14 ADB sink. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define		OFFSET_AC98IN	0x7c	/* ch 0x14 ADB source. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define		OFFSET_AC98OUT	0x94	/* ch 0x14 ADB sink. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define		OFFSET_EQIN		0xa0	/* ch 0x11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define		OFFSET_EQOUT	0x7e /* ch 0x11 */	/* 2 routes on ch 0x11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define		OFFSET_A3DIN	0x70	/* ADB sink. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define		OFFSET_A3DOUT	0xA6	/* ADB source. 2 routes per slice = 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define		OFFSET_WT0		0x40	/* WT bank 0 output. 0x40 - 0x65 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define		OFFSET_WT1		0x80	/* WT bank 1 output. 0x80 - 0xA5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) /* WT sources offset : 0x00-0x1f Direct stream. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) /* WT sources offset : 0x20-0x25 Mixed Output. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define		OFFSET_XTALKOUT	0x66	/* crosstalk canceller (source) 2 routes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define		OFFSET_XTALKIN	0x96	/* crosstalk canceller (sink). 10 routes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define		OFFSET_EFXOUT	0x68	/* ADB source. 8 routes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define		OFFSET_EFXIN	0x80	/* ADB sink. 8 routes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* ADB route translate helper */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define ADB_DMA(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define ADB_SRCOUT(x) (x + OFFSET_SRCOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define ADB_SRCIN(x) (x + OFFSET_SRCIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define ADB_MIXOUT(x) (x + OFFSET_MIXOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define ADB_MIXIN(x) (x + OFFSET_MIXIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define ADB_CODECIN(x) (x + OFFSET_CODECIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define ADB_CODECOUT(x) (x + OFFSET_CODECOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ADB_SPORTIN(x) (x + OFFSET_SPORTIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define ADB_SPORTOUT(x) (x + OFFSET_SPORTOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define ADB_SPDIFIN(x)	(x + OFFSET_SPDIFIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define ADB_SPDIFOUT(x)	(x + OFFSET_SPDIFOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define ADB_EQIN(x) (x + OFFSET_EQIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define ADB_EQOUT(x) (x + OFFSET_EQOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define ADB_A3DOUT(x) (x + OFFSET_A3DOUT)	/* 0x10 A3D blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define ADB_A3DIN(x) (x + OFFSET_A3DIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) //#define ADB_WTOUT(x) ((x<x20)?(x + OFFSET_WT0):(x + OFFSET_WT1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define ADB_WTOUT(x,y) (((x)==0)?((y) + OFFSET_WT0):((y) + OFFSET_WT1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define ADB_XTALKIN(x) ((x) + OFFSET_XTALKIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define ADB_XTALKOUT(x) ((x) + OFFSET_XTALKOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MIX_DEFIGAIN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MIX_DEFOGAIN 0x08	/* 0x8->6dB  (6dB = x4) 16 to 18 bit conversion? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* MIXER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define VORTEX_MIXER_SR 0x21f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define VORTEX_MIXER_CLIP 0x21f80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define VORTEX_MIXER_CHNBASE 0x21e40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define VORTEX_MIXER_RTBASE 0x21e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define 	MIXER_RTBASE_SIZE 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define VORTEX_MIX_ENIN 0x21a00	/* Input enable bits. 4 bits wide. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define VORTEX_MIX_SMP 0x21c00	/* wave data buffers. AU8820: 0x9c00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* MIX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define VORTEX_MIX_INVOL_B 0x20000	/* Input volume current */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define VORTEX_MIX_VOL_B 0x20800	/* Output Volume current */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define VORTEX_MIX_INVOL_A 0x21000	/* Input Volume target */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define VORTEX_MIX_VOL_A 0x21800	/* Output Volume target */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define 	VOL_MIN 0x80	/* Input volume when muted. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define		VOL_MAX 0x7f	/* FIXME: Not confirmed! Just guessed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* SRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define VORTEX_SRC_CHNBASE		0x26c40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define VORTEX_SRC_RTBASE		0x26c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define VORTEX_SRCBLOCK_SR		0x26cc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define VORTEX_SRC_SOURCE		0x26cc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define VORTEX_SRC_SOURCESIZE	0x26cc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Params
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	0x26e00	: 1 U0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	0x26e40	: 2 CR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	0x26e80	: 3 U3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	0x26ec0	: 4 DRIFT1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	0x26f00 : 5 U1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	0x26f40	: 6 DRIFT2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	0x26f80	: 7 U2 : Target rate, direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define VORTEX_SRC_CONVRATIO	0x26e40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define VORTEX_SRC_DRIFT0		0x26e80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define VORTEX_SRC_DRIFT1		0x26ec0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define VORTEX_SRC_DRIFT2		0x26f40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define VORTEX_SRC_U0			0x26e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define		U0_SLOWLOCK		0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define VORTEX_SRC_U1			0x26f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define VORTEX_SRC_U2			0x26f80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define VORTEX_SRC_DATA			0x26800	/* 0xc800 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define VORTEX_SRC_DATA0		0x26000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define VORTEX_FIFO_ADBCTRL 0x16100	/* Control bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define VORTEX_FIFO_WTCTRL 0x16000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define		FIFO_RDONLY	0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define		FIFO_CTRL	0x00000002	/* Allow ctrl. ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define		FIFO_VALID	0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define 	FIFO_EMPTY	0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define		FIFO_U0		0x00002000	/* Unknown. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define		FIFO_U1		0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define		FIFO_SIZE_BITS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define		FIFO_SIZE	(1<<(FIFO_SIZE_BITS))	// 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define 	FIFO_MASK	(FIFO_SIZE-1)	//0x3f    /* at shift left 0xc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define 	FIFO_BITS	0x1c400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define VORTEX_FIFO_ADBDATA 0x14000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define VORTEX_FIFO_WTDATA 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define VORTEX_FIFO_GIRT	0x17000	/* wt0, wt1, adb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define		GIRT_COUNT	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* CODEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define VORTEX_CODEC_CHN 0x29080	/* The name "CHN" is wrong. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define VORTEX_CODEC_CTRL 0x29184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define VORTEX_CODEC_IO 0x29188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define VORTEX_CODEC_SPORTCTRL 0x2918c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define VORTEX_CODEC_EN 0x29190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define		EN_AUDIO0		0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define		EN_MODEM		0x00000c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define		EN_AUDIO1		0x00003000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define		EN_SPORT		0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define		EN_SPDIF		0x000c0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define		EN_CODEC		(EN_AUDIO1 | EN_AUDIO0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define VORTEX_SPDIF_SMPRATE	0x29194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define VORTEX_SPDIF_FLAGS		0x2205c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define VORTEX_SPDIF_CFG0		0x291D0	/* status data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define VORTEX_SPDIF_CFG1		0x291D4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define VORTEX_SMP_TIME			0x29198	/* Sample counter/timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define VORTEX_SMP_TIMER		0x2919c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define VORTEX_CODEC2_CTRL		0x291a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define VORTEX_MODEM_CTRL		0x291ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define VORTEX_IRQ_SOURCE 0x2a000	/* Interrupt source flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define VORTEX_IRQ_CTRL 0x2a004	/* Interrupt source mask. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) //#define VORTEX_IRQ_U0 0x2a008 /* ?? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define VORTEX_STAT		0x2a008	/* Some sort of status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define 	STAT_IRQ	0x00000001	/* This bitis set if the IRQ is valid. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define VORTEX_CTRL		0x2a00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define 	CTRL_MIDI_EN	0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define 	CTRL_MIDI_PORT	0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define 	CTRL_GAME_EN	0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define 	CTRL_GAME_PORT	0x00000e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define 	CTRL_IRQ_ENABLE	0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define		CTRL_SPDIF		0x00000000	/* unknown. Please find this value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define 	CTRL_SPORT		0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define 	CTRL_RST		0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define 	CTRL_UNKNOWN	0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* write: Timer period config / read: TIMER IRQ ack. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define VORTEX_IRQ_STAT 0x2919c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		     /* MIDI *//* GAME. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define VORTEX_MIDI_DATA 0x28800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define VORTEX_MIDI_CMD 0x28804	/* Write command / Read status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define VORTEX_GAME_LEGACY 0x28808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define VORTEX_CTRL2 0x2880c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define		CTRL2_GAME_ADCMODE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define VORTEX_GAME_AXIS 0x28810	/* Axis base register. 4 axis's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define		AXIS_SIZE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define		AXIS_RANGE 0x1fff