Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)     Aureal Vortex Soundcard driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)     IO addr collected from asp4core.vxd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)     function    address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)     0005D5A0    13004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)     00080674    14004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)     00080AFF    12818
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define CHIP_AU8820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define CARD_NAME "Aureal Vortex"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define CARD_NAME_SHORT "au8820"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) /* Number of ADB and WT channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define NR_ADB		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define NR_WT		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define NR_SRC		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define NR_A3D		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define NR_MIXIN	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define NR_MIXOUT 	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) /* ADBDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define VORTEX_ADBDMA_STAT 0x105c0	/* read only, subbuffer, DMA pos */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define		POS_MASK 0x00000fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define     POS_SHIFT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define 	ADB_SUBBUF_MASK 0x00003000	/* ADB only. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define     ADB_SUBBUF_SHIFT 0xc	/* ADB only. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define VORTEX_ADBDMA_CTRL 0x10580	/* write only, format, flags, DMA pos */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define		OFFSET_MASK 0x00000fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define     OFFSET_SHIFT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define		IE_MASK 0x00001000	/* interrupt enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define     IE_SHIFT 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define     DIR_MASK 0x00002000	/* Direction. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define     DIR_SHIFT 0xd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define		FMT_MASK 0x0003c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define		FMT_SHIFT 0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) // The masks and shift also work for the wtdma, if not specified otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define VORTEX_ADBDMA_BUFCFG0 0x10400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define VORTEX_ADBDMA_BUFCFG1 0x10404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define VORTEX_ADBDMA_BUFBASE 0x10200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define VORTEX_ADBDMA_START 0x106c0	/* Which subbuffer starts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define VORTEX_ADBDMA_STATUS 0x10600	/* stored at AdbDma->this_10 / 2 DWORD in size. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) /* ADB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define VORTEX_ADB_SR 0x10a00	/* Samplerates enable/disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define VORTEX_ADB_RTBASE 0x10800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define VORTEX_ADB_RTBASE_COUNT 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define VORTEX_ADB_CHNBASE 0x1099c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define VORTEX_ADB_CHNBASE_COUNT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define 	ROUTE_MASK	0x3fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define     ADB_MASK   0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define		ADB_SHIFT 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) //#define     ADB_MIX_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) /* ADB address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define		OFFSET_ADBDMA	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define		OFFSET_SRCOUT	0x10	/* on channel 0x11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define		OFFSET_SRCIN	0x10	/* on channel < 0x11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define		OFFSET_MIXOUT	0x20	/* source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define		OFFSET_MIXIN	0x30	/* sink */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define		OFFSET_CODECIN	0x48	/* ADB source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define		OFFSET_CODECOUT	0x58	/* ADB sink/target */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define		OFFSET_SPORTOUT	0x60	/* sink */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define		OFFSET_SPORTIN	0x50	/* source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define		OFFSET_EFXOUT	0x50	/* sink */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define		OFFSET_EFXIN	0x40	/* source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define		OFFSET_A3DOUT	0x00	/* This card has no HRTF :( */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define		OFFSET_A3DIN	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define		OFFSET_WTOUT	0x58	/*  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) /* ADB route translate helper */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define ADB_DMA(x) (x + OFFSET_ADBDMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define ADB_SRCOUT(x) (x + OFFSET_SRCOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define ADB_SRCIN(x) (x + OFFSET_SRCIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define ADB_MIXOUT(x) (x + OFFSET_MIXOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define ADB_MIXIN(x) (x + OFFSET_MIXIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define ADB_CODECIN(x) (x + OFFSET_CODECIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define ADB_CODECOUT(x) (x + OFFSET_CODECOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define ADB_SPORTOUT(x) (x + OFFSET_SPORTOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define ADB_SPORTIN(x) (x + OFFSET_SPORTIN)	/*  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define ADB_A3DOUT(x) (x + OFFSET_A3DOUT)	/* 8 A3D blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define ADB_A3DIN(x) (x + OFFSET_A3DIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define ADB_WTOUT(x,y) (y + OFFSET_WTOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) /* WTDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define VORTEX_WTDMA_CTRL 0x10500	/* format, DMA pos */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define VORTEX_WTDMA_STAT 0x10500	/* DMA subbuf, DMA pos */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define     WT_SUBBUF_MASK (0x3 << WT_SUBBUF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define     WT_SUBBUF_SHIFT 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define VORTEX_WTDMA_BUFBASE 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define VORTEX_WTDMA_BUFCFG0 0x10300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define VORTEX_WTDMA_BUFCFG1 0x10304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define VORTEX_WTDMA_START 0x10640	/* which subbuffer is first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define VORTEX_WT_BASE 0x9000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* MIXER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define VORTEX_MIXER_SR 0x9f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define VORTEX_MIXER_CLIP 0x9f80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define VORTEX_MIXER_CHNBASE 0x9e40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define VORTEX_MIXER_RTBASE 0x9e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define 	MIXER_RTBASE_SIZE 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define VORTEX_MIX_ENIN 0x9a00	/* Input enable bits. 4 bits wide. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define VORTEX_MIX_SMP 0x9c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* MIX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define VORTEX_MIX_INVOL_A 0x9000	/* in? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define VORTEX_MIX_INVOL_B 0x8000	/* out? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define VORTEX_MIX_VOL_A 0x9800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define VORTEX_MIX_VOL_B 0x8800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define 	VOL_MIN 0x80	/* Input volume when muted. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define		VOL_MAX 0x7f	/* FIXME: Not confirmed! Just guessed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) //#define MIX_OUTL    0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) //#define MIX_OUTR    0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) //#define MIX_INL     0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) //#define MIX_INR     0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MIX_DEFIGAIN 0x08	/* 0x8 => 6dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MIX_DEFOGAIN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* SRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define VORTEX_SRCBLOCK_SR	0xccc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define VORTEX_SRC_CHNBASE	0xcc40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define VORTEX_SRC_RTBASE	0xcc00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define VORTEX_SRC_SOURCE	0xccc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define VORTEX_SRC_SOURCESIZE 0xccc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define VORTEX_SRC_U0		0xce00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define VORTEX_SRC_DRIFT0	0xce80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define VORTEX_SRC_DRIFT1	0xcec0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define VORTEX_SRC_U1		0xcf00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define VORTEX_SRC_DRIFT2	0xcf40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define VORTEX_SRC_U2		0xcf80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define VORTEX_SRC_DATA		0xc800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define VORTEX_SRC_DATA0	0xc000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define VORTEX_SRC_CONVRATIO 0xce40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) //#define     SRC_RATIO(x) ((((x<<15)/48000) + 1)/2) /* Playback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) //#define     SRC_RATIO2(x) ((((48000<<15)/x) + 1)/2) /* Recording */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define VORTEX_FIFO_ADBCTRL 0xf800	/* Control bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define VORTEX_FIFO_WTCTRL 0xf840
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define		FIFO_RDONLY	0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define		FIFO_CTRL	0x00000002	/* Allow ctrl. ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define		FIFO_VALID	0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define 	FIFO_EMPTY	0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define		FIFO_U0		0x00001000	/* Unknown. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define		FIFO_U1		0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define		FIFO_SIZE_BITS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define		FIFO_SIZE	(1<<FIFO_SIZE_BITS)	// 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define 	FIFO_MASK	(FIFO_SIZE-1)	//0x1f    /* at shift left 0xc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define VORTEX_FIFO_ADBDATA 0xe000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define VORTEX_FIFO_WTDATA 0xe800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* CODEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define VORTEX_CODEC_CTRL 0x11984
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define VORTEX_CODEC_EN 0x11990
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define		EN_CODEC	0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define		EN_SPORT	0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define		EN_SPDIF	0x000c0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define VORTEX_CODEC_CHN 0x11880
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define VORTEX_CODEC_IO 0x11988
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define VORTEX_SPDIF_FLAGS		0x1005c	/* FIXME */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define VORTEX_SPDIF_CFG0		0x119D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define VORTEX_SPDIF_CFG1		0x119D4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define VORTEX_SPDIF_SMPRATE	0x11994
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* Sample timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define VORTEX_SMP_TIME 0x11998
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define VORTEX_IRQ_SOURCE 0x12800	/* Interrupt source flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define VORTEX_IRQ_CTRL 0x12804	/* Interrupt source mask. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define VORTEX_STAT		0x12808	/* ?? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define VORTEX_CTRL 0x1280c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define 	CTRL_MIDI_EN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define 	CTRL_MIDI_PORT 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define 	CTRL_GAME_EN 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define 	CTRL_GAME_PORT 0x00000e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define 	CTRL_IRQ_ENABLE 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* write: Timer period config / read: TIMER IRQ ack. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define VORTEX_IRQ_STAT 0x1199c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define VORTEX_DMA_BUFFER 0x10200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define VORTEX_ENGINE_CTRL 0x1060c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define 	ENGINE_INIT 0x0L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		     /* MIDI *//* GAME. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define VORTEX_MIDI_DATA 0x11000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define VORTEX_MIDI_CMD 0x11004	/* Write command / Read status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define VORTEX_GAME_LEGACY 0x11008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define VORTEX_CTRL2 0x1100c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define 	CTRL2_GAME_ADCMODE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define VORTEX_GAME_AXIS 0x11010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define 	AXIS_SIZE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define		AXIS_RANGE 0x1fff