Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)     Aureal Advantage Soundcard driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #define CHIP_AU8810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define CARD_NAME "Aureal Advantage"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define CARD_NAME_SHORT "au8810"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define NR_ADB		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define NR_WT		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define NR_SRC		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define NR_A3D		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define NR_MIXIN	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define NR_MIXOUT	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) /* ADBDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define VORTEX_ADBDMA_STAT 0x27e00	/* read only, subbuffer, DMA pos */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define		POS_MASK 0x00000fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define     POS_SHIFT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define 	ADB_SUBBUF_MASK 0x00003000	/* ADB only. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define     ADB_SUBBUF_SHIFT 0xc	/* ADB only. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define VORTEX_ADBDMA_CTRL 0x27180	/* write only; format, flags, DMA pos */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define		OFFSET_MASK 0x00000fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define     OFFSET_SHIFT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define		IE_MASK 0x00001000	/* interrupt enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define     IE_SHIFT 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define     DIR_MASK 0x00002000	/* Direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define     DIR_SHIFT 0xd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define		FMT_MASK 0x0003c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define		FMT_SHIFT 0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) // The ADB masks and shift also are valid for the wtdma, except if specified otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define VORTEX_ADBDMA_BUFCFG0 0x27100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define VORTEX_ADBDMA_BUFCFG1 0x27104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define VORTEX_ADBDMA_BUFBASE 0x27000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define VORTEX_ADBDMA_START 0x27c00	/* Which subbuffer starts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define VORTEX_ADBDMA_STATUS 0x27A90	/* stored at AdbDma->this_10 / 2 DWORD in size. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) /* WTDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define VORTEX_WTDMA_CTRL 0x27fd8	/* format, DMA pos */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define VORTEX_WTDMA_STAT 0x27fe8	/* DMA subbuf, DMA pos */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define     WT_SUBBUF_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define     WT_SUBBUF_SHIFT 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define VORTEX_WTDMA_BUFBASE 0x27fc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define VORTEX_WTDMA_BUFCFG0 0x27fd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define VORTEX_WTDMA_BUFCFG1 0x27fd4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define VORTEX_WTDMA_START 0x27fe4	/* which subbuffer is first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) /* ADB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define VORTEX_ADB_SR 0x28400	/* Samplerates enable/disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define VORTEX_ADB_RTBASE 0x28000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define VORTEX_ADB_RTBASE_COUNT 173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define VORTEX_ADB_CHNBASE 0x282b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define VORTEX_ADB_CHNBASE_COUNT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define 	ROUTE_MASK	0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define		SOURCE_MASK	0xff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define     ADB_MASK   0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define		ADB_SHIFT 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) /* ADB address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define		OFFSET_ADBDMA	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define		OFFSET_SRCIN	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define		OFFSET_SRCOUT	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define		OFFSET_MIXIN	0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define		OFFSET_MIXOUT	0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define		OFFSET_CODECIN	0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define		OFFSET_CODECOUT	0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define		OFFSET_SPORTIN	0x78	/* ch 0x13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define		OFFSET_SPORTOUT	0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define		OFFSET_SPDIFOUT	0x92	/* ch 0x14 check this! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define		OFFSET_EQIN	0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define		OFFSET_EQOUT	0x7e	/* 2 routes on ch 0x11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define		OFFSET_XTALKOUT	0x66	/* crosstalk canceller (source) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define		OFFSET_XTALKIN	0x96	/* crosstalk canceller (sink) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define		OFFSET_A3DIN	0x70	/* ADB sink. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define		OFFSET_A3DOUT	0xA6	/* ADB source. 2 routes per slice = 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define		OFFSET_EFXIN	0x80	/* ADB sink. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define		OFFSET_EFXOUT	0x68	/* ADB source. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) /* ADB route translate helper */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define ADB_DMA(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define ADB_SRCOUT(x) (x + OFFSET_SRCOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define ADB_SRCIN(x) (x + OFFSET_SRCIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define ADB_MIXOUT(x) (x + OFFSET_MIXOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define ADB_MIXIN(x) (x + OFFSET_MIXIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define ADB_CODECIN(x) (x + OFFSET_CODECIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define ADB_CODECOUT(x) (x + OFFSET_CODECOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define ADB_SPORTIN(x) (x + OFFSET_SPORTIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define ADB_SPORTOUT(x) (x + OFFSET_SPORTOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define ADB_SPDIFOUT(x)	(x + OFFSET_SPDIFOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define ADB_EQIN(x) (x + OFFSET_EQIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define ADB_EQOUT(x) (x + OFFSET_EQOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define ADB_A3DOUT(x) (x + OFFSET_A3DOUT)	/* 0x10 A3D blocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define ADB_A3DIN(x) (x + OFFSET_A3DIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define ADB_XTALKIN(x) (x + OFFSET_XTALKIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define ADB_XTALKOUT(x) (x + OFFSET_XTALKOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MIX_OUTL    0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MIX_OUTR    0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MIX_INL     0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MIX_INR     0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MIX_DEFIGAIN 0x08	/* 0x8 => 6dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MIX_DEFOGAIN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* MIXER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define VORTEX_MIXER_SR 0x21f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define VORTEX_MIXER_CLIP 0x21f80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define VORTEX_MIXER_CHNBASE 0x21e40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define VORTEX_MIXER_RTBASE 0x21e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define 	MIXER_RTBASE_SIZE 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define VORTEX_MIX_ENIN 0x21a00	/* Input enable bits. 4 bits wide. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define VORTEX_MIX_SMP 0x21c00	/* AU8820: 0x9c00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* MIX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define VORTEX_MIX_INVOL_A 0x21000	/* in? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define VORTEX_MIX_INVOL_B 0x20000	/* out? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define VORTEX_MIX_VOL_A 0x21800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define VORTEX_MIX_VOL_B 0x20800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define 	VOL_MIN 0x80	/* Input volume when muted. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define		VOL_MAX 0x7f	/* FIXME: Not confirmed! Just guessed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* SRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define VORTEX_SRC_CHNBASE		0x26c40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define VORTEX_SRC_RTBASE		0x26c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define VORTEX_SRCBLOCK_SR		0x26cc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define VORTEX_SRC_SOURCE		0x26cc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define VORTEX_SRC_SOURCESIZE	0x26cc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Params
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	0x26e00	: 1 U0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	0x26e40	: 2 CR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	0x26e80	: 3 U3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	0x26ec0	: 4 DRIFT1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	0x26f00 : 5 U1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	0x26f40	: 6 DRIFT2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	0x26f80	: 7 U2 : Target rate, direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define VORTEX_SRC_CONVRATIO	0x26e40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define VORTEX_SRC_DRIFT0		0x26e80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define VORTEX_SRC_DRIFT1		0x26ec0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define VORTEX_SRC_DRIFT2		0x26f40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define VORTEX_SRC_U0			0x26e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define		U0_SLOWLOCK		0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define VORTEX_SRC_U1			0x26f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define VORTEX_SRC_U2			0x26f80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define VORTEX_SRC_DATA			0x26800	/* 0xc800 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define VORTEX_SRC_DATA0		0x26000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define VORTEX_FIFO_ADBCTRL 0x16100	/* Control bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define VORTEX_FIFO_WTCTRL 0x16000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define		FIFO_RDONLY	0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define		FIFO_CTRL	0x00000002	/* Allow ctrl. ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define		FIFO_VALID	0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define 	FIFO_EMPTY	0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define		FIFO_U0		0x00001000	/* Unknown. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define		FIFO_U1		0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define		FIFO_SIZE_BITS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define		FIFO_SIZE	(1<<FIFO_SIZE_BITS)	// 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define 	FIFO_MASK	(FIFO_SIZE-1)	//0x1f    /* at shift left 0xc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) //#define       FIFO_MASK       0x1f    /* at shift left 0xb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) //#define               FIFO_SIZE       0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define 	FIFO_BITS	0x03880000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define VORTEX_FIFO_ADBDATA	0x14000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define VORTEX_FIFO_WTDATA	0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* CODEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define VORTEX_CODEC_CTRL	0x29184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define VORTEX_CODEC_EN		0x29190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define		EN_CODEC0	0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define 	EN_AC98		0x00000c00 /* Modem AC98 slots. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define		EN_CODEC1	0x00003000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define		EN_CODEC	(EN_CODEC0 | EN_CODEC1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define		EN_SPORT	0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define		EN_SPDIF	0x000c0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define VORTEX_CODEC_CHN 	0x29080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define VORTEX_CODEC_IO		0x29188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* SPDIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define VORTEX_SPDIF_FLAGS	0x2205c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define VORTEX_SPDIF_CFG0	0x291D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define VORTEX_SPDIF_CFG1	0x291D4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define VORTEX_SPDIF_SMPRATE	0x29194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* Sample timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define VORTEX_SMP_TIME		0x29198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define VORTEX_MODEM_CTRL	0x291ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define VORTEX_IRQ_SOURCE 0x2a000	/* Interrupt source flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define VORTEX_IRQ_CTRL 0x2a004	/* Interrupt source mask. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define VORTEX_STAT	0x2a008	/* Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define VORTEX_CTRL		0x2a00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define 	CTRL_MIDI_EN	0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define 	CTRL_MIDI_PORT	0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define 	CTRL_GAME_EN	0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define 	CTRL_GAME_PORT	0x00000e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) //#define       CTRL_IRQ_ENABLE 0x01004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define 	CTRL_IRQ_ENABLE	0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* write: Timer period config / read: TIMER IRQ ack. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define VORTEX_IRQ_STAT		0x2919c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define VORTEX_ENGINE_CTRL	0x27ae8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define 	ENGINE_INIT	0x1380000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* MIDI *//* GAME. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define VORTEX_MIDI_DATA	0x28800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define VORTEX_MIDI_CMD		0x28804	/* Write command / Read status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define VORTEX_CTRL2		0x2880c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define		CTRL2_GAME_ADCMODE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define VORTEX_GAME_LEGACY	0x28808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define VORTEX_GAME_AXIS	0x28810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define		AXIS_SIZE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define		AXIS_RANGE 0x1fff