^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /******************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) AudioScience HPI driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Copyright (C) 1997-2011 AudioScience Inc. <support@audioscience.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) Hardware Programming Interface (HPI) for AudioScience ASI6200 series adapters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) These PCI bus adapters are based on the TI C6711 DSP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Exported functions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) void HPI_6000(struct hpi_message *phm, struct hpi_response *phr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #defines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) HIDE_PCI_ASSERTS to show the PCI asserts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) PROFILE_DSP2 get profile data from DSP2 if present (instead of DSP 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) (C) Copyright AudioScience Inc. 1998-2003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *******************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SOURCEFILE_NAME "hpi6000.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "hpi_internal.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "hpimsginit.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "hpidebug.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "hpi6000.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "hpidspcd.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "hpicmn.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define HPI_HIF_BASE (0x00000200) /* start of C67xx internal RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define HPI_HIF_ADDR(member) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) (HPI_HIF_BASE + offsetof(struct hpi_hif_6000, member))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define HPI_HIF_ERROR_MASK 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* HPI6000 specific error codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define HPI6000_ERROR_BASE 900 /* not actually used anywhere */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* operational/messaging errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define HPI6000_ERROR_MSG_RESP_IDLE_TIMEOUT 901
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define HPI6000_ERROR_RESP_GET_LEN 902
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define HPI6000_ERROR_MSG_RESP_GET_RESP_ACK 903
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define HPI6000_ERROR_MSG_GET_ADR 904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define HPI6000_ERROR_RESP_GET_ADR 905
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define HPI6000_ERROR_MSG_RESP_BLOCKWRITE32 906
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define HPI6000_ERROR_MSG_RESP_BLOCKREAD32 907
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define HPI6000_ERROR_CONTROL_CACHE_PARAMS 909
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define HPI6000_ERROR_SEND_DATA_IDLE_TIMEOUT 911
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define HPI6000_ERROR_SEND_DATA_ACK 912
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define HPI6000_ERROR_SEND_DATA_ADR 913
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define HPI6000_ERROR_SEND_DATA_TIMEOUT 914
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define HPI6000_ERROR_SEND_DATA_CMD 915
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define HPI6000_ERROR_SEND_DATA_WRITE 916
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define HPI6000_ERROR_SEND_DATA_IDLECMD 917
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define HPI6000_ERROR_GET_DATA_IDLE_TIMEOUT 921
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define HPI6000_ERROR_GET_DATA_ACK 922
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define HPI6000_ERROR_GET_DATA_CMD 923
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define HPI6000_ERROR_GET_DATA_READ 924
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define HPI6000_ERROR_GET_DATA_IDLECMD 925
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define HPI6000_ERROR_CONTROL_CACHE_ADDRLEN 951
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define HPI6000_ERROR_CONTROL_CACHE_READ 952
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define HPI6000_ERROR_CONTROL_CACHE_FLUSH 953
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define HPI6000_ERROR_MSG_RESP_GETRESPCMD 961
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define HPI6000_ERROR_MSG_RESP_IDLECMD 962
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* Initialisation/bootload errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define HPI6000_ERROR_UNHANDLED_SUBSYS_ID 930
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* can't access PCI2040 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define HPI6000_ERROR_INIT_PCI2040 931
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* can't access DSP HPI i/f */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define HPI6000_ERROR_INIT_DSPHPI 932
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* can't access internal DSP memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define HPI6000_ERROR_INIT_DSPINTMEM 933
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* can't access SDRAM - test#1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define HPI6000_ERROR_INIT_SDRAM1 934
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* can't access SDRAM - test#2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define HPI6000_ERROR_INIT_SDRAM2 935
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define HPI6000_ERROR_INIT_VERIFY 938
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define HPI6000_ERROR_INIT_NOACK 939
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define HPI6000_ERROR_INIT_PLDTEST1 941
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define HPI6000_ERROR_INIT_PLDTEST2 942
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* local defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define HIDE_PCI_ASSERTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PROFILE_DSP2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* for PCI2040 i/f chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* HPI CSR registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* word offsets from CSR base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* use when io addresses defined as u32 * */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define INTERRUPT_EVENT_SET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define INTERRUPT_EVENT_CLEAR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define INTERRUPT_MASK_SET 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define INTERRUPT_MASK_CLEAR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define HPI_ERROR_REPORT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define HPI_RESET 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define HPI_DATA_WIDTH 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MAX_DSPS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* HPI registers, spaced 8K bytes = 2K words apart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define DSP_SPACING 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CONTROL 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define ADDRESS 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define DATA_AUTOINC 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define DATA 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define TIMEOUT 500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct dsp_obj {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) __iomem u32 *prHPI_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) __iomem u32 *prHPI_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) __iomem u32 *prHPI_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) __iomem u32 *prHPI_data_auto_inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) char c_dsp_rev; /*A, B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 control_cache_address_on_dsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 control_cache_length_on_dsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct hpi_adapter_obj *pa_parent_adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct hpi_hw_obj {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) __iomem u32 *dw2040_HPICSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) __iomem u32 *dw2040_HPIDSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u16 num_dsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct dsp_obj ado[MAX_DSPS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 message_buffer_address_on_dsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 response_buffer_address_on_dsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 pCI2040HPI_error_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct hpi_control_cache_single control_cache[HPI_NMIXER_CONTROLS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct hpi_control_cache *p_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static u16 hpi6000_dsp_block_write32(struct hpi_adapter_obj *pao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u16 dsp_index, u32 hpi_address, u32 *source, u32 count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static u16 hpi6000_dsp_block_read32(struct hpi_adapter_obj *pao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u16 dsp_index, u32 hpi_address, u32 *dest, u32 count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static short hpi6000_adapter_boot_load_dsp(struct hpi_adapter_obj *pao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u32 *pos_error_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static short hpi6000_check_PCI2040_error_flag(struct hpi_adapter_obj *pao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u16 read_or_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define H6READ 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define H6WRITE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static short hpi6000_update_control_cache(struct hpi_adapter_obj *pao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct hpi_message *phm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static short hpi6000_message_response_sequence(struct hpi_adapter_obj *pao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u16 dsp_index, struct hpi_message *phm, struct hpi_response *phr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct hpi_response *phr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static short hpi6000_wait_dsp_ack(struct hpi_adapter_obj *pao, u16 dsp_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u32 ack_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static short hpi6000_send_host_command(struct hpi_adapter_obj *pao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u16 dsp_index, u32 host_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static void hpi6000_send_dsp_interrupt(struct dsp_obj *pdo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static short hpi6000_send_data(struct hpi_adapter_obj *pao, u16 dsp_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct hpi_message *phm, struct hpi_response *phr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static short hpi6000_get_data(struct hpi_adapter_obj *pao, u16 dsp_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct hpi_message *phm, struct hpi_response *phr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static void hpi_write_word(struct dsp_obj *pdo, u32 address, u32 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static u32 hpi_read_word(struct dsp_obj *pdo, u32 address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static void hpi_write_block(struct dsp_obj *pdo, u32 address, u32 *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u32 length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static void hpi_read_block(struct dsp_obj *pdo, u32 address, u32 *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u32 length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static void subsys_create_adapter(struct hpi_message *phm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct hpi_response *phr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static void adapter_delete(struct hpi_adapter_obj *pao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct hpi_message *phm, struct hpi_response *phr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static void adapter_get_asserts(struct hpi_adapter_obj *pao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct hpi_message *phm, struct hpi_response *phr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static short create_adapter_obj(struct hpi_adapter_obj *pao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u32 *pos_error_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static void delete_adapter_obj(struct hpi_adapter_obj *pao);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* local globals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static u16 gw_pci_read_asserts; /* used to count PCI2040 errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static u16 gw_pci_write_asserts; /* used to count PCI2040 errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static void subsys_message(struct hpi_message *phm, struct hpi_response *phr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) switch (phm->function) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) case HPI_SUBSYS_CREATE_ADAPTER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) subsys_create_adapter(phm, phr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) phr->error = HPI_ERROR_INVALID_FUNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static void control_message(struct hpi_adapter_obj *pao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct hpi_message *phm, struct hpi_response *phr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct hpi_hw_obj *phw = pao->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) switch (phm->function) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) case HPI_CONTROL_GET_STATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (pao->has_control_cache) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u16 err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) err = hpi6000_update_control_cache(pao, phm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (err >= HPI_ERROR_BACKEND_BASE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) phr->error =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) HPI_ERROR_CONTROL_CACHING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) phr->specific_error = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) phr->error = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (hpi_check_control_cache(phw->p_cache, phm, phr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) hw_message(pao, phm, phr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) case HPI_CONTROL_SET_STATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) hw_message(pao, phm, phr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) hpi_cmn_control_cache_sync_to_msg(phw->p_cache, phm, phr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) case HPI_CONTROL_GET_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) hw_message(pao, phm, phr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static void adapter_message(struct hpi_adapter_obj *pao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct hpi_message *phm, struct hpi_response *phr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) switch (phm->function) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) case HPI_ADAPTER_GET_ASSERT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) adapter_get_asserts(pao, phm, phr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) case HPI_ADAPTER_DELETE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) adapter_delete(pao, phm, phr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) hw_message(pao, phm, phr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static void outstream_message(struct hpi_adapter_obj *pao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct hpi_message *phm, struct hpi_response *phr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) switch (phm->function) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) case HPI_OSTREAM_HOSTBUFFER_ALLOC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) case HPI_OSTREAM_HOSTBUFFER_FREE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* Don't let these messages go to the HW function because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * they're called without locking the spinlock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * For the HPI6000 adapters the HW would return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * HPI_ERROR_INVALID_FUNC anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) phr->error = HPI_ERROR_INVALID_FUNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) hw_message(pao, phm, phr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static void instream_message(struct hpi_adapter_obj *pao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct hpi_message *phm, struct hpi_response *phr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) switch (phm->function) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) case HPI_ISTREAM_HOSTBUFFER_ALLOC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) case HPI_ISTREAM_HOSTBUFFER_FREE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* Don't let these messages go to the HW function because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * they're called without locking the spinlock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * For the HPI6000 adapters the HW would return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * HPI_ERROR_INVALID_FUNC anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) phr->error = HPI_ERROR_INVALID_FUNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) hw_message(pao, phm, phr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /** HPI_6000()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * Entry point from HPIMAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * All calls to the HPI start here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) void HPI_6000(struct hpi_message *phm, struct hpi_response *phr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct hpi_adapter_obj *pao = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (phm->object != HPI_OBJ_SUBSYSTEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) pao = hpi_find_adapter(phm->adapter_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (!pao) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) hpi_init_response(phr, phm->object, phm->function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) HPI_ERROR_BAD_ADAPTER_NUMBER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) HPI_DEBUG_LOG(DEBUG, "invalid adapter index: %d \n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) phm->adapter_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* Don't even try to communicate with crashed DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (pao->dsp_crashed >= 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) hpi_init_response(phr, phm->object, phm->function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) HPI_ERROR_DSP_HARDWARE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) HPI_DEBUG_LOG(DEBUG, "adapter %d dsp crashed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) phm->adapter_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* Init default response including the size field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (phm->function != HPI_SUBSYS_CREATE_ADAPTER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) hpi_init_response(phr, phm->object, phm->function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) HPI_ERROR_PROCESSING_MESSAGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) switch (phm->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) case HPI_TYPE_REQUEST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) switch (phm->object) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) case HPI_OBJ_SUBSYSTEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) subsys_message(phm, phr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) case HPI_OBJ_ADAPTER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) phr->size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) sizeof(struct hpi_response_header) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) sizeof(struct hpi_adapter_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) adapter_message(pao, phm, phr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) case HPI_OBJ_CONTROL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) control_message(pao, phm, phr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) case HPI_OBJ_OSTREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) outstream_message(pao, phm, phr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) case HPI_OBJ_ISTREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) instream_message(pao, phm, phr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) hw_message(pao, phm, phr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) phr->error = HPI_ERROR_INVALID_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* SUBSYSTEM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* create an adapter object and initialise it based on resource information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * passed in in the message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * NOTE - you cannot use this function AND the FindAdapters function at the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * same time, the application must use only one of them to get the adapters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static void subsys_create_adapter(struct hpi_message *phm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct hpi_response *phr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* create temp adapter obj, because we don't know what index yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct hpi_adapter_obj ao;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct hpi_adapter_obj *pao;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) u32 os_error_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) u16 err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) u32 dsp_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) HPI_DEBUG_LOG(VERBOSE, "subsys_create_adapter\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) memset(&ao, 0, sizeof(ao));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) ao.priv = kzalloc(sizeof(struct hpi_hw_obj), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (!ao.priv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) HPI_DEBUG_LOG(ERROR, "can't get mem for adapter object\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) phr->error = HPI_ERROR_MEMORY_ALLOC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* create the adapter object based on the resource information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) ao.pci = *phm->u.s.resource.r.pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) err = create_adapter_obj(&ao, &os_error_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) delete_adapter_obj(&ao);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (err >= HPI_ERROR_BACKEND_BASE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) phr->error = HPI_ERROR_DSP_BOOTLOAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) phr->specific_error = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) phr->error = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) phr->u.s.data = os_error_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* need to update paParentAdapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) pao = hpi_find_adapter(ao.index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (!pao) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* We just added this adapter, why can't we find it!? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) HPI_DEBUG_LOG(ERROR, "lost adapter after boot\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) phr->error = HPI_ERROR_BAD_ADAPTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) for (dsp_index = 0; dsp_index < MAX_DSPS; dsp_index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct hpi_hw_obj *phw = pao->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) phw->ado[dsp_index].pa_parent_adapter = pao;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) phr->u.s.adapter_type = ao.type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) phr->u.s.adapter_index = ao.index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) phr->error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static void adapter_delete(struct hpi_adapter_obj *pao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct hpi_message *phm, struct hpi_response *phr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) delete_adapter_obj(pao);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) hpi_delete_adapter(pao);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) phr->error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* this routine is called from SubSysFindAdapter and SubSysCreateAdapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static short create_adapter_obj(struct hpi_adapter_obj *pao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) u32 *pos_error_code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) short boot_error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) u32 dsp_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) u32 control_cache_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) u32 control_cache_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct hpi_hw_obj *phw = pao->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /* The PCI2040 has the following address map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* BAR0 - 4K = HPI control and status registers on PCI2040 (HPI CSR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* BAR1 - 32K = HPI registers on DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) phw->dw2040_HPICSR = pao->pci.ap_mem_base[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) phw->dw2040_HPIDSP = pao->pci.ap_mem_base[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) HPI_DEBUG_LOG(VERBOSE, "csr %p, dsp %p\n", phw->dw2040_HPICSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) phw->dw2040_HPIDSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* set addresses for the possible DSP HPI interfaces */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) for (dsp_index = 0; dsp_index < MAX_DSPS; dsp_index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) phw->ado[dsp_index].prHPI_control =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) phw->dw2040_HPIDSP + (CONTROL +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) DSP_SPACING * dsp_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) phw->ado[dsp_index].prHPI_address =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) phw->dw2040_HPIDSP + (ADDRESS +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) DSP_SPACING * dsp_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) phw->ado[dsp_index].prHPI_data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) phw->dw2040_HPIDSP + (DATA + DSP_SPACING * dsp_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) phw->ado[dsp_index].prHPI_data_auto_inc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) phw->dw2040_HPIDSP + (DATA_AUTOINC +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) DSP_SPACING * dsp_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) HPI_DEBUG_LOG(VERBOSE, "ctl %p, adr %p, dat %p, dat++ %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) phw->ado[dsp_index].prHPI_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) phw->ado[dsp_index].prHPI_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) phw->ado[dsp_index].prHPI_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) phw->ado[dsp_index].prHPI_data_auto_inc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) phw->ado[dsp_index].pa_parent_adapter = pao;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) phw->pCI2040HPI_error_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) pao->has_control_cache = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* Set the default number of DSPs on this card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* This is (conditionally) adjusted after bootloading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /* of the first DSP in the bootload section. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) phw->num_dsp = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) boot_error = hpi6000_adapter_boot_load_dsp(pao, pos_error_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (boot_error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return boot_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) HPI_DEBUG_LOG(INFO, "bootload DSP OK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) phw->message_buffer_address_on_dsp = 0L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) phw->response_buffer_address_on_dsp = 0L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* get info about the adapter by asking the adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /* send a HPI_ADAPTER_GET_INFO message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct hpi_message hm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct hpi_response hr0; /* response from DSP 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct hpi_response hr1; /* response from DSP 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) u16 error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) HPI_DEBUG_LOG(VERBOSE, "send ADAPTER_GET_INFO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) memset(&hm, 0, sizeof(hm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) hm.type = HPI_TYPE_REQUEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) hm.size = sizeof(struct hpi_message);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) hm.object = HPI_OBJ_ADAPTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) hm.function = HPI_ADAPTER_GET_INFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) hm.adapter_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) memset(&hr0, 0, sizeof(hr0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) memset(&hr1, 0, sizeof(hr1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) hr0.size = sizeof(hr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) hr1.size = sizeof(hr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) error = hpi6000_message_response_sequence(pao, 0, &hm, &hr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (hr0.error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) HPI_DEBUG_LOG(DEBUG, "message error %d\n", hr0.error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return hr0.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (phw->num_dsp == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) error = hpi6000_message_response_sequence(pao, 1, &hm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) &hr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) pao->type = hr0.u.ax.info.adapter_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) pao->index = hr0.u.ax.info.adapter_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) memset(&phw->control_cache[0], 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) sizeof(struct hpi_control_cache_single) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) HPI_NMIXER_CONTROLS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /* Read the control cache length to figure out if it is turned on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) control_cache_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) hpi_read_word(&phw->ado[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) HPI_HIF_ADDR(control_cache_size_in_bytes));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (control_cache_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) control_cache_count =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) hpi_read_word(&phw->ado[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) HPI_HIF_ADDR(control_cache_count));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) phw->p_cache =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) hpi_alloc_control_cache(control_cache_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) control_cache_size, (unsigned char *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) &phw->control_cache[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (phw->p_cache)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) pao->has_control_cache = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) HPI_DEBUG_LOG(DEBUG, "get adapter info ASI%04X index %d\n", pao->type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) pao->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (phw->p_cache)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) phw->p_cache->adap_idx = pao->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return hpi_add_adapter(pao);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static void delete_adapter_obj(struct hpi_adapter_obj *pao)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) struct hpi_hw_obj *phw = pao->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (pao->has_control_cache)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) hpi_free_control_cache(phw->p_cache);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /* reset DSPs on adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) iowrite32(0x0003000F, phw->dw2040_HPICSR + HPI_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) kfree(phw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* ADAPTER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static void adapter_get_asserts(struct hpi_adapter_obj *pao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct hpi_message *phm, struct hpi_response *phr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #ifndef HIDE_PCI_ASSERTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /* if we have PCI2040 asserts then collect them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if ((gw_pci_read_asserts > 0) || (gw_pci_write_asserts > 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) phr->u.ax.assert.p1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) gw_pci_read_asserts * 100 + gw_pci_write_asserts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) phr->u.ax.assert.p2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) phr->u.ax.assert.count = 1; /* assert count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) phr->u.ax.assert.dsp_index = -1; /* "dsp index" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) strcpy(phr->u.ax.assert.sz_message, "PCI2040 error");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) phr->u.ax.assert.dsp_msg_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) gw_pci_read_asserts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) gw_pci_write_asserts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) phr->error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) hw_message(pao, phm, phr); /*get DSP asserts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* LOW-LEVEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static short hpi6000_adapter_boot_load_dsp(struct hpi_adapter_obj *pao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) u32 *pos_error_code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) struct hpi_hw_obj *phw = pao->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) short error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) u32 timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) u32 read = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) u32 i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) u32 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) u32 j = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) u32 test_addr = 0x80000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) u32 test_data = 0x00000001;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) u32 dw2040_reset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) u32 dsp_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) u32 endian = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) u32 adapter_info = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) u32 delay = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct dsp_code dsp_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) u16 boot_load_family = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /* NOTE don't use wAdapterType in this routine. It is not setup yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) switch (pao->pci.pci_dev->subsystem_device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) case 0x5100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) case 0x5110: /* ASI5100 revB or higher with C6711D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) case 0x5200: /* ASI5200 PCIe version of ASI5100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) case 0x6100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) case 0x6200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) boot_load_family = HPI_ADAPTER_FAMILY_ASI(0x6200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return HPI6000_ERROR_UNHANDLED_SUBSYS_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /* reset all DSPs, indicate two DSPs are present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) * set RST3-=1 to disconnect HAD8 to set DSP in little endian mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) endian = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) dw2040_reset = 0x0003000F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /* read back register to make sure PCI2040 chip is functioning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * note that bits 4..15 are read-only and so should always return zero,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * even though we wrote 1 to them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) hpios_delay_micro_seconds(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) delay = ioread32(phw->dw2040_HPICSR + HPI_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (delay != dw2040_reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) HPI_DEBUG_LOG(ERROR, "INIT_PCI2040 %x %x\n", dw2040_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return HPI6000_ERROR_INIT_PCI2040;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /* Indicate that DSP#0,1 is a C6X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) iowrite32(0x00000003, phw->dw2040_HPICSR + HPI_DATA_WIDTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) /* set Bit30 and 29 - which will prevent Target aborts from being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) * issued upon HPI or GP error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) iowrite32(0x60000000, phw->dw2040_HPICSR + INTERRUPT_MASK_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /* isolate DSP HAD8 line from PCI2040 so that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) * Little endian can be set by pullup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) dw2040_reset = dw2040_reset & (~(endian << 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) phw->ado[0].c_dsp_rev = 'B'; /* revB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) phw->ado[1].c_dsp_rev = 'B'; /* revB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /*Take both DSPs out of reset, setting HAD8 to the correct Endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) dw2040_reset = dw2040_reset & (~0x00000001); /* start DSP 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) dw2040_reset = dw2040_reset & (~0x00000002); /* start DSP 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /* set HAD8 back to PCI2040, now that DSP set to little endian mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) dw2040_reset = dw2040_reset & (~0x00000008);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) iowrite32(dw2040_reset, phw->dw2040_HPICSR + HPI_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /*delay to allow DSP to get going */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) hpios_delay_micro_seconds(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /* loop through all DSPs, downloading DSP code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) for (dsp_index = 0; dsp_index < phw->num_dsp; dsp_index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) struct dsp_obj *pdo = &phw->ado[dsp_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /* configure DSP so that we download code into the SRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /* set control reg for little endian, HWOB=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) iowrite32(0x00010001, pdo->prHPI_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) /* test access to the HPI address register (HPIA) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) test_data = 0x00000001;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) for (j = 0; j < 32; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) iowrite32(test_data, pdo->prHPI_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) data = ioread32(pdo->prHPI_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (data != test_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) HPI_DEBUG_LOG(ERROR, "INIT_DSPHPI %x %x %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) test_data, data, dsp_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return HPI6000_ERROR_INIT_DSPHPI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) test_data = test_data << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /* if C6713 the setup PLL to generate 225MHz from 25MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) * Since the PLLDIV1 read is sometimes wrong, even on a C6713,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) * we're going to do this unconditionally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /* PLLDIV1 should have a value of 8000 after reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (HpiReadWord(pdo,0x01B7C118) == 0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /* C6713 datasheet says we cannot program PLL from HPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) * and indeed if we try to set the PLL multiply from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) * HPI, the PLL does not seem to lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) * so we enable the PLL and use the default of x 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /* bypass PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) hpi_write_word(pdo, 0x01B7C100, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) hpios_delay_micro_seconds(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* ** use default of PLL x7 ** */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /* EMIF = 225/3=75MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) hpi_write_word(pdo, 0x01B7C120, 0x8002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) hpios_delay_micro_seconds(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /* peri = 225/2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) hpi_write_word(pdo, 0x01B7C11C, 0x8001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) hpios_delay_micro_seconds(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) /* cpu = 225/1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) hpi_write_word(pdo, 0x01B7C118, 0x8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) /* ~2ms delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) hpios_delay_micro_seconds(2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /* PLL not bypassed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) hpi_write_word(pdo, 0x01B7C100, 0x0001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) /* ~2ms delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) hpios_delay_micro_seconds(2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) /* test r/w to internal DSP memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) * C6711 has L2 cache mapped to 0x0 when reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) * revB - because of bug 3.0.1 last HPI read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) * (before HPI address issued) must be non-autoinc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /* test each bit in the 32bit word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) for (i = 0; i < 100; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) test_addr = 0x00000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) test_data = 0x00000001;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) for (j = 0; j < 32; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) hpi_write_word(pdo, test_addr + i, test_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) data = hpi_read_word(pdo, test_addr + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (data != test_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) HPI_DEBUG_LOG(ERROR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) "DSP mem %x %x %x %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) test_addr + i, test_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) data, dsp_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return HPI6000_ERROR_INIT_DSPINTMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) test_data = test_data << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) /* memory map of ASI6200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) 00000000-0000FFFF 16Kx32 internal program
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) 01800000-019FFFFF Internal peripheral
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) 80000000-807FFFFF CE0 2Mx32 SDRAM running @ 100MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) 90000000-9000FFFF CE1 Async peripherals:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) EMIF config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) ------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) Global EMIF control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) 0 -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) 1 -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) 2 -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) 3 CLK2EN = 1 CLKOUT2 enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) 4 CLK1EN = 0 CLKOUT1 disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) 5 EKEN = 1 <--!! C6713 specific, enables ECLKOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) 6 -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) 7 NOHOLD = 1 external HOLD disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) 8 HOLDA = 0 HOLDA output is low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) 9 HOLD = 0 HOLD input is low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) 10 ARDY = 1 ARDY input is high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) 11 BUSREQ = 0 BUSREQ output is low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) 12,13 Reserved = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) hpi_write_word(pdo, 0x01800000, 0x34A8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) /* EMIF CE0 setup - 2Mx32 Sync DRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) 31..28 Wr setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) 27..22 Wr strobe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) 21..20 Wr hold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) 19..16 Rd setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) 15..14 -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) 13..8 Rd strobe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) 7..4 MTYPE 0011 Sync DRAM 32bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) 3 Wr hold MSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) 2..0 Rd hold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) hpi_write_word(pdo, 0x01800008, 0x00000030);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) /* EMIF SDRAM Extension
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) 31-21 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) 20 WR2RD = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) 19-18 WR2DEAC = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) 17 WR2WR = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) 16-15 R2WDQM = 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) 14-12 RD2WR = 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) 11-10 RD2DEAC = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) 9 RD2RD = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) 8-7 THZP = 10b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) 6-5 TWR = 2-1 = 01b (tWR = 10ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) 4 TRRD = 0b = 2 ECLK (tRRD = 14ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) 3-1 TRAS = 5-1 = 100b (Tras=42ns = 5 ECLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) 1 CAS latency = 3 ECLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) (for Micron 2M32-7 operating at 100Mhz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) /* need to use this else DSP code crashes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) hpi_write_word(pdo, 0x01800020, 0x001BDF29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) /* EMIF SDRAM control - set up for a 2Mx32 SDRAM (512x32x4 bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) 31 - -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) 30 SDBSZ 1 4 bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) 29..28 SDRSZ 00 11 row address pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) 27..26 SDCSZ 01 8 column address pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) 25 RFEN 1 refersh enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) 24 INIT 1 init SDRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) 23..20 TRCD 0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) 19..16 TRP 0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) 15..12 TRC 0110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) 11..0 - -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) /* need to use this else DSP code crashes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) hpi_write_word(pdo, 0x01800018, 0x47117000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) /* EMIF SDRAM Refresh Timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) hpi_write_word(pdo, 0x0180001C, 0x00000410);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /*MIF CE1 setup - Async peripherals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) @100MHz bus speed, each cycle is 10ns,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) 31..28 Wr setup = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) 27..22 Wr strobe = 3 30ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) 21..20 Wr hold = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) 19..16 Rd setup =1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) 15..14 Ta = 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) 13..8 Rd strobe = 3 30ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) 7..4 MTYPE 0010 Async 32bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) 3 Wr hold MSB =0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) 2..0 Rd hold = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) u32 cE1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) (1L << 28) | (3L << 22) | (1L << 20) | (1L <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) 16) | (2L << 14) | (3L << 8) | (2L << 4) | 1L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) hpi_write_word(pdo, 0x01800004, cE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) /* delay a little to allow SDRAM and DSP to "get going" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) hpios_delay_micro_seconds(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) /* test access to SDRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) test_addr = 0x80000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) test_data = 0x00000001;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) /* test each bit in the 32bit word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) for (j = 0; j < 32; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) hpi_write_word(pdo, test_addr, test_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) data = hpi_read_word(pdo, test_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) if (data != test_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) HPI_DEBUG_LOG(ERROR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) "DSP dram %x %x %x %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) test_addr, test_data, data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) dsp_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) return HPI6000_ERROR_INIT_SDRAM1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) test_data = test_data << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) /* test every Nth address in the DRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #define DRAM_SIZE_WORDS 0x200000 /*2_mx32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) #define DRAM_INC 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) test_addr = 0x80000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) test_data = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) for (i = 0; i < DRAM_SIZE_WORDS; i = i + DRAM_INC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) hpi_write_word(pdo, test_addr + i, test_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) test_data++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) test_addr = 0x80000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) test_data = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) for (i = 0; i < DRAM_SIZE_WORDS; i = i + DRAM_INC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) data = hpi_read_word(pdo, test_addr + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) if (data != test_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) HPI_DEBUG_LOG(ERROR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) "DSP dram %x %x %x %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) test_addr + i, test_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) data, dsp_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) return HPI6000_ERROR_INIT_SDRAM2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) test_data++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) /* write the DSP code down into the DSPs memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) error = hpi_dsp_code_open(boot_load_family, pao->pci.pci_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) &dsp_code, pos_error_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) u32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) u32 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) u32 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) u32 *pcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) error = hpi_dsp_code_read_word(&dsp_code, &length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (length == 0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) break; /* end of code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) error = hpi_dsp_code_read_word(&dsp_code, &address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) error = hpi_dsp_code_read_word(&dsp_code, &type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) error = hpi_dsp_code_read_block(length, &dsp_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) &pcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) error = hpi6000_dsp_block_write32(pao, (u16)dsp_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) address, pcode, length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) hpi_dsp_code_close(&dsp_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) /* verify that code was written correctly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /* this time through, assume no errors in DSP code file/array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) hpi_dsp_code_rewind(&dsp_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) u32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) u32 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) u32 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) u32 *pcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) hpi_dsp_code_read_word(&dsp_code, &length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) if (length == 0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) break; /* end of code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) hpi_dsp_code_read_word(&dsp_code, &address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) hpi_dsp_code_read_word(&dsp_code, &type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) hpi_dsp_code_read_block(length, &dsp_code, &pcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) for (i = 0; i < length; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) data = hpi_read_word(pdo, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (data != *pcode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) error = HPI6000_ERROR_INIT_VERIFY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) HPI_DEBUG_LOG(ERROR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) "DSP verify %x %x %x %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) address, *pcode, data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) dsp_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) pcode++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) address += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) hpi_dsp_code_close(&dsp_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) /* zero out the hostmailbox */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) u32 address = HPI_HIF_ADDR(host_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) hpi_write_word(pdo, address, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) address += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) /* write the DSP number into the hostmailbox */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) /* structure before starting the DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) hpi_write_word(pdo, HPI_HIF_ADDR(dsp_number), dsp_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) /* write the DSP adapter Info into the */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) /* hostmailbox before starting the DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) if (dsp_index > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) hpi_write_word(pdo, HPI_HIF_ADDR(adapter_info),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) adapter_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) /* step 3. Start code by sending interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) iowrite32(0x00030003, pdo->prHPI_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) hpios_delay_micro_seconds(10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) /* wait for a non-zero value in hostcmd -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) * indicating initialization is complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) * Init could take a while if DSP checks SDRAM memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) * Was 200000. Increased to 2000000 for ASI8801 so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) * don't get 938 errors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) timeout = 2000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) while (timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) read = hpi_read_word(pdo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) HPI_HIF_ADDR(host_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) } while (--timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) && hpi6000_check_PCI2040_error_flag(pao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) H6READ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) if (read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) /* The following is a workaround for bug #94:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) * Bluescreen on install and subsequent boots on a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) * DELL PowerEdge 600SC PC with 1.8GHz P4 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) * ServerWorks chipset. Without this delay the system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) * locks up with a bluescreen (NOT GPF or pagefault).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) hpios_delay_micro_seconds(10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) if (timeout == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) return HPI6000_ERROR_INIT_NOACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) /* read the DSP adapter Info from the */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) /* hostmailbox structure after starting the DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) if (dsp_index == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) /*u32 dwTestData=0; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) u32 mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) adapter_info =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) hpi_read_word(pdo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) HPI_HIF_ADDR(adapter_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) if (HPI_ADAPTER_FAMILY_ASI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) (HPI_HIF_ADAPTER_INFO_EXTRACT_ADAPTER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) (adapter_info)) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) HPI_ADAPTER_FAMILY_ASI(0x6200))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) /* all 6200 cards have this many DSPs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) phw->num_dsp = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) /* test that the PLD is programmed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) /* and we can read/write 24bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) #define PLD_BASE_ADDRESS 0x90000000L /*for ASI6100/6200/8800 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) switch (boot_load_family) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) case HPI_ADAPTER_FAMILY_ASI(0x6200):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) /* ASI6100/6200 has 24bit path to FPGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) mask = 0xFFFFFF00L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) /* ASI5100 uses AX6 code, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) /* but has no PLD r/w register to test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) if (HPI_ADAPTER_FAMILY_ASI(pao->pci.pci_dev->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) subsystem_device) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) HPI_ADAPTER_FAMILY_ASI(0x5100))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) mask = 0x00000000L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) /* ASI5200 uses AX6 code, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) /* but has no PLD r/w register to test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) if (HPI_ADAPTER_FAMILY_ASI(pao->pci.pci_dev->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) subsystem_device) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) HPI_ADAPTER_FAMILY_ASI(0x5200))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) mask = 0x00000000L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) case HPI_ADAPTER_FAMILY_ASI(0x8800):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) /* ASI8800 has 16bit path to FPGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) mask = 0xFFFF0000L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) test_data = 0xAAAAAA00L & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) /* write to 24 bit Debug register (D31-D8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) hpi_write_word(pdo, PLD_BASE_ADDRESS + 4L, test_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) read = hpi_read_word(pdo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) PLD_BASE_ADDRESS + 4L) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) if (read != test_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) HPI_DEBUG_LOG(ERROR, "PLD %x %x\n", test_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) return HPI6000_ERROR_INIT_PLDTEST1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) test_data = 0x55555500L & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) hpi_write_word(pdo, PLD_BASE_ADDRESS + 4L, test_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) read = hpi_read_word(pdo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) PLD_BASE_ADDRESS + 4L) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) if (read != test_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) HPI_DEBUG_LOG(ERROR, "PLD %x %x\n", test_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) return HPI6000_ERROR_INIT_PLDTEST2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) } /* for numDSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) #define PCI_TIMEOUT 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) static int hpi_set_address(struct dsp_obj *pdo, u32 address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) u32 timeout = PCI_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) iowrite32(address, pdo->prHPI_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) } while (hpi6000_check_PCI2040_error_flag(pdo->pa_parent_adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) H6WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) && --timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) if (timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) /* write one word to the HPI port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) static void hpi_write_word(struct dsp_obj *pdo, u32 address, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) if (hpi_set_address(pdo, address))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) iowrite32(data, pdo->prHPI_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) /* read one word from the HPI port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) static u32 hpi_read_word(struct dsp_obj *pdo, u32 address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) u32 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) if (hpi_set_address(pdo, address))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) return 0; /*? No way to return error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) /* take care of errata in revB DSP (2.0.1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) data = ioread32(pdo->prHPI_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) /* write a block of 32bit words to the DSP HPI port using auto-inc mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) static void hpi_write_block(struct dsp_obj *pdo, u32 address, u32 *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) u32 length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) u16 length16 = length - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) if (length == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) if (hpi_set_address(pdo, address))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) iowrite32_rep(pdo->prHPI_data_auto_inc, pdata, length16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) /* take care of errata in revB DSP (2.0.1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) /* must end with non auto-inc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) iowrite32(*(pdata + length - 1), pdo->prHPI_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) /** read a block of 32bit words from the DSP HPI port using auto-inc mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) static void hpi_read_block(struct dsp_obj *pdo, u32 address, u32 *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) u32 length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) u16 length16 = length - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) if (length == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) if (hpi_set_address(pdo, address))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) ioread32_rep(pdo->prHPI_data_auto_inc, pdata, length16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) /* take care of errata in revB DSP (2.0.1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) /* must end with non auto-inc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) *(pdata + length - 1) = ioread32(pdo->prHPI_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) static u16 hpi6000_dsp_block_write32(struct hpi_adapter_obj *pao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) u16 dsp_index, u32 hpi_address, u32 *source, u32 count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) struct hpi_hw_obj *phw = pao->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) struct dsp_obj *pdo = &phw->ado[dsp_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) u32 time_out = PCI_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) int c6711_burst_size = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) u32 local_hpi_address = hpi_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) int local_count = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) int xfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) u32 *pdata = source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) while (local_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) if (local_count > c6711_burst_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) xfer_size = c6711_burst_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) xfer_size = local_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) time_out = PCI_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) hpi_write_block(pdo, local_hpi_address, pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) xfer_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) } while (hpi6000_check_PCI2040_error_flag(pao, H6WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) && --time_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (!time_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) pdata += xfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) local_hpi_address += sizeof(u32) * xfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) local_count -= xfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) if (time_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) static u16 hpi6000_dsp_block_read32(struct hpi_adapter_obj *pao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) u16 dsp_index, u32 hpi_address, u32 *dest, u32 count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) struct hpi_hw_obj *phw = pao->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) struct dsp_obj *pdo = &phw->ado[dsp_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) u32 time_out = PCI_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) int c6711_burst_size = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) u32 local_hpi_address = hpi_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) int local_count = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) int xfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) u32 *pdata = dest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) u32 loop_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) while (local_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) if (local_count > c6711_burst_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) xfer_size = c6711_burst_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) xfer_size = local_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) time_out = PCI_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) hpi_read_block(pdo, local_hpi_address, pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) xfer_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) && --time_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) if (!time_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) pdata += xfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) local_hpi_address += sizeof(u32) * xfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) local_count -= xfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) loop_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) if (time_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) static short hpi6000_message_response_sequence(struct hpi_adapter_obj *pao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) u16 dsp_index, struct hpi_message *phm, struct hpi_response *phr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) struct hpi_hw_obj *phw = pao->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) struct dsp_obj *pdo = &phw->ado[dsp_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) u32 timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) u16 ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) u32 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) u32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) u32 *p_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) u16 error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_IDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) if (ack & HPI_HIF_ERROR_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) pao->dsp_crashed++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) return HPI6000_ERROR_MSG_RESP_IDLE_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) pao->dsp_crashed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) /* get the message address and size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) if (phw->message_buffer_address_on_dsp == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) timeout = TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) address =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) hpi_read_word(pdo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) HPI_HIF_ADDR(message_buffer_address));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) phw->message_buffer_address_on_dsp = address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) && --timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) if (!timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) return HPI6000_ERROR_MSG_GET_ADR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) address = phw->message_buffer_address_on_dsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) length = phm->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) /* send the message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) p_data = (u32 *)phm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) if (hpi6000_dsp_block_write32(pao, dsp_index, address, p_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) (u16)length / 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) return HPI6000_ERROR_MSG_RESP_BLOCKWRITE32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_GET_RESP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) return HPI6000_ERROR_MSG_RESP_GETRESPCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) hpi6000_send_dsp_interrupt(pdo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_GET_RESP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) if (ack & HPI_HIF_ERROR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) return HPI6000_ERROR_MSG_RESP_GET_RESP_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) /* get the response address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) if (phw->response_buffer_address_on_dsp == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) timeout = TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) address =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) hpi_read_word(pdo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) HPI_HIF_ADDR(response_buffer_address));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) && --timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) phw->response_buffer_address_on_dsp = address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) if (!timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) return HPI6000_ERROR_RESP_GET_ADR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) address = phw->response_buffer_address_on_dsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) /* read the length of the response back from the DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) timeout = TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) length = hpi_read_word(pdo, HPI_HIF_ADDR(length));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) } while (hpi6000_check_PCI2040_error_flag(pao, H6READ) && --timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) if (!timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) return HPI6000_ERROR_RESP_GET_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) if (length > phr->size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) return HPI_ERROR_RESPONSE_BUFFER_TOO_SMALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) /* get the response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) p_data = (u32 *)phr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) if (hpi6000_dsp_block_read32(pao, dsp_index, address, p_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) (u16)length / 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) return HPI6000_ERROR_MSG_RESP_BLOCKREAD32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) /* set i/f back to idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_IDLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) return HPI6000_ERROR_MSG_RESP_IDLECMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) hpi6000_send_dsp_interrupt(pdo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) error = hpi_validate_response(phm, phr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) /* have to set up the below defines to match stuff in the MAP file */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) #define MSG_ADDRESS (HPI_HIF_BASE+0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) #define MSG_LENGTH 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) #define RESP_ADDRESS (HPI_HIF_BASE+0x44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) #define RESP_LENGTH 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) #define QUEUE_START (HPI_HIF_BASE+0x88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) #define QUEUE_SIZE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) static short hpi6000_send_data_check_adr(u32 address, u32 length_in_dwords)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) /*#define CHECKING // comment this line in to enable checking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) #ifdef CHECKING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) if (address < (u32)MSG_ADDRESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) if (address > (u32)(QUEUE_START + QUEUE_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) if ((address + (length_in_dwords << 2)) >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) (u32)(QUEUE_START + QUEUE_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) (void)address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) (void)length_in_dwords;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) static short hpi6000_send_data(struct hpi_adapter_obj *pao, u16 dsp_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) struct hpi_message *phm, struct hpi_response *phr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) struct hpi_hw_obj *phw = pao->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) struct dsp_obj *pdo = &phw->ado[dsp_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) u32 data_sent = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) u16 ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) u32 length, address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) u32 *p_data = (u32 *)phm->u.d.u.data.pb_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) u16 time_out = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) (void)phr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) /* round dwDataSize down to nearest 4 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) while ((data_sent < (phm->u.d.u.data.data_size & ~3L))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) && --time_out) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_IDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) if (ack & HPI_HIF_ERROR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) return HPI6000_ERROR_SEND_DATA_IDLE_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) if (hpi6000_send_host_command(pao, dsp_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) HPI_HIF_SEND_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) return HPI6000_ERROR_SEND_DATA_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) hpi6000_send_dsp_interrupt(pdo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_SEND_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) if (ack & HPI_HIF_ERROR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) return HPI6000_ERROR_SEND_DATA_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) /* get the address and size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) address = hpi_read_word(pdo, HPI_HIF_ADDR(address));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) /* DSP returns number of DWORDS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) length = hpi_read_word(pdo, HPI_HIF_ADDR(length));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) } while (hpi6000_check_PCI2040_error_flag(pao, H6READ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) if (!hpi6000_send_data_check_adr(address, length))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) return HPI6000_ERROR_SEND_DATA_ADR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) /* send the data. break data into 512 DWORD blocks (2K bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) * and send using block write. 2Kbytes is the max as this is the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) * memory window given to the HPI data register by the PCI2040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) u32 len = length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) u32 blk_len = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) while (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) if (len < blk_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) blk_len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) if (hpi6000_dsp_block_write32(pao, dsp_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) address, p_data, blk_len))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) return HPI6000_ERROR_SEND_DATA_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) address += blk_len * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) p_data += blk_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) len -= blk_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_IDLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) return HPI6000_ERROR_SEND_DATA_IDLECMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) hpi6000_send_dsp_interrupt(pdo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) data_sent += length * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) if (!time_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) return HPI6000_ERROR_SEND_DATA_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) static short hpi6000_get_data(struct hpi_adapter_obj *pao, u16 dsp_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) struct hpi_message *phm, struct hpi_response *phr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) struct hpi_hw_obj *phw = pao->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) struct dsp_obj *pdo = &phw->ado[dsp_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) u32 data_got = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) u16 ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) u32 length, address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) u32 *p_data = (u32 *)phm->u.d.u.data.pb_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) (void)phr; /* this parameter not used! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) /* round dwDataSize down to nearest 4 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) while (data_got < (phm->u.d.u.data.data_size & ~3L)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_IDLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) if (ack & HPI_HIF_ERROR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) return HPI6000_ERROR_GET_DATA_IDLE_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) if (hpi6000_send_host_command(pao, dsp_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) HPI_HIF_GET_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) return HPI6000_ERROR_GET_DATA_CMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) hpi6000_send_dsp_interrupt(pdo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) ack = hpi6000_wait_dsp_ack(pao, dsp_index, HPI_HIF_GET_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) if (ack & HPI_HIF_ERROR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) return HPI6000_ERROR_GET_DATA_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) /* get the address and size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) address = hpi_read_word(pdo, HPI_HIF_ADDR(address));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) length = hpi_read_word(pdo, HPI_HIF_ADDR(length));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) } while (hpi6000_check_PCI2040_error_flag(pao, H6READ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) /* read the data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) u32 len = length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) u32 blk_len = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) while (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) if (len < blk_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) blk_len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) if (hpi6000_dsp_block_read32(pao, dsp_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) address, p_data, blk_len))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) return HPI6000_ERROR_GET_DATA_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) address += blk_len * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) p_data += blk_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) len -= blk_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) if (hpi6000_send_host_command(pao, dsp_index, HPI_HIF_IDLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) return HPI6000_ERROR_GET_DATA_IDLECMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) hpi6000_send_dsp_interrupt(pdo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) data_got += length * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) static void hpi6000_send_dsp_interrupt(struct dsp_obj *pdo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) iowrite32(0x00030003, pdo->prHPI_control); /* DSPINT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) static short hpi6000_send_host_command(struct hpi_adapter_obj *pao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) u16 dsp_index, u32 host_cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) struct hpi_hw_obj *phw = pao->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) struct dsp_obj *pdo = &phw->ado[dsp_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) u32 timeout = TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) /* set command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) hpi_write_word(pdo, HPI_HIF_ADDR(host_cmd), host_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) /* flush the FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) hpi_set_address(pdo, HPI_HIF_ADDR(host_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) } while (hpi6000_check_PCI2040_error_flag(pao, H6WRITE) && --timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) /* reset the interrupt bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) iowrite32(0x00040004, pdo->prHPI_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) if (timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) /* if the PCI2040 has recorded an HPI timeout, reset the error and return 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) static short hpi6000_check_PCI2040_error_flag(struct hpi_adapter_obj *pao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) u16 read_or_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) u32 hPI_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) struct hpi_hw_obj *phw = pao->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) /* read the error bits from the PCI2040 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) hPI_error = ioread32(phw->dw2040_HPICSR + HPI_ERROR_REPORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) if (hPI_error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) /* reset the error flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) iowrite32(0L, phw->dw2040_HPICSR + HPI_ERROR_REPORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) phw->pCI2040HPI_error_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) if (read_or_write == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) gw_pci_read_asserts++; /************* inc global */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) gw_pci_write_asserts++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) static short hpi6000_wait_dsp_ack(struct hpi_adapter_obj *pao, u16 dsp_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) u32 ack_value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) struct hpi_hw_obj *phw = pao->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) struct dsp_obj *pdo = &phw->ado[dsp_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) u32 ack = 0L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) u32 timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) u32 hPIC = 0L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) /* wait for host interrupt to signal ack is ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) timeout = TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) while (--timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) hPIC = ioread32(pdo->prHPI_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) if (hPIC & 0x04) /* 0x04 = HINT from DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) if (timeout == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) return HPI_HIF_ERROR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) /* wait for dwAckValue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) timeout = TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) while (--timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) /* read the ack mailbox */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) ack = hpi_read_word(pdo, HPI_HIF_ADDR(dsp_ack));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) if (ack == ack_value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) if ((ack & HPI_HIF_ERROR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) && !hpi6000_check_PCI2040_error_flag(pao, H6READ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) /*for (i=0;i<1000;i++) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) /* dwPause=i+1; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) if (ack & HPI_HIF_ERROR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) /* indicates bad read from DSP -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) typically 0xffffff is read for some reason */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) ack = HPI_HIF_ERROR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) if (timeout == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) ack = HPI_HIF_ERROR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) return (short)ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) static short hpi6000_update_control_cache(struct hpi_adapter_obj *pao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) struct hpi_message *phm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) const u16 dsp_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) struct hpi_hw_obj *phw = pao->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) struct dsp_obj *pdo = &phw->ado[dsp_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) u32 timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) u32 cache_dirty_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) u16 err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) hpios_dsplock_lock(pao);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) timeout = TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) cache_dirty_flag =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) hpi_read_word((struct dsp_obj *)pdo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) HPI_HIF_ADDR(control_cache_is_dirty));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) } while (hpi6000_check_PCI2040_error_flag(pao, H6READ) && --timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) if (!timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) err = HPI6000_ERROR_CONTROL_CACHE_PARAMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) if (cache_dirty_flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) /* read the cached controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) u32 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) u32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) timeout = TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) if (pdo->control_cache_address_on_dsp == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) address =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) hpi_read_word((struct dsp_obj *)pdo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) HPI_HIF_ADDR(control_cache_address));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) length = hpi_read_word((struct dsp_obj *)pdo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) HPI_HIF_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) (control_cache_size_in_bytes));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) } while (hpi6000_check_PCI2040_error_flag(pao, H6READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) && --timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) if (!timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) err = HPI6000_ERROR_CONTROL_CACHE_ADDRLEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) pdo->control_cache_address_on_dsp = address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) pdo->control_cache_length_on_dsp = length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) address = pdo->control_cache_address_on_dsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) length = pdo->control_cache_length_on_dsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) if (hpi6000_dsp_block_read32(pao, dsp_index, address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) (u32 *)&phw->control_cache[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) length / sizeof(u32))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) err = HPI6000_ERROR_CONTROL_CACHE_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) hpi_write_word((struct dsp_obj *)pdo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) HPI_HIF_ADDR(control_cache_is_dirty), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) /* flush the FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) hpi_set_address(pdo, HPI_HIF_ADDR(host_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) } while (hpi6000_check_PCI2040_error_flag(pao, H6WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) && --timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) if (!timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) err = HPI6000_ERROR_CONTROL_CACHE_FLUSH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) hpios_dsplock_unlock(pao);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) /** Get dsp index for multi DSP adapters only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) static u16 get_dsp_index(struct hpi_adapter_obj *pao, struct hpi_message *phm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) u16 ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) switch (phm->object) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) case HPI_OBJ_ISTREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) if (phm->obj_index < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) case HPI_OBJ_PROFILE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) ret = phm->obj_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) /** Complete transaction with DSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) Send message, get response, send or get stream data if any.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) struct hpi_response *phr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) u16 error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) u16 dsp_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) struct hpi_hw_obj *phw = pao->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) u16 num_dsp = phw->num_dsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) if (num_dsp < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) dsp_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) dsp_index = get_dsp_index(pao, phm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) /* is this checked on the DSP anyway? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) if ((phm->function == HPI_ISTREAM_GROUP_ADD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) || (phm->function == HPI_OSTREAM_GROUP_ADD)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) struct hpi_message hm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) u16 add_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) hm.obj_index = phm->u.d.u.stream.stream_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) hm.object = phm->u.d.u.stream.object_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) add_index = get_dsp_index(pao, &hm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) if (add_index != dsp_index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) phr->error = HPI_ERROR_NO_INTERDSP_GROUPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) hpios_dsplock_lock(pao);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) error = hpi6000_message_response_sequence(pao, dsp_index, phm, phr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) if (error) /* something failed in the HPI/DSP interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) if (phr->error) /* something failed in the DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) switch (phm->function) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) case HPI_OSTREAM_WRITE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) case HPI_ISTREAM_ANC_WRITE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) error = hpi6000_send_data(pao, dsp_index, phm, phr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) case HPI_ISTREAM_READ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) case HPI_OSTREAM_ANC_READ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) error = hpi6000_get_data(pao, dsp_index, phm, phr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) case HPI_ADAPTER_GET_ASSERT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) phr->u.ax.assert.dsp_index = 0; /* dsp 0 default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) if (num_dsp == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) if (!phr->u.ax.assert.count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) /* no assert from dsp 0, check dsp 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) error = hpi6000_message_response_sequence(pao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) 1, phm, phr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) phr->u.ax.assert.dsp_index = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) if (error >= HPI_ERROR_BACKEND_BASE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) phr->error = HPI_ERROR_DSP_COMMUNICATION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) phr->specific_error = error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) phr->error = error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) /* just the header of the response is valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) phr->size = sizeof(struct hpi_response_header);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) hpios_dsplock_unlock(pao);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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