^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * card-als4000.c - driver for Avance Logic ALS4000 based soundcards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2000 by Bart Hartgers <bart@etpmod.phys.tue.nl>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Jaroslav Kysela <perex@perex.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2002, 2008 by Andreas Mohr <hw7oshyuv3001@sneakemail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Framework borrowed from Massimo Piccioni's card-als100.c.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * NOTES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Since Avance does not provide any meaningful documentation, and I
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * bought an ALS4000 based soundcard, I was forced to base this driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * on reverse engineering.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Note: this is no longer true (thank you!):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * pretty verbose chip docu (ALS4000a.PDF) can be found on the ALSA web site.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Page numbers stated anywhere below with the "SPECS_PAGE:" tag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * refer to: ALS4000a.PDF specs Ver 1.0, May 28th, 1998.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * The ALS4000 seems to be the PCI-cousin of the ALS100. It contains an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * ALS100-like SB DSP/mixer, an OPL3 synth, a MPU401 and a gameport
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * interface. These subsystems can be mapped into ISA io-port space,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * using the PCI-interface. In addition, the PCI-bit provides DMA and IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * services to the subsystems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * While ALS4000 is very similar to a SoundBlaster, the differences in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * DMA and capturing require more changes to the SoundBlaster than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * desirable, so I made this separate driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * The ALS4000 can do real full duplex playback/capture.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * FMDAC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * - 0x4f -> port 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * - port 0x15 |= 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Enable/disable 3D sound:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * - 0x50 -> port 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * - change bit 6 (0x40) of port 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * Set QSound:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * - 0xdb -> port 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * - set port 0x15:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * 0x3e (mode 3), 0x3c (mode 2), 0x3a (mode 1), 0x38 (mode 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * Set KSound:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * - value -> some port 0x0c0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * ToDo:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * - by default, don't enable legacy game and use PCI game I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * - power management? (card can do voice wakeup according to datasheet!!)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include <linux/gameport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #include <sound/rawmidi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #include <sound/mpu401.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #include <sound/opl3.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #include <sound/sb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) MODULE_AUTHOR("Bart Hartgers <bart@etpmod.phys.tue.nl>, Andreas Mohr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) MODULE_DESCRIPTION("Avance Logic ALS4000");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) MODULE_SUPPORTED_DEVICE("{{Avance Logic,ALS4000}}");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #if IS_REACHABLE(CONFIG_GAMEPORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SUPPORT_JOYSTICK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #ifdef SUPPORT_JOYSTICK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static int joystick_port[SNDRV_CARDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) module_param_array(index, int, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) MODULE_PARM_DESC(index, "Index value for ALS4000 soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) module_param_array(id, charp, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MODULE_PARM_DESC(id, "ID string for ALS4000 soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) module_param_array(enable, bool, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MODULE_PARM_DESC(enable, "Enable ALS4000 soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #ifdef SUPPORT_JOYSTICK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) module_param_hw_array(joystick_port, int, ioport, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MODULE_PARM_DESC(joystick_port, "Joystick port address for ALS4000 soundcard. (0 = disabled)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct snd_card_als4000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* most frequent access first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned long iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct pci_dev *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct snd_sb *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #ifdef SUPPORT_JOYSTICK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct gameport *gameport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static const struct pci_device_id snd_als4000_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { 0x4005, 0x4000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, }, /* ALS4000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) MODULE_DEVICE_TABLE(pci, snd_als4000_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) enum als4k_iobase_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* IOx: B == Byte, W = Word, D = DWord; SPECS_PAGE: 37 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ALS4K_IOD_00_AC97_ACCESS = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ALS4K_IOW_04_AC97_READ = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ALS4K_IOB_06_AC97_STATUS = 0x06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ALS4K_IOB_07_IRQSTATUS = 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ALS4K_IOD_08_GCR_DATA = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ALS4K_IOB_0C_GCR_INDEX = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ALS4K_IOB_0E_IRQTYPE_SB_CR1E_MPU = 0x0e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ALS4K_IOB_10_ADLIB_ADDR0 = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ALS4K_IOB_11_ADLIB_ADDR1 = 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ALS4K_IOB_12_ADLIB_ADDR2 = 0x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ALS4K_IOB_13_ADLIB_ADDR3 = 0x13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ALS4K_IOB_14_MIXER_INDEX = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ALS4K_IOB_15_MIXER_DATA = 0x15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ALS4K_IOB_16_ESP_RESET = 0x16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ALS4K_IOB_16_ACK_FOR_CR1E = 0x16, /* 2nd function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ALS4K_IOB_18_OPL_ADDR0 = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ALS4K_IOB_19_OPL_ADDR1 = 0x19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) ALS4K_IOB_1A_ESP_RD_DATA = 0x1a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ALS4K_IOB_1C_ESP_CMD_DATA = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) ALS4K_IOB_1C_ESP_WR_STATUS = 0x1c, /* 2nd function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ALS4K_IOB_1E_ESP_RD_STATUS8 = 0x1e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ALS4K_IOB_1F_ESP_RD_STATUS16 = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ALS4K_IOB_20_ESP_GAMEPORT_200 = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ALS4K_IOB_21_ESP_GAMEPORT_201 = 0x21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ALS4K_IOB_30_MIDI_DATA = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ALS4K_IOB_31_MIDI_STATUS = 0x31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ALS4K_IOB_31_MIDI_COMMAND = 0x31, /* 2nd function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) enum als4k_iobase_0e_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) ALS4K_IOB_0E_MPU_IRQ = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ALS4K_IOB_0E_CR1E_IRQ = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ALS4K_IOB_0E_SB_DMA_IRQ = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) enum als4k_gcr_t { /* all registers 32bit wide; SPECS_PAGE: 38 to 42 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ALS4K_GCR8C_MISC_CTRL = 0x8c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ALS4K_GCR90_TEST_MODE_REG = 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ALS4K_GCR91_DMA0_ADDR = 0x91,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ALS4K_GCR92_DMA0_MODE_COUNT = 0x92,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ALS4K_GCR93_DMA1_ADDR = 0x93,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ALS4K_GCR94_DMA1_MODE_COUNT = 0x94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ALS4K_GCR95_DMA3_ADDR = 0x95,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ALS4K_GCR96_DMA3_MODE_COUNT = 0x96,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ALS4K_GCR99_DMA_EMULATION_CTRL = 0x99,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ALS4K_GCRA0_FIFO1_CURRENT_ADDR = 0xa0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ALS4K_GCRA1_FIFO1_STATUS_BYTECOUNT = 0xa1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ALS4K_GCRA2_FIFO2_PCIADDR = 0xa2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ALS4K_GCRA3_FIFO2_COUNT = 0xa3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ALS4K_GCRA4_FIFO2_CURRENT_ADDR = 0xa4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ALS4K_GCRA5_FIFO1_STATUS_BYTECOUNT = 0xa5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ALS4K_GCRA6_PM_CTRL = 0xa6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ALS4K_GCRA7_PCI_ACCESS_STORAGE = 0xa7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ALS4K_GCRA8_LEGACY_CFG1 = 0xa8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ALS4K_GCRA9_LEGACY_CFG2 = 0xa9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ALS4K_GCRFF_DUMMY_SCRATCH = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) enum als4k_gcr8c_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ALS4K_GCR8C_IRQ_MASK_CTRL_ENABLE = 0x8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ALS4K_GCR8C_CHIP_REV_MASK = 0xf0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static inline void snd_als4k_iobase_writeb(unsigned long iobase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) enum als4k_iobase_t reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) outb(val, iobase + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static inline void snd_als4k_iobase_writel(unsigned long iobase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) enum als4k_iobase_t reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) outl(val, iobase + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static inline u8 snd_als4k_iobase_readb(unsigned long iobase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) enum als4k_iobase_t reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return inb(iobase + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static inline u32 snd_als4k_iobase_readl(unsigned long iobase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) enum als4k_iobase_t reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return inl(iobase + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static inline void snd_als4k_gcr_write_addr(unsigned long iobase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) enum als4k_gcr_t reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) snd_als4k_iobase_writeb(iobase, ALS4K_IOB_0C_GCR_INDEX, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) snd_als4k_iobase_writel(iobase, ALS4K_IOD_08_GCR_DATA, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static inline void snd_als4k_gcr_write(struct snd_sb *sb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) enum als4k_gcr_t reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) snd_als4k_gcr_write_addr(sb->alt_port, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static inline u32 snd_als4k_gcr_read_addr(unsigned long iobase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) enum als4k_gcr_t reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* SPECS_PAGE: 37/38 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) snd_als4k_iobase_writeb(iobase, ALS4K_IOB_0C_GCR_INDEX, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return snd_als4k_iobase_readl(iobase, ALS4K_IOD_08_GCR_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static inline u32 snd_als4k_gcr_read(struct snd_sb *sb, enum als4k_gcr_t reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return snd_als4k_gcr_read_addr(sb->alt_port, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) enum als4k_cr_t { /* all registers 8bit wide; SPECS_PAGE: 20 to 23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ALS4K_CR0_SB_CONFIG = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ALS4K_CR2_MISC_CONTROL = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ALS4K_CR3_CONFIGURATION = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ALS4K_CR17_FIFO_STATUS = 0x17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ALS4K_CR18_ESP_MAJOR_VERSION = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ALS4K_CR19_ESP_MINOR_VERSION = 0x19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ALS4K_CR1A_MPU401_UART_MODE_CONTROL = 0x1a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ALS4K_CR1C_FIFO2_BLOCK_LENGTH_LO = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ALS4K_CR1D_FIFO2_BLOCK_LENGTH_HI = 0x1d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ALS4K_CR1E_FIFO2_CONTROL = 0x1e, /* secondary PCM FIFO (recording) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ALS4K_CR3A_MISC_CONTROL = 0x3a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ALS4K_CR3B_CRC32_BYTE0 = 0x3b, /* for testing, activate via CR3A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ALS4K_CR3C_CRC32_BYTE1 = 0x3c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ALS4K_CR3D_CRC32_BYTE2 = 0x3d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ALS4K_CR3E_CRC32_BYTE3 = 0x3e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) enum als4k_cr0_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ALS4K_CR0_DMA_CONTIN_MODE_CTRL = 0x02, /* IRQ/FIFO controlled for 0/1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ALS4K_CR0_DMA_90H_MODE_CTRL = 0x04, /* IRQ/FIFO controlled for 0/1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ALS4K_CR0_MX80_81_REG_WRITE_ENABLE = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static inline void snd_als4_cr_write(struct snd_sb *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) enum als4k_cr_t reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* Control Register is reg | 0xc0 (bit 7, 6 set) on sbmixer_index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * NOTE: assumes chip->mixer_lock to be locked externally already!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * SPECS_PAGE: 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) snd_sbmixer_write(chip, reg | 0xc0, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static inline u8 snd_als4_cr_read(struct snd_sb *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) enum als4k_cr_t reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* NOTE: assumes chip->mixer_lock to be locked externally already! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return snd_sbmixer_read(chip, reg | 0xc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static void snd_als4000_set_rate(struct snd_sb *chip, unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (!(chip->mode & SB_RATE_LOCK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) snd_sbdsp_command(chip, SB_DSP_SAMPLE_RATE_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) snd_sbdsp_command(chip, rate>>8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) snd_sbdsp_command(chip, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static inline void snd_als4000_set_capture_dma(struct snd_sb *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) dma_addr_t addr, unsigned size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* SPECS_PAGE: 40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) snd_als4k_gcr_write(chip, ALS4K_GCRA2_FIFO2_PCIADDR, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) snd_als4k_gcr_write(chip, ALS4K_GCRA3_FIFO2_COUNT, (size-1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static inline void snd_als4000_set_playback_dma(struct snd_sb *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) dma_addr_t addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) unsigned size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* SPECS_PAGE: 38 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) snd_als4k_gcr_write(chip, ALS4K_GCR91_DMA0_ADDR, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) snd_als4k_gcr_write(chip, ALS4K_GCR92_DMA0_MODE_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) (size-1)|0x180000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define ALS4000_FORMAT_SIGNED (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define ALS4000_FORMAT_16BIT (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define ALS4000_FORMAT_STEREO (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static int snd_als4000_get_format(struct snd_pcm_runtime *runtime)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (snd_pcm_format_signed(runtime->format))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) result |= ALS4000_FORMAT_SIGNED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (snd_pcm_format_physical_width(runtime->format) == 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) result |= ALS4000_FORMAT_16BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (runtime->channels > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) result |= ALS4000_FORMAT_STEREO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* structure for setting up playback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) unsigned char dsp_cmd, dma_on, dma_off, format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) } playback_cmd_vals[]={
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* ALS4000_FORMAT_U8_MONO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) { SB_DSP4_OUT8_AI, SB_DSP_DMA8_ON, SB_DSP_DMA8_OFF, SB_DSP4_MODE_UNS_MONO },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* ALS4000_FORMAT_S8_MONO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) { SB_DSP4_OUT8_AI, SB_DSP_DMA8_ON, SB_DSP_DMA8_OFF, SB_DSP4_MODE_SIGN_MONO },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* ALS4000_FORMAT_U16L_MONO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) { SB_DSP4_OUT16_AI, SB_DSP_DMA16_ON, SB_DSP_DMA16_OFF, SB_DSP4_MODE_UNS_MONO },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* ALS4000_FORMAT_S16L_MONO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) { SB_DSP4_OUT16_AI, SB_DSP_DMA16_ON, SB_DSP_DMA16_OFF, SB_DSP4_MODE_SIGN_MONO },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* ALS4000_FORMAT_U8_STEREO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) { SB_DSP4_OUT8_AI, SB_DSP_DMA8_ON, SB_DSP_DMA8_OFF, SB_DSP4_MODE_UNS_STEREO },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* ALS4000_FORMAT_S8_STEREO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) { SB_DSP4_OUT8_AI, SB_DSP_DMA8_ON, SB_DSP_DMA8_OFF, SB_DSP4_MODE_SIGN_STEREO },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* ALS4000_FORMAT_U16L_STEREO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) { SB_DSP4_OUT16_AI, SB_DSP_DMA16_ON, SB_DSP_DMA16_OFF, SB_DSP4_MODE_UNS_STEREO },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* ALS4000_FORMAT_S16L_STEREO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) { SB_DSP4_OUT16_AI, SB_DSP_DMA16_ON, SB_DSP_DMA16_OFF, SB_DSP4_MODE_SIGN_STEREO },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define playback_cmd(chip) (playback_cmd_vals[(chip)->playback_format])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* structure for setting up capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) enum { CMD_WIDTH8=0x04, CMD_SIGNED=0x10, CMD_MONO=0x80, CMD_STEREO=0xA0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static const unsigned char capture_cmd_vals[]=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) CMD_WIDTH8|CMD_MONO, /* ALS4000_FORMAT_U8_MONO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) CMD_WIDTH8|CMD_SIGNED|CMD_MONO, /* ALS4000_FORMAT_S8_MONO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) CMD_MONO, /* ALS4000_FORMAT_U16L_MONO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) CMD_SIGNED|CMD_MONO, /* ALS4000_FORMAT_S16L_MONO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) CMD_WIDTH8|CMD_STEREO, /* ALS4000_FORMAT_U8_STEREO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) CMD_WIDTH8|CMD_SIGNED|CMD_STEREO, /* ALS4000_FORMAT_S8_STEREO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) CMD_STEREO, /* ALS4000_FORMAT_U16L_STEREO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) CMD_SIGNED|CMD_STEREO, /* ALS4000_FORMAT_S16L_STEREO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define capture_cmd(chip) (capture_cmd_vals[(chip)->capture_format])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static int snd_als4000_capture_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct snd_sb *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) unsigned long size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) unsigned count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) chip->capture_format = snd_als4000_get_format(runtime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) size = snd_pcm_lib_buffer_bytes(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) count = snd_pcm_lib_period_bytes(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (chip->capture_format & ALS4000_FORMAT_16BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) count >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) snd_als4000_set_rate(chip, runtime->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) snd_als4000_set_capture_dma(chip, runtime->dma_addr, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) spin_lock_irq(&chip->mixer_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) snd_als4_cr_write(chip, ALS4K_CR1C_FIFO2_BLOCK_LENGTH_LO, count & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) snd_als4_cr_write(chip, ALS4K_CR1D_FIFO2_BLOCK_LENGTH_HI, count >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) spin_unlock_irq(&chip->mixer_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static int snd_als4000_playback_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct snd_sb *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) unsigned long size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) unsigned count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) chip->playback_format = snd_als4000_get_format(runtime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) size = snd_pcm_lib_buffer_bytes(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) count = snd_pcm_lib_period_bytes(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (chip->playback_format & ALS4000_FORMAT_16BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) count >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* FIXME: from second playback on, there's a lot more clicks and pops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * involved here than on first playback. Fiddling with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * tons of different settings didn't help (DMA, speaker on/off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * reordering, ...). Something seems to get enabled on playback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * that I haven't found out how to disable again, which then causes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * the switching pops to reach the speakers the next time here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) snd_als4000_set_rate(chip, runtime->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) snd_als4000_set_playback_dma(chip, runtime->dma_addr, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* SPEAKER_ON not needed, since dma_on seems to also enable speaker */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* snd_sbdsp_command(chip, SB_DSP_SPEAKER_ON); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) snd_sbdsp_command(chip, playback_cmd(chip).dsp_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) snd_sbdsp_command(chip, playback_cmd(chip).format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) snd_sbdsp_command(chip, count & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) snd_sbdsp_command(chip, count >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) snd_sbdsp_command(chip, playback_cmd(chip).dma_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static int snd_als4000_capture_trigger(struct snd_pcm_substream *substream, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct snd_sb *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) int result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* FIXME race condition in here!!!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) chip->mode non-atomic update gets consistently protected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) by reg_lock always, _except_ for this place!!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) Probably need to take reg_lock as outer (or inner??) lock, too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) (or serialize both lock operations? probably not, though... - racy?)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) spin_lock(&chip->mixer_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) chip->mode |= SB_RATE_LOCK_CAPTURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) snd_als4_cr_write(chip, ALS4K_CR1E_FIFO2_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) capture_cmd(chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) chip->mode &= ~SB_RATE_LOCK_CAPTURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) snd_als4_cr_write(chip, ALS4K_CR1E_FIFO2_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) capture_cmd(chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) result = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) spin_unlock(&chip->mixer_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static int snd_als4000_playback_trigger(struct snd_pcm_substream *substream, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct snd_sb *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) int result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) spin_lock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) chip->mode |= SB_RATE_LOCK_PLAYBACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) snd_sbdsp_command(chip, playback_cmd(chip).dma_on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) snd_sbdsp_command(chip, playback_cmd(chip).dma_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) chip->mode &= ~SB_RATE_LOCK_PLAYBACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) result = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) spin_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static snd_pcm_uframes_t snd_als4000_capture_pointer(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct snd_sb *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) unsigned int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) spin_lock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) result = snd_als4k_gcr_read(chip, ALS4K_GCRA4_FIFO2_CURRENT_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) spin_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) result &= 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return bytes_to_frames( substream->runtime, result );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static snd_pcm_uframes_t snd_als4000_playback_pointer(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct snd_sb *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) unsigned result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) spin_lock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) result = snd_als4k_gcr_read(chip, ALS4K_GCRA0_FIFO1_CURRENT_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) spin_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) result &= 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return bytes_to_frames( substream->runtime, result );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* FIXME: this IRQ routine doesn't really support IRQ sharing (we always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * return IRQ_HANDLED no matter whether we actually had an IRQ flag or not).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * ALS4000a.PDF writes that while ACKing IRQ in PCI block will *not* ACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * the IRQ in the SB core, ACKing IRQ in SB block *will* ACK the PCI IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * register (alt_port + ALS4K_IOB_0E_IRQTYPE_SB_CR1E_MPU). Probably something
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * could be optimized here to query/write one register only...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * And even if both registers need to be queried, then there's still the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * question of whether it's actually correct to ACK PCI IRQ before reading
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * SB IRQ like we do now, since ALS4000a.PDF mentions that PCI IRQ will *clear*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * SB IRQ status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * (hmm, SPECS_PAGE: 38 mentions it the other way around!)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * And do we *really* need the lock here for *reading* SB_DSP4_IRQSTATUS??
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static irqreturn_t snd_als4000_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct snd_sb *chip = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) unsigned pci_irqstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) unsigned sb_irqstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* find out which bit of the ALS4000 PCI block produced the interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) SPECS_PAGE: 38, 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) pci_irqstatus = snd_als4k_iobase_readb(chip->alt_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) ALS4K_IOB_0E_IRQTYPE_SB_CR1E_MPU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if ((pci_irqstatus & ALS4K_IOB_0E_SB_DMA_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) && (chip->playback_substream)) /* playback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) snd_pcm_period_elapsed(chip->playback_substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if ((pci_irqstatus & ALS4K_IOB_0E_CR1E_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) && (chip->capture_substream)) /* capturing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) snd_pcm_period_elapsed(chip->capture_substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if ((pci_irqstatus & ALS4K_IOB_0E_MPU_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) && (chip->rmidi)) /* MPU401 interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* ACK the PCI block IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) snd_als4k_iobase_writeb(chip->alt_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) ALS4K_IOB_0E_IRQTYPE_SB_CR1E_MPU, pci_irqstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) spin_lock(&chip->mixer_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /* SPECS_PAGE: 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) sb_irqstatus = snd_sbmixer_read(chip, SB_DSP4_IRQSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) spin_unlock(&chip->mixer_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (sb_irqstatus & SB_IRQTYPE_8BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) snd_sb_ack_8bit(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (sb_irqstatus & SB_IRQTYPE_16BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) snd_sb_ack_16bit(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (sb_irqstatus & SB_IRQTYPE_MPUIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) inb(chip->mpu_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (sb_irqstatus & ALS4K_IRQTYPE_CR1E_DMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) snd_als4k_iobase_readb(chip->alt_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) ALS4K_IOB_16_ACK_FOR_CR1E);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /* dev_dbg(chip->card->dev, "als4000: irq 0x%04x 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) pci_irqstatus, sb_irqstatus); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /* only ack the things we actually handled above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return IRQ_RETVAL(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) (pci_irqstatus & (ALS4K_IOB_0E_SB_DMA_IRQ|ALS4K_IOB_0E_CR1E_IRQ|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) ALS4K_IOB_0E_MPU_IRQ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) || (sb_irqstatus & (SB_IRQTYPE_8BIT|SB_IRQTYPE_16BIT|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) SB_IRQTYPE_MPUIN|ALS4K_IRQTYPE_CR1E_DMA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /*****************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static const struct snd_pcm_hardware snd_als4000_playback =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) SNDRV_PCM_INFO_MMAP_VALID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE, /* formats */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .rate_min = 4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .buffer_bytes_max = 65536,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .period_bytes_min = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .period_bytes_max = 65536,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .periods_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .periods_max = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .fifo_size = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static const struct snd_pcm_hardware snd_als4000_capture =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) SNDRV_PCM_INFO_MMAP_VALID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_U16_LE, /* formats */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .rate_min = 4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .buffer_bytes_max = 65536,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .period_bytes_min = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .period_bytes_max = 65536,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .periods_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .periods_max = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .fifo_size = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /*****************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static int snd_als4000_playback_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) struct snd_sb *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) chip->playback_substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) runtime->hw = snd_als4000_playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static int snd_als4000_playback_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) struct snd_sb *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) chip->playback_substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) static int snd_als4000_capture_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) struct snd_sb *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) chip->capture_substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) runtime->hw = snd_als4000_capture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static int snd_als4000_capture_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) struct snd_sb *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) chip->capture_substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /******************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static const struct snd_pcm_ops snd_als4000_playback_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .open = snd_als4000_playback_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .close = snd_als4000_playback_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .prepare = snd_als4000_playback_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .trigger = snd_als4000_playback_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .pointer = snd_als4000_playback_pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) static const struct snd_pcm_ops snd_als4000_capture_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .open = snd_als4000_capture_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .close = snd_als4000_capture_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .prepare = snd_als4000_capture_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .trigger = snd_als4000_capture_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .pointer = snd_als4000_capture_pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static int snd_als4000_pcm(struct snd_sb *chip, int device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) err = snd_pcm_new(chip->card, "ALS4000 DSP", device, 1, 1, &pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) pcm->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_als4000_playback_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_als4000_capture_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) &chip->pci->dev, 64*1024, 64*1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) chip->pcm = pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /******************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) static void snd_als4000_set_addr(unsigned long iobase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) unsigned int sb_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) unsigned int mpu_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) unsigned int opl_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) unsigned int game_io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) u32 cfg1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) u32 cfg2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (mpu_io > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) cfg2 |= (mpu_io | 1) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (sb_io > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) cfg2 |= (sb_io | 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (game_io > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) cfg1 |= (game_io | 1) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (opl_io > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) cfg1 |= (opl_io | 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) snd_als4k_gcr_write_addr(iobase, ALS4K_GCRA8_LEGACY_CFG1, cfg1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) snd_als4k_gcr_write_addr(iobase, ALS4K_GCRA9_LEGACY_CFG2, cfg2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) static void snd_als4000_configure(struct snd_sb *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) /* do some more configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) spin_lock_irq(&chip->mixer_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) tmp = snd_als4_cr_read(chip, ALS4K_CR0_SB_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) snd_als4_cr_write(chip, ALS4K_CR0_SB_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) tmp|ALS4K_CR0_MX80_81_REG_WRITE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) /* always select DMA channel 0, since we do not actually use DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) * SPECS_PAGE: 19/20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) snd_sbmixer_write(chip, SB_DSP4_DMASETUP, SB_DMASETUP_DMA0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) snd_als4_cr_write(chip, ALS4K_CR0_SB_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) tmp & ~ALS4K_CR0_MX80_81_REG_WRITE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) spin_unlock_irq(&chip->mixer_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) /* enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) snd_als4k_gcr_write(chip, ALS4K_GCR8C_MISC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) ALS4K_GCR8C_IRQ_MASK_CTRL_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /* SPECS_PAGE: 39 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) for (i = ALS4K_GCR91_DMA0_ADDR; i <= ALS4K_GCR96_DMA3_MODE_COUNT; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) snd_als4k_gcr_write(chip, i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) /* enable burst mode to prevent dropouts during high PCI bus usage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) snd_als4k_gcr_write(chip, ALS4K_GCR99_DMA_EMULATION_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) (snd_als4k_gcr_read(chip, ALS4K_GCR99_DMA_EMULATION_CTRL) & ~0x07) | 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #ifdef SUPPORT_JOYSTICK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static int snd_als4000_create_gameport(struct snd_card_als4000 *acard, int dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) struct gameport *gp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) int io_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (joystick_port[dev] == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (joystick_port[dev] == 1) { /* auto-detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) for (io_port = 0x200; io_port <= 0x218; io_port += 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) r = request_region(io_port, 8, "ALS4000 gameport");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) io_port = joystick_port[dev];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) r = request_region(io_port, 8, "ALS4000 gameport");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (!r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) dev_warn(&acard->pci->dev, "cannot reserve joystick ports\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) acard->gameport = gp = gameport_allocate_port();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (!gp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) dev_err(&acard->pci->dev, "cannot allocate memory for gameport\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) release_and_free_resource(r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) gameport_set_name(gp, "ALS4000 Gameport");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) gameport_set_phys(gp, "pci%s/gameport0", pci_name(acard->pci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) gameport_set_dev_parent(gp, &acard->pci->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) gp->io = io_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) gameport_set_port_data(gp, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /* Enable legacy joystick port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) snd_als4000_set_addr(acard->iobase, 0, 0, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) gameport_register_port(acard->gameport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static void snd_als4000_free_gameport(struct snd_card_als4000 *acard)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (acard->gameport) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) struct resource *r = gameport_get_port_data(acard->gameport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) gameport_unregister_port(acard->gameport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) acard->gameport = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /* disable joystick */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) snd_als4000_set_addr(acard->iobase, 0, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) release_and_free_resource(r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static inline int snd_als4000_create_gameport(struct snd_card_als4000 *acard, int dev) { return -ENOSYS; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) static inline void snd_als4000_free_gameport(struct snd_card_als4000 *acard) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static void snd_card_als4000_free( struct snd_card *card )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) struct snd_card_als4000 *acard = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) /* make sure that interrupts are disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) snd_als4k_gcr_write_addr(acard->iobase, ALS4K_GCR8C_MISC_CTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /* free resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) snd_als4000_free_gameport(acard);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) pci_release_regions(acard->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) pci_disable_device(acard->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) static int snd_card_als4000_probe(struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) const struct pci_device_id *pci_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) static int dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) struct snd_card_als4000 *acard;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) unsigned long iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) struct snd_sb *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) struct snd_opl3 *opl3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) unsigned short word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (dev >= SNDRV_CARDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (!enable[dev]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) dev++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /* enable PCI device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if ((err = pci_enable_device(pci)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) /* check, if we can restrict PCI DMA transfers to 24 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (dma_set_mask(&pci->dev, DMA_BIT_MASK(24)) < 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(24)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) dev_err(&pci->dev, "architecture does not support 24bit PCI busmaster DMA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if ((err = pci_request_regions(pci, "ALS4000")) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) iobase = pci_resource_start(pci, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) pci_read_config_word(pci, PCI_COMMAND, &word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) pci_write_config_word(pci, PCI_COMMAND, word | PCI_COMMAND_IO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) pci_set_master(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) sizeof(*acard) /* private_data: acard */,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) &card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) pci_release_regions(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) acard = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) acard->pci = pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) acard->iobase = iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) card->private_free = snd_card_als4000_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) /* disable all legacy ISA stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) snd_als4000_set_addr(acard->iobase, 0, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if ((err = snd_sbdsp_create(card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) iobase + ALS4K_IOB_10_ADLIB_ADDR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) pci->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) /* internally registered as IRQF_SHARED in case of ALS4000 SB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) snd_als4000_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) SB_HW_ALS4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) &chip)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) acard->chip = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) chip->pci = pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) chip->alt_port = iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) snd_als4000_configure(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) strcpy(card->driver, "ALS4000");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) strcpy(card->shortname, "Avance Logic ALS4000");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) sprintf(card->longname, "%s at 0x%lx, irq %i",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) card->shortname, chip->alt_port, chip->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if ((err = snd_mpu401_uart_new( card, 0, MPU401_HW_ALS4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) iobase + ALS4K_IOB_30_MIDI_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) MPU401_INFO_INTEGRATED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) MPU401_INFO_IRQ_HOOK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) -1, &chip->rmidi)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) dev_err(&pci->dev, "no MPU-401 device at 0x%lx?\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) iobase + ALS4K_IOB_30_MIDI_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) /* FIXME: ALS4000 has interesting MPU401 configuration features
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) * at ALS4K_CR1A_MPU401_UART_MODE_CONTROL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) * (pass-thru / UART switching, fast MIDI clock, etc.),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) * however there doesn't seem to be an ALSA API for this...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) * SPECS_PAGE: 21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if ((err = snd_als4000_pcm(chip, 0)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if ((err = snd_sbmixer_new(chip)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (snd_opl3_create(card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) iobase + ALS4K_IOB_10_ADLIB_ADDR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) iobase + ALS4K_IOB_12_ADLIB_ADDR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) OPL3_HW_AUTO, 1, &opl3) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) dev_err(&pci->dev, "no OPL device at 0x%lx-0x%lx?\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) iobase + ALS4K_IOB_10_ADLIB_ADDR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) iobase + ALS4K_IOB_12_ADLIB_ADDR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) snd_als4000_create_gameport(acard, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if ((err = snd_card_register(card)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) pci_set_drvdata(pci, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) dev++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) out_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) static void snd_card_als4000_remove(struct pci_dev *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) snd_card_free(pci_get_drvdata(pci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) static int snd_als4000_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) struct snd_card_als4000 *acard = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) struct snd_sb *chip = acard->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) snd_sbmixer_suspend(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) static int snd_als4000_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) struct snd_card_als4000 *acard = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) struct snd_sb *chip = acard->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) snd_als4000_configure(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) snd_sbdsp_reset(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) snd_sbmixer_resume(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) #ifdef SUPPORT_JOYSTICK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) if (acard->gameport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) snd_als4000_set_addr(acard->iobase, 0, 0, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) snd_power_change_state(card, SNDRV_CTL_POWER_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) static SIMPLE_DEV_PM_OPS(snd_als4000_pm, snd_als4000_suspend, snd_als4000_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) #define SND_ALS4000_PM_OPS &snd_als4000_pm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) #define SND_ALS4000_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) static struct pci_driver als4000_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .id_table = snd_als4000_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .probe = snd_card_als4000_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .remove = snd_card_als4000_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .pm = SND_ALS4000_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) module_pci_driver(als4000_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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