^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * als300.c - driver for Avance Logic ALS300/ALS300+ soundcards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2005 by Ash Willis <ashwillis@programmer.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * TODO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * 4 channel playback for ALS300+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * gameport
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * mpu401
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * opl3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * NOTES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * The BLOCK_COUNTER registers for the ALS300(+) return a figure related to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * the position in the current period, NOT the whole buffer. It is important
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * to know which period we are in so we can calculate the correct pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * This is why we always use 2 periods. We can then use a flip-flop variable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * to keep track of what period we are in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <sound/control.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <sound/ac97_codec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <sound/opl3.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* snd_als300_set_irq_flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IRQ_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IRQ_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* I/O port layout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AC97_ACCESS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AC97_READ 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AC97_STATUS 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AC97_DATA_AVAIL (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AC97_BUSY (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ALS300_IRQ_STATUS 0x07 /* ALS300 Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IRQ_PLAYBACK (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IRQ_CAPTURE (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define GCR_DATA 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define GCR_INDEX 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ALS300P_DRAM_IRQ_STATUS 0x0D /* ALS300+ Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MPU_IRQ_STATUS 0x0E /* ALS300 Rev. E+, ALS300+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ALS300P_IRQ_STATUS 0x0F /* ALS300+ Only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* General Control Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PLAYBACK_START 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PLAYBACK_END 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PLAYBACK_CONTROL 0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define TRANSFER_START (1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define FIFO_PAUSE (1<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RECORD_START 0x83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RECORD_END 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RECORD_CONTROL 0x85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DRAM_WRITE_CONTROL 0x8B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define WRITE_TRANS_START (1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DRAM_MODE_2 (1<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MISC_CONTROL 0x8C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define IRQ_SET_BIT (1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define VMUTE_NORMAL (1<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MMUTE_NORMAL (1<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MUS_VOC_VOL 0x8E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PLAYBACK_BLOCK_COUNTER 0x9A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define RECORD_BLOCK_COUNTER 0x9B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define DEBUG_PLAY_REC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #if DEBUG_PLAY_REC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define snd_als300_dbgplay(format, args...) printk(KERN_ERR format, ##args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define snd_als300_dbgplay(format, args...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) enum {DEVICE_ALS300, DEVICE_ALS300_PLUS};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) MODULE_AUTHOR("Ash Willis <ashwillis@programmer.net>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MODULE_DESCRIPTION("Avance Logic ALS300");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MODULE_SUPPORTED_DEVICE("{{Avance Logic,ALS300},{Avance Logic,ALS300+}}");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) module_param_array(index, int, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MODULE_PARM_DESC(index, "Index value for ALS300 sound card.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) module_param_array(id, charp, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) MODULE_PARM_DESC(id, "ID string for ALS300 sound card.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) module_param_array(enable, bool, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MODULE_PARM_DESC(enable, "Enable ALS300 sound card.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct snd_als300 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned long port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) spinlock_t reg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct pci_dev *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct snd_pcm_substream *playback_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct snd_pcm_substream *capture_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct snd_ac97 *ac97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct snd_opl3 *opl3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct resource *res_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int chip_type; /* ALS300 or ALS300+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) char revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct snd_als300_substream_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int period_flipflop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int control_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int block_counter_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static const struct pci_device_id snd_als300_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { 0x4005, 0x0300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALS300 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { 0x4005, 0x0308, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALS300_PLUS },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) MODULE_DEVICE_TABLE(pci, snd_als300_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static inline u32 snd_als300_gcr_read(unsigned long port, unsigned short reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) outb(reg, port+GCR_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return inl(port+GCR_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static inline void snd_als300_gcr_write(unsigned long port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned short reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) outb(reg, port+GCR_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) outl(val, port+GCR_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* Enable/Disable Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static void snd_als300_set_irq_flag(struct snd_als300 *chip, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u32 tmp = snd_als300_gcr_read(chip->port, MISC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* boolean XOR check, since old vs. new hardware have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) directly reversed bit setting for ENABLE and DISABLE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ALS300+ acts like newer versions of ALS300 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (((chip->revision > 5 || chip->chip_type == DEVICE_ALS300_PLUS) ^
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) (cmd == IRQ_ENABLE)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) tmp |= IRQ_SET_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) tmp &= ~IRQ_SET_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) snd_als300_gcr_write(chip->port, MISC_CONTROL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static int snd_als300_free(struct snd_als300 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) snd_als300_set_irq_flag(chip, IRQ_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (chip->irq >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) free_irq(chip->irq, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) pci_release_regions(chip->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) pci_disable_device(chip->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) kfree(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static int snd_als300_dev_free(struct snd_device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct snd_als300 *chip = device->device_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return snd_als300_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static irqreturn_t snd_als300_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct snd_als300 *chip = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct snd_als300_substream_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) status = inb(chip->port+ALS300_IRQ_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (!status) /* shared IRQ, for different device?? Exit ASAP! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* ACK everything ASAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) outb(status, chip->port+ALS300_IRQ_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (status & IRQ_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (chip->pcm && chip->playback_substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) data = chip->playback_substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) data->period_flipflop ^= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) snd_pcm_period_elapsed(chip->playback_substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) snd_als300_dbgplay("IRQ_PLAYBACK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (status & IRQ_CAPTURE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (chip->pcm && chip->capture_substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) data = chip->capture_substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) data->period_flipflop ^= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) snd_pcm_period_elapsed(chip->capture_substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) snd_als300_dbgplay("IRQ_CAPTURE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static irqreturn_t snd_als300plus_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u8 general, mpu, dram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct snd_als300 *chip = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct snd_als300_substream_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) general = inb(chip->port+ALS300P_IRQ_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) mpu = inb(chip->port+MPU_IRQ_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) dram = inb(chip->port+ALS300P_DRAM_IRQ_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* shared IRQ, for different device?? Exit ASAP! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if ((general == 0) && ((mpu & 0x80) == 0) && ((dram & 0x01) == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (general & IRQ_PLAYBACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (chip->pcm && chip->playback_substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) outb(IRQ_PLAYBACK, chip->port+ALS300P_IRQ_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) data = chip->playback_substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) data->period_flipflop ^= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) snd_pcm_period_elapsed(chip->playback_substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) snd_als300_dbgplay("IRQ_PLAYBACK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (general & IRQ_CAPTURE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (chip->pcm && chip->capture_substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) outb(IRQ_CAPTURE, chip->port+ALS300P_IRQ_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) data = chip->capture_substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) data->period_flipflop ^= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) snd_pcm_period_elapsed(chip->capture_substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) snd_als300_dbgplay("IRQ_CAPTURE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* FIXME: Ack other interrupt types. Not important right now as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * those other devices aren't enabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static void snd_als300_remove(struct pci_dev *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) snd_card_free(pci_get_drvdata(pci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static unsigned short snd_als300_ac97_read(struct snd_ac97 *ac97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) unsigned short reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct snd_als300 *chip = ac97->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) for (i = 0; i < 1000; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if ((inb(chip->port+AC97_STATUS) & (AC97_BUSY)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) outl((reg << 24) | (1 << 31), chip->port+AC97_ACCESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) for (i = 0; i < 1000; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if ((inb(chip->port+AC97_STATUS) & (AC97_DATA_AVAIL)) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return inw(chip->port+AC97_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static void snd_als300_ac97_write(struct snd_ac97 *ac97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) unsigned short reg, unsigned short val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct snd_als300 *chip = ac97->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) for (i = 0; i < 1000; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if ((inb(chip->port+AC97_STATUS) & (AC97_BUSY)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) outl((reg << 24) | val, chip->port+AC97_ACCESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static int snd_als300_ac97(struct snd_als300 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct snd_ac97_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct snd_ac97_template ac97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static const struct snd_ac97_bus_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .write = snd_als300_ac97_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .read = snd_als300_ac97_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &bus)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) memset(&ac97, 0, sizeof(ac97));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ac97.private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return snd_ac97_mixer(bus, &ac97, &chip->ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* hardware definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * In AC97 mode, we always use 48k/16bit/stereo.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * Any request to change data type is ignored by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * the card when it is running outside of legacy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static const struct snd_pcm_hardware snd_als300_playback_hw =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .info = (SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) SNDRV_PCM_INFO_PAUSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) SNDRV_PCM_INFO_MMAP_VALID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .formats = SNDRV_PCM_FMTBIT_S16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .rates = SNDRV_PCM_RATE_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .rate_min = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .buffer_bytes_max = 64 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .period_bytes_min = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .period_bytes_max = 32 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .periods_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static const struct snd_pcm_hardware snd_als300_capture_hw =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .info = (SNDRV_PCM_INFO_MMAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) SNDRV_PCM_INFO_PAUSE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) SNDRV_PCM_INFO_MMAP_VALID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .formats = SNDRV_PCM_FMTBIT_S16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .rates = SNDRV_PCM_RATE_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .rate_min = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .channels_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .buffer_bytes_max = 64 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .period_bytes_min = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .period_bytes_max = 32 * 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .periods_min = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .periods_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static int snd_als300_playback_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct snd_als300 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct snd_als300_substream_data *data = kzalloc(sizeof(*data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) chip->playback_substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) runtime->hw = snd_als300_playback_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) runtime->private_data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) data->control_register = PLAYBACK_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) data->block_counter_register = PLAYBACK_BLOCK_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static int snd_als300_playback_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct snd_als300 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct snd_als300_substream_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) data = substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) kfree(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) chip->playback_substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static int snd_als300_capture_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct snd_als300 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct snd_als300_substream_data *data = kzalloc(sizeof(*data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) chip->capture_substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) runtime->hw = snd_als300_capture_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) runtime->private_data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) data->control_register = RECORD_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) data->block_counter_register = RECORD_BLOCK_COUNTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static int snd_als300_capture_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct snd_als300 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct snd_als300_substream_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) data = substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) kfree(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) chip->capture_substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static int snd_als300_playback_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct snd_als300 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) unsigned short period_bytes = snd_pcm_lib_period_bytes(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) unsigned short buffer_bytes = snd_pcm_lib_buffer_bytes(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) tmp = snd_als300_gcr_read(chip->port, PLAYBACK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) tmp &= ~TRANSFER_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) snd_als300_dbgplay("Period bytes: %d Buffer bytes %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) period_bytes, buffer_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* set block size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) tmp &= 0xffff0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) tmp |= period_bytes - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) snd_als300_gcr_write(chip->port, PLAYBACK_CONTROL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* set dma area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) snd_als300_gcr_write(chip->port, PLAYBACK_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) runtime->dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) snd_als300_gcr_write(chip->port, PLAYBACK_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) runtime->dma_addr + buffer_bytes - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static int snd_als300_capture_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct snd_als300 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) unsigned short period_bytes = snd_pcm_lib_period_bytes(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) unsigned short buffer_bytes = snd_pcm_lib_buffer_bytes(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) spin_lock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) tmp = snd_als300_gcr_read(chip->port, RECORD_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) tmp &= ~TRANSFER_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) snd_als300_dbgplay("Period bytes: %d Buffer bytes %d\n", period_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) buffer_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* set block size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) tmp &= 0xffff0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) tmp |= period_bytes - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* set dma area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) snd_als300_gcr_write(chip->port, RECORD_CONTROL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) snd_als300_gcr_write(chip->port, RECORD_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) runtime->dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) snd_als300_gcr_write(chip->port, RECORD_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) runtime->dma_addr + buffer_bytes - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) spin_unlock_irq(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static int snd_als300_trigger(struct snd_pcm_substream *substream, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct snd_als300 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct snd_als300_substream_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) unsigned short reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) data = substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) reg = data->control_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) spin_lock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) tmp = snd_als300_gcr_read(chip->port, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) data->period_flipflop = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) snd_als300_gcr_write(chip->port, reg, tmp | TRANSFER_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) snd_als300_dbgplay("TRIGGER START\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) tmp = snd_als300_gcr_read(chip->port, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) snd_als300_gcr_write(chip->port, reg, tmp & ~TRANSFER_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) snd_als300_dbgplay("TRIGGER STOP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) tmp = snd_als300_gcr_read(chip->port, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) snd_als300_gcr_write(chip->port, reg, tmp | FIFO_PAUSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) snd_als300_dbgplay("TRIGGER PAUSE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) tmp = snd_als300_gcr_read(chip->port, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) snd_als300_gcr_write(chip->port, reg, tmp & ~FIFO_PAUSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) snd_als300_dbgplay("TRIGGER RELEASE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) snd_als300_dbgplay("TRIGGER INVALID\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) spin_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static snd_pcm_uframes_t snd_als300_pointer(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) u16 current_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct snd_als300 *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct snd_als300_substream_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) unsigned short period_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) data = substream->runtime->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) period_bytes = snd_pcm_lib_period_bytes(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) spin_lock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) current_ptr = (u16) snd_als300_gcr_read(chip->port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) data->block_counter_register) + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) spin_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (current_ptr > period_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) current_ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) current_ptr = period_bytes - current_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (data->period_flipflop == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) current_ptr += period_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) snd_als300_dbgplay("Pointer (bytes): %d\n", current_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return bytes_to_frames(substream->runtime, current_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static const struct snd_pcm_ops snd_als300_playback_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .open = snd_als300_playback_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .close = snd_als300_playback_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .prepare = snd_als300_playback_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .trigger = snd_als300_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .pointer = snd_als300_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static const struct snd_pcm_ops snd_als300_capture_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .open = snd_als300_capture_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .close = snd_als300_capture_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .prepare = snd_als300_capture_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .trigger = snd_als300_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .pointer = snd_als300_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static int snd_als300_new_pcm(struct snd_als300 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) err = snd_pcm_new(chip->card, "ALS300", 0, 1, 1, &pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) pcm->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) strcpy(pcm->name, "ALS300");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) chip->pcm = pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* set operators */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) &snd_als300_playback_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) &snd_als300_capture_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /* pre-allocation of buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 64*1024, 64*1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static void snd_als300_init(struct snd_als300 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) chip->revision = (snd_als300_gcr_read(chip->port, MISC_CONTROL) >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) & 0x0000000F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* Setup DRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) tmp = snd_als300_gcr_read(chip->port, DRAM_WRITE_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) snd_als300_gcr_write(chip->port, DRAM_WRITE_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) (tmp | DRAM_MODE_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) & ~WRITE_TRANS_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /* Enable IRQ output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) snd_als300_set_irq_flag(chip, IRQ_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /* Unmute hardware devices so their outputs get routed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * the onboard mixer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) tmp = snd_als300_gcr_read(chip->port, MISC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) snd_als300_gcr_write(chip->port, MISC_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) tmp | VMUTE_NORMAL | MMUTE_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /* Reset volumes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) snd_als300_gcr_write(chip->port, MUS_VOC_VOL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /* Make sure playback transfer is stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) tmp = snd_als300_gcr_read(chip->port, PLAYBACK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) snd_als300_gcr_write(chip->port, PLAYBACK_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) tmp & ~TRANSFER_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static int snd_als300_create(struct snd_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct pci_dev *pci, int chip_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) struct snd_als300 **rchip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) struct snd_als300 *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) void *irq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static const struct snd_device_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .dev_free = snd_als300_dev_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) *rchip = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if ((err = pci_enable_device(pci)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (dma_set_mask(&pci->dev, DMA_BIT_MASK(28)) < 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(28)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) dev_err(card->dev, "error setting 28bit DMA mask\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) pci_set_master(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) chip = kzalloc(sizeof(*chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (chip == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) chip->card = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) chip->pci = pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) chip->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) chip->chip_type = chip_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) spin_lock_init(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if ((err = pci_request_regions(pci, "ALS300")) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) kfree(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) chip->port = pci_resource_start(pci, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (chip->chip_type == DEVICE_ALS300_PLUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) irq_handler = snd_als300plus_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) irq_handler = snd_als300_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (request_irq(pci->irq, irq_handler, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) KBUILD_MODNAME, chip)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) snd_als300_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) chip->irq = pci->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) card->sync_irq = chip->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) snd_als300_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) err = snd_als300_ac97(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) dev_err(card->dev, "Could not create ac97\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) snd_als300_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if ((err = snd_als300_new_pcm(chip)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) dev_err(card->dev, "Could not create PCM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) snd_als300_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) chip, &ops)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) snd_als300_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) *rchip = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) static int snd_als300_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) struct snd_als300 *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) snd_ac97_suspend(chip->ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static int snd_als300_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct snd_card *card = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) struct snd_als300 *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) snd_als300_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) snd_ac97_resume(chip->ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) snd_power_change_state(card, SNDRV_CTL_POWER_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static SIMPLE_DEV_PM_OPS(snd_als300_pm, snd_als300_suspend, snd_als300_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define SND_ALS300_PM_OPS &snd_als300_pm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define SND_ALS300_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) static int snd_als300_probe(struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) const struct pci_device_id *pci_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) static int dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) struct snd_als300 *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) int err, chip_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (dev >= SNDRV_CARDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (!enable[dev]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) dev++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) 0, &card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) chip_type = pci_id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if ((err = snd_als300_create(card, pci, chip_type, &chip)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) card->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) strcpy(card->driver, "ALS300");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (chip->chip_type == DEVICE_ALS300_PLUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /* don't know much about ALS300+ yet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) * print revision number for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) sprintf(card->shortname, "ALS300+ (Rev. %d)", chip->revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) sprintf(card->shortname, "ALS300 (Rev. %c)", 'A' +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) chip->revision - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) sprintf(card->longname, "%s at 0x%lx irq %i",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) card->shortname, chip->port, chip->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if ((err = snd_card_register(card)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) pci_set_drvdata(pci, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) dev++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static struct pci_driver als300_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .id_table = snd_als300_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .probe = snd_als300_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .remove = snd_als300_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .pm = SND_ALS300_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) module_pci_driver(als300_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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