Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /* Analog Devices 1889 audio driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2004, Kyle McMartin <kyle@parisc-linux.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #ifndef __AD1889_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #define __AD1889_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define AD_DS_WSMC	0x00 /* wave/synthesis channel mixer control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define  AD_DS_WSMC_SYEN 0x0004 /* synthesis channel enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define  AD_DS_WSMC_SYRQ 0x0030 /* synth. fifo request point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define  AD_DS_WSMC_WA16 0x0100 /* wave channel 16bit select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define  AD_DS_WSMC_WAST 0x0200 /* wave channel stereo select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define  AD_DS_WSMC_WAEN 0x0400 /* wave channel enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define  AD_DS_WSMC_WARQ 0x3000 /* wave fifo request point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define AD_DS_RAMC	0x02 /* resampler/ADC channel mixer control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define  AD_DS_RAMC_AD16 0x0001 /* ADC channel 16bit select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define  AD_DS_RAMC_ADST 0x0002 /* ADC channel stereo select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define  AD_DS_RAMC_ADEN 0x0004 /* ADC channel enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define  AD_DS_RAMC_ACRQ 0x0030 /* ADC fifo request point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define  AD_DS_RAMC_REEN 0x0400 /* resampler channel enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define  AD_DS_RAMC_RERQ 0x3000 /* res. fifo request point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define AD_DS_WADA	0x04 /* wave channel mix attenuation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define  AD_DS_WADA_RWAM 0x0080 /* right wave mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define  AD_DS_WADA_RWAA 0x001f /* right wave attenuation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define  AD_DS_WADA_LWAM 0x8000 /* left wave mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define  AD_DS_WADA_LWAA 0x3e00 /* left wave attenuation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define AD_DS_SYDA	0x06 /* synthesis channel mix attenuation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define  AD_DS_SYDA_RSYM 0x0080 /* right synthesis mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define  AD_DS_SYDA_RSYA 0x001f /* right synthesis attenuation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define  AD_DS_SYDA_LSYM 0x8000 /* left synthesis mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define  AD_DS_SYDA_LSYA 0x3e00 /* left synthesis attenuation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define AD_DS_WAS	0x08 /* wave channel sample rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define  AD_DS_WAS_WAS   0xffff /* sample rate mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define AD_DS_RES	0x0a /* resampler channel sample rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define  AD_DS_RES_RES   0xffff /* sample rate mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define AD_DS_CCS	0x0c /* chip control/status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define  AD_DS_CCS_ADO   0x0001 /* ADC channel overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define  AD_DS_CCS_REO   0x0002 /* resampler channel overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define  AD_DS_CCS_SYU   0x0004 /* synthesis channel underflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define  AD_DS_CCS_WAU   0x0008 /* wave channel underflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) /* bits 4 -> 7, 9, 11 -> 14 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define  AD_DS_CCS_XTD   0x0100 /* xtd delay control (4096 clock cycles) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define  AD_DS_CCS_PDALL 0x0400 /* power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define  AD_DS_CCS_CLKEN 0x8000 /* clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define AD_DMA_RESBA	0x40 /* RES base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define AD_DMA_RESCA	0x44 /* RES current address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define AD_DMA_RESBC	0x48 /* RES base count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define AD_DMA_RESCC	0x4c /* RES current count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define AD_DMA_ADCBA	0x50 /* ADC base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define AD_DMA_ADCCA	0x54 /* ADC current address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define AD_DMA_ADCBC	0x58 /* ADC base count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define AD_DMA_ADCCC	0x5c /* ADC current count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define AD_DMA_SYNBA	0x60 /* synth base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define AD_DMA_SYNCA	0x64 /* synth current address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define AD_DMA_SYNBC	0x68 /* synth base count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define AD_DMA_SYNCC	0x6c /* synth current count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define AD_DMA_WAVBA	0x70 /* wave base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define AD_DMA_WAVCA	0x74 /* wave current address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define AD_DMA_WAVBC	0x78 /* wave base count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define AD_DMA_WAVCC	0x7c /* wave current count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define AD_DMA_RESIC	0x80 /* RES dma interrupt current byte count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define AD_DMA_RESIB	0x84 /* RES dma interrupt base byte count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define AD_DMA_ADCIC	0x88 /* ADC dma interrupt current byte count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define AD_DMA_ADCIB	0x8c /* ADC dma interrupt base byte count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define AD_DMA_SYNIC	0x90 /* synth dma interrupt current byte count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define AD_DMA_SYNIB	0x94 /* synth dma interrupt base byte count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define AD_DMA_WAVIC	0x98 /* wave dma interrupt current byte count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define AD_DMA_WAVIB	0x9c /* wave dma interrupt base byte count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define  AD_DMA_ICC	0xffffff /* current byte count mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define  AD_DMA_IBC	0xffffff /* base byte count mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) /* bits 24 -> 31 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) /* 4 bytes pad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define AD_DMA_ADC	0xa8	/* ADC      dma control and status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define AD_DMA_SYNTH	0xb0	/* Synth    dma control and status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define AD_DMA_WAV	0xb8	/* wave     dma control and status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define AD_DMA_RES	0xa0	/* Resample dma control and status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define  AD_DMA_SGDE	0x0001 /* SGD mode enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define  AD_DMA_LOOP	0x0002 /* loop enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define  AD_DMA_IM	0x000c /* interrupt mode mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define  AD_DMA_IM_DIS	(~AD_DMA_IM)	/* disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define  AD_DMA_IM_CNT	0x0004 /* interrupt on count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define  AD_DMA_IM_SGD	0x0008 /* interrupt on SGD flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define  AD_DMA_IM_EOL	0x000c /* interrupt on End of Linked List */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define  AD_DMA_SGDS	0x0030 /* SGD status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define  AD_DMA_SFLG	0x0040 /* SGD flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define  AD_DMA_EOL	0x0080 /* SGD end of list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* bits 8 -> 15 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define AD_DMA_DISR	0xc0 /* dma interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define  AD_DMA_DISR_RESI 0x000001 /* resampler channel interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define  AD_DMA_DISR_ADCI 0x000002 /* ADC channel interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define  AD_DMA_DISR_SYNI 0x000004 /* synthesis channel interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define  AD_DMA_DISR_WAVI 0x000008 /* wave channel interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* bits 4, 5 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define  AD_DMA_DISR_SEPS 0x000040 /* serial eeprom status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* bits 7 -> 13 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define  AD_DMA_DISR_PMAI 0x004000 /* pci master abort interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define  AD_DMA_DISR_PTAI 0x008000 /* pci target abort interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define  AD_DMA_DISR_PTAE 0x010000 /* pci target abort interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define  AD_DMA_DISR_PMAE 0x020000 /* pci master abort interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* bits 19 -> 31 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* interrupt mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define  AD_INTR_MASK     (AD_DMA_DISR_RESI|AD_DMA_DISR_ADCI| \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)                            AD_DMA_DISR_WAVI|AD_DMA_DISR_SYNI| \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)                            AD_DMA_DISR_PMAI|AD_DMA_DISR_PTAI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define AD_DMA_CHSS	0xc4 /* dma channel stop status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define  AD_DMA_CHSS_RESS 0x000001 /* resampler channel stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define  AD_DMA_CHSS_ADCS 0x000002 /* ADC channel stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define  AD_DMA_CHSS_SYNS 0x000004 /* synthesis channel stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define  AD_DMA_CHSS_WAVS 0x000008 /* wave channel stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define AD_GPIO_IPC	0xc8	/* gpio port control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define AD_GPIO_OP	0xca	/* gpio output port status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define AD_GPIO_IP	0xcc	/* gpio  input port status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define AD_AC97_BASE	0x100	/* ac97 base register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define AD_AC97_RESET   0x100   /* reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define AD_AC97_PWR_CTL	0x126	/* == AC97_POWERDOWN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define  AD_AC97_PWR_ADC 0x0001 /* ADC ready status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define  AD_AC97_PWR_DAC 0x0002 /* DAC ready status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define  AD_AC97_PWR_PR0 0x0100 /* PR0 (ADC) powerdown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define  AD_AC97_PWR_PR1 0x0200 /* PR1 (DAC) powerdown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define AD_MISC_CTL     0x176 /* misc control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define  AD_MISC_CTL_DACZ   0x8000 /* set for zero fill, unset for repeat */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define  AD_MISC_CTL_ARSR   0x0001 /* set for SR1, unset for SR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define  AD_MISC_CTL_ALSR   0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define  AD_MISC_CTL_DLSR   0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define  AD_MISC_CTL_DRSR   0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define AD_AC97_SR0     0x178 /* sample rate 0, 0xbb80 == 48K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define  AD_AC97_SR0_48K 0xbb80 /* 48KHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define AD_AC97_SR1     0x17a /* sample rate 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define AD_AC97_ACIC	0x180 /* ac97 codec interface control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define  AD_AC97_ACIC_ACIE  0x0001 /* analog codec interface enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define  AD_AC97_ACIC_ACRD  0x0002 /* analog codec reset disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define  AD_AC97_ACIC_ASOE  0x0004 /* audio stream output enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define  AD_AC97_ACIC_VSRM  0x0008 /* variable sample rate mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define  AD_AC97_ACIC_FSDH  0x0100 /* force SDATA_OUT high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define  AD_AC97_ACIC_FSYH  0x0200 /* force sync high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define  AD_AC97_ACIC_ACRDY 0x8000 /* analog codec ready status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* bits 10 -> 14 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define AD_DS_MEMSIZE	512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define AD_OPL_MEMSIZE	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define AD_MIDI_MEMSIZE	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define AD_WAV_STATE	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define AD_ADC_STATE	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define AD_MAX_STATES	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define AD_CHAN_WAV	0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define AD_CHAN_ADC	0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define AD_CHAN_RES	0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define AD_CHAN_SYN	0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* The chip would support 4 GB buffers and 16 MB periods,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)  * but let's not overdo it ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define BUFFER_BYTES_MAX	(256 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define PERIOD_BYTES_MIN	32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define PERIOD_BYTES_MAX	(BUFFER_BYTES_MAX / 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define PERIODS_MIN		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define PERIODS_MAX		(BUFFER_BYTES_MAX / PERIOD_BYTES_MIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #endif /* __AD1889_H__ */