^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Analog Devices 1889 audio driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This is a driver for the AD1889 PCI audio chipset found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * on the HP PA-RISC [BCJ]-xxx0 workstations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2004-2005, Kyle McMartin <kyle@parisc-linux.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2005, Thibaut Varene <varenet@parisc-linux.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Based on the OSS AD1889 driver by Randolph Chung <tausq@debian.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * TODO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Do we need to take care of CCS register?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Maybe we could use finer grained locking (separate locks for pb/cap)?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Wishlist:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Control Interface (mixer) support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Better AC97 support (VSR...)?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * PM support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * MIDI support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Game Port support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * SG DMA support (this will need *a lot* of work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/compiler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <sound/ac97_codec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include "ad1889.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include "ac97/ac97_id.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AD1889_DRVVER "Version: 1.7"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MODULE_AUTHOR("Kyle McMartin <kyle@parisc-linux.org>, Thibaut Varene <t-bone@parisc-linux.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) MODULE_DESCRIPTION("Analog Devices AD1889 ALSA sound driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MODULE_SUPPORTED_DEVICE("{{Analog Devices,AD1889}}");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) module_param_array(index, int, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) MODULE_PARM_DESC(index, "Index value for the AD1889 soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) module_param_array(id, charp, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MODULE_PARM_DESC(id, "ID string for the AD1889 soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) module_param_array(enable, bool, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MODULE_PARM_DESC(enable, "Enable AD1889 soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static char *ac97_quirk[SNDRV_CARDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) module_param_array(ac97_quirk, charp, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DEVNAME "ad1889"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PFX DEVNAME ": "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* keep track of some hw registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct ad1889_register_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u16 reg; /* reg setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 addr; /* dma base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned long size; /* DMA buffer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct snd_ad1889 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct pci_dev *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned long bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) void __iomem *iobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct snd_ac97 *ac97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct snd_ac97_bus *ac97_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct snd_info_entry *proc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct snd_pcm_substream *psubs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct snd_pcm_substream *csubs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* playback register state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct ad1889_register_state wave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct ad1889_register_state ramc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static inline u16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ad1889_readw(struct snd_ad1889 *chip, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return readw(chip->iobase + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ad1889_writew(struct snd_ad1889 *chip, unsigned reg, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) writew(val, chip->iobase + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static inline u32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ad1889_readl(struct snd_ad1889 *chip, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return readl(chip->iobase + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ad1889_writel(struct snd_ad1889 *chip, unsigned reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) writel(val, chip->iobase + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ad1889_unmute(struct snd_ad1889 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u16 st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) st = ad1889_readw(chip, AD_DS_WADA) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ~(AD_DS_WADA_RWAM | AD_DS_WADA_LWAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ad1889_writew(chip, AD_DS_WADA, st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ad1889_readw(chip, AD_DS_WADA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ad1889_mute(struct snd_ad1889 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u16 st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) st = ad1889_readw(chip, AD_DS_WADA) | AD_DS_WADA_RWAM | AD_DS_WADA_LWAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ad1889_writew(chip, AD_DS_WADA, st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ad1889_readw(chip, AD_DS_WADA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) ad1889_load_adc_buffer_address(struct snd_ad1889 *chip, u32 address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ad1889_writel(chip, AD_DMA_ADCBA, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) ad1889_writel(chip, AD_DMA_ADCCA, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ad1889_load_adc_buffer_count(struct snd_ad1889 *chip, u32 count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ad1889_writel(chip, AD_DMA_ADCBC, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ad1889_writel(chip, AD_DMA_ADCCC, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ad1889_load_adc_interrupt_count(struct snd_ad1889 *chip, u32 count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ad1889_writel(chip, AD_DMA_ADCIB, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ad1889_writel(chip, AD_DMA_ADCIC, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ad1889_load_wave_buffer_address(struct snd_ad1889 *chip, u32 address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ad1889_writel(chip, AD_DMA_WAVBA, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ad1889_writel(chip, AD_DMA_WAVCA, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ad1889_load_wave_buffer_count(struct snd_ad1889 *chip, u32 count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ad1889_writel(chip, AD_DMA_WAVBC, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ad1889_writel(chip, AD_DMA_WAVCC, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ad1889_load_wave_interrupt_count(struct snd_ad1889 *chip, u32 count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ad1889_writel(chip, AD_DMA_WAVIB, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ad1889_writel(chip, AD_DMA_WAVIC, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ad1889_channel_reset(struct snd_ad1889 *chip, unsigned int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (channel & AD_CHAN_WAV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* Disable wave channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) reg = ad1889_readw(chip, AD_DS_WSMC) & ~AD_DS_WSMC_WAEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ad1889_writew(chip, AD_DS_WSMC, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) chip->wave.reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* disable IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) reg = ad1889_readw(chip, AD_DMA_WAV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) reg &= AD_DMA_IM_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) reg &= ~AD_DMA_LOOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ad1889_writew(chip, AD_DMA_WAV, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* clear IRQ and address counters and pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ad1889_load_wave_buffer_address(chip, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ad1889_load_wave_buffer_count(chip, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ad1889_load_wave_interrupt_count(chip, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ad1889_readw(chip, AD_DMA_WAV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (channel & AD_CHAN_ADC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Disable ADC channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) reg = ad1889_readw(chip, AD_DS_RAMC) & ~AD_DS_RAMC_ADEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ad1889_writew(chip, AD_DS_RAMC, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) chip->ramc.reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) reg = ad1889_readw(chip, AD_DMA_ADC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) reg &= AD_DMA_IM_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) reg &= ~AD_DMA_LOOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) ad1889_writew(chip, AD_DMA_ADC, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ad1889_load_adc_buffer_address(chip, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ad1889_load_adc_buffer_count(chip, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ad1889_load_adc_interrupt_count(chip, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ad1889_readw(chip, AD_DMA_ADC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static u16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) snd_ad1889_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct snd_ad1889 *chip = ac97->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return ad1889_readw(chip, AD_AC97_BASE + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) snd_ad1889_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct snd_ad1889 *chip = ac97->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ad1889_writew(chip, AD_AC97_BASE + reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) snd_ad1889_ac97_ready(struct snd_ad1889 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) int retry = 400; /* average needs 352 msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) while (!(ad1889_readw(chip, AD_AC97_ACIC) & AD_AC97_ACIC_ACRDY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) && --retry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (!retry) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) dev_err(chip->card->dev, "[%s] Link is not ready.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) dev_dbg(chip->card->dev, "[%s] ready after %d ms\n", __func__, 400 - retry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static const struct snd_pcm_hardware snd_ad1889_playback_hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BLOCK_TRANSFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .rate_min = 8000, /* docs say 7000, but we're lazy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .buffer_bytes_max = BUFFER_BYTES_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .period_bytes_min = PERIOD_BYTES_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .period_bytes_max = PERIOD_BYTES_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .periods_min = PERIODS_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .periods_max = PERIODS_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /*.fifo_size = 0,*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static const struct snd_pcm_hardware snd_ad1889_capture_hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .info = SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BLOCK_TRANSFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .formats = SNDRV_PCM_FMTBIT_S16_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .rates = SNDRV_PCM_RATE_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .rate_min = 48000, /* docs say we could to VSR, but we're lazy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .buffer_bytes_max = BUFFER_BYTES_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .period_bytes_min = PERIOD_BYTES_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .period_bytes_max = PERIOD_BYTES_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .periods_min = PERIODS_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .periods_max = PERIODS_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /*.fifo_size = 0,*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) snd_ad1889_playback_open(struct snd_pcm_substream *ss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct snd_pcm_runtime *rt = ss->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) chip->psubs = ss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) rt->hw = snd_ad1889_playback_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) snd_ad1889_capture_open(struct snd_pcm_substream *ss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct snd_pcm_runtime *rt = ss->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) chip->csubs = ss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) rt->hw = snd_ad1889_capture_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) snd_ad1889_playback_close(struct snd_pcm_substream *ss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) chip->psubs = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) snd_ad1889_capture_close(struct snd_pcm_substream *ss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) chip->csubs = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) snd_ad1889_playback_prepare(struct snd_pcm_substream *ss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct snd_pcm_runtime *rt = ss->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) unsigned int size = snd_pcm_lib_buffer_bytes(ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) unsigned int count = snd_pcm_lib_period_bytes(ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ad1889_channel_reset(chip, AD_CHAN_WAV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) reg = ad1889_readw(chip, AD_DS_WSMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* Mask out 16-bit / Stereo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) reg &= ~(AD_DS_WSMC_WA16 | AD_DS_WSMC_WAST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (snd_pcm_format_width(rt->format) == 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) reg |= AD_DS_WSMC_WA16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (rt->channels > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) reg |= AD_DS_WSMC_WAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* let's make sure we don't clobber ourselves */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) spin_lock_irq(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) chip->wave.size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) chip->wave.reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) chip->wave.addr = rt->dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ad1889_writew(chip, AD_DS_WSMC, chip->wave.reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* Set sample rates on the codec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ad1889_writew(chip, AD_DS_WAS, rt->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* Set up DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ad1889_load_wave_buffer_address(chip, chip->wave.addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ad1889_load_wave_buffer_count(chip, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ad1889_load_wave_interrupt_count(chip, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* writes flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ad1889_readw(chip, AD_DS_WSMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) spin_unlock_irq(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) "prepare playback: addr = 0x%x, count = %u, size = %u, reg = 0x%x, rate = %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) chip->wave.addr, count, size, reg, rt->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) snd_ad1889_capture_prepare(struct snd_pcm_substream *ss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct snd_pcm_runtime *rt = ss->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) unsigned int size = snd_pcm_lib_buffer_bytes(ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) unsigned int count = snd_pcm_lib_period_bytes(ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) ad1889_channel_reset(chip, AD_CHAN_ADC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) reg = ad1889_readw(chip, AD_DS_RAMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* Mask out 16-bit / Stereo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) reg &= ~(AD_DS_RAMC_AD16 | AD_DS_RAMC_ADST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (snd_pcm_format_width(rt->format) == 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) reg |= AD_DS_RAMC_AD16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (rt->channels > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) reg |= AD_DS_RAMC_ADST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* let's make sure we don't clobber ourselves */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) spin_lock_irq(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) chip->ramc.size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) chip->ramc.reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) chip->ramc.addr = rt->dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) ad1889_writew(chip, AD_DS_RAMC, chip->ramc.reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* Set up DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ad1889_load_adc_buffer_address(chip, chip->ramc.addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) ad1889_load_adc_buffer_count(chip, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ad1889_load_adc_interrupt_count(chip, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* writes flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) ad1889_readw(chip, AD_DS_RAMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) spin_unlock_irq(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) "prepare capture: addr = 0x%x, count = %u, size = %u, reg = 0x%x, rate = %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) chip->ramc.addr, count, size, reg, rt->rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* this is called in atomic context with IRQ disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) Must be as fast as possible and not sleep.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) DMA should be *triggered* by this call.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) The WSMC "WAEN" bit triggers DMA Wave On/Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) snd_ad1889_playback_trigger(struct snd_pcm_substream *ss, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) u16 wsmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) wsmc = ad1889_readw(chip, AD_DS_WSMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* enable DMA loop & interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) ad1889_writew(chip, AD_DMA_WAV, AD_DMA_LOOP | AD_DMA_IM_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) wsmc |= AD_DS_WSMC_WAEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* 1 to clear CHSS bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) ad1889_writel(chip, AD_DMA_CHSS, AD_DMA_CHSS_WAVS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ad1889_unmute(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ad1889_mute(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) wsmc &= ~AD_DS_WSMC_WAEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) snd_BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) chip->wave.reg = wsmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ad1889_writew(chip, AD_DS_WSMC, wsmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) ad1889_readw(chip, AD_DS_WSMC); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* reset the chip when STOP - will disable IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (cmd == SNDRV_PCM_TRIGGER_STOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) ad1889_channel_reset(chip, AD_CHAN_WAV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* this is called in atomic context with IRQ disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) Must be as fast as possible and not sleep.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) DMA should be *triggered* by this call.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) The RAMC "ADEN" bit triggers DMA ADC On/Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) snd_ad1889_capture_trigger(struct snd_pcm_substream *ss, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) u16 ramc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) ramc = ad1889_readw(chip, AD_DS_RAMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* enable DMA loop & interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) ad1889_writew(chip, AD_DMA_ADC, AD_DMA_LOOP | AD_DMA_IM_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ramc |= AD_DS_RAMC_ADEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* 1 to clear CHSS bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) ad1889_writel(chip, AD_DMA_CHSS, AD_DMA_CHSS_ADCS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) ramc &= ~AD_DS_RAMC_ADEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) chip->ramc.reg = ramc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) ad1889_writew(chip, AD_DS_RAMC, ramc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) ad1889_readw(chip, AD_DS_RAMC); /* flush */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* reset the chip when STOP - will disable IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (cmd == SNDRV_PCM_TRIGGER_STOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ad1889_channel_reset(chip, AD_CHAN_ADC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* Called in atomic context with IRQ disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static snd_pcm_uframes_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) snd_ad1889_playback_pointer(struct snd_pcm_substream *ss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) size_t ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (unlikely(!(chip->wave.reg & AD_DS_WSMC_WAEN)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) ptr = ad1889_readl(chip, AD_DMA_WAVCA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) ptr -= chip->wave.addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (snd_BUG_ON(ptr >= chip->wave.size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return bytes_to_frames(ss->runtime, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* Called in atomic context with IRQ disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static snd_pcm_uframes_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) snd_ad1889_capture_pointer(struct snd_pcm_substream *ss)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) size_t ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct snd_ad1889 *chip = snd_pcm_substream_chip(ss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (unlikely(!(chip->ramc.reg & AD_DS_RAMC_ADEN)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ptr = ad1889_readl(chip, AD_DMA_ADCCA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) ptr -= chip->ramc.addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (snd_BUG_ON(ptr >= chip->ramc.size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return bytes_to_frames(ss->runtime, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static const struct snd_pcm_ops snd_ad1889_playback_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .open = snd_ad1889_playback_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .close = snd_ad1889_playback_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .prepare = snd_ad1889_playback_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .trigger = snd_ad1889_playback_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .pointer = snd_ad1889_playback_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static const struct snd_pcm_ops snd_ad1889_capture_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .open = snd_ad1889_capture_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .close = snd_ad1889_capture_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .prepare = snd_ad1889_capture_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .trigger = snd_ad1889_capture_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .pointer = snd_ad1889_capture_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) snd_ad1889_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) unsigned long st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) struct snd_ad1889 *chip = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) st = ad1889_readl(chip, AD_DMA_DISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /* clear ISR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) ad1889_writel(chip, AD_DMA_DISR, st);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) st &= AD_INTR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (unlikely(!st))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (st & (AD_DMA_DISR_PMAI|AD_DMA_DISR_PTAI))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) dev_dbg(chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) "Unexpected master or target abort interrupt!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if ((st & AD_DMA_DISR_WAVI) && chip->psubs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) snd_pcm_period_elapsed(chip->psubs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if ((st & AD_DMA_DISR_ADCI) && chip->csubs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) snd_pcm_period_elapsed(chip->csubs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) snd_ad1889_pcm_init(struct snd_ad1889 *chip, int device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) err = snd_pcm_new(chip->card, chip->card->driver, device, 1, 1, &pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) &snd_ad1889_playback_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) &snd_ad1889_capture_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) pcm->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) pcm->info_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) strcpy(pcm->name, chip->card->shortname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) chip->pcm = pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) chip->psubs = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) chip->csubs = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, &chip->pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) BUFFER_BYTES_MAX / 2, BUFFER_BYTES_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) snd_ad1889_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct snd_ad1889 *chip = entry->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) reg = ad1889_readw(chip, AD_DS_WSMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) snd_iprintf(buffer, "Wave output: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) (reg & AD_DS_WSMC_WAEN) ? "enabled" : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) snd_iprintf(buffer, "Wave Channels: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) (reg & AD_DS_WSMC_WAST) ? "stereo" : "mono");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) snd_iprintf(buffer, "Wave Quality: %d-bit linear\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) (reg & AD_DS_WSMC_WA16) ? 16 : 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) /* WARQ is at offset 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) tmp = (reg & AD_DS_WSMC_WARQ) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) ((((reg & AD_DS_WSMC_WARQ) >> 12) & 0x01) ? 12 : 18) : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) tmp /= (reg & AD_DS_WSMC_WAST) ? 2 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) snd_iprintf(buffer, "Wave FIFO: %d %s words\n\n", tmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) (reg & AD_DS_WSMC_WAST) ? "stereo" : "mono");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) snd_iprintf(buffer, "Synthesis output: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) reg & AD_DS_WSMC_SYEN ? "enabled" : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /* SYRQ is at offset 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) tmp = (reg & AD_DS_WSMC_SYRQ) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) ((((reg & AD_DS_WSMC_SYRQ) >> 4) & 0x01) ? 12 : 18) : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) tmp /= (reg & AD_DS_WSMC_WAST) ? 2 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) snd_iprintf(buffer, "Synthesis FIFO: %d %s words\n\n", tmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) (reg & AD_DS_WSMC_WAST) ? "stereo" : "mono");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) reg = ad1889_readw(chip, AD_DS_RAMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) snd_iprintf(buffer, "ADC input: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) (reg & AD_DS_RAMC_ADEN) ? "enabled" : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) snd_iprintf(buffer, "ADC Channels: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) (reg & AD_DS_RAMC_ADST) ? "stereo" : "mono");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) snd_iprintf(buffer, "ADC Quality: %d-bit linear\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) (reg & AD_DS_RAMC_AD16) ? 16 : 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /* ACRQ is at offset 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) tmp = (reg & AD_DS_RAMC_ACRQ) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) ((((reg & AD_DS_RAMC_ACRQ) >> 4) & 0x01) ? 12 : 18) : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) tmp /= (reg & AD_DS_RAMC_ADST) ? 2 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) snd_iprintf(buffer, "ADC FIFO: %d %s words\n\n", tmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) (reg & AD_DS_RAMC_ADST) ? "stereo" : "mono");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) snd_iprintf(buffer, "Resampler input: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) reg & AD_DS_RAMC_REEN ? "enabled" : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /* RERQ is at offset 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) tmp = (reg & AD_DS_RAMC_RERQ) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) ((((reg & AD_DS_RAMC_RERQ) >> 12) & 0x01) ? 12 : 18) : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) tmp /= (reg & AD_DS_RAMC_ADST) ? 2 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) snd_iprintf(buffer, "Resampler FIFO: %d %s words\n\n", tmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) (reg & AD_DS_WSMC_WAST) ? "stereo" : "mono");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* doc says LSB represents -1.5dB, but the max value (-94.5dB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) suggests that LSB is -3dB, which is more coherent with the logarithmic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) nature of the dB scale */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) reg = ad1889_readw(chip, AD_DS_WADA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) snd_iprintf(buffer, "Left: %s, -%d dB\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) (reg & AD_DS_WADA_LWAM) ? "mute" : "unmute",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) ((reg & AD_DS_WADA_LWAA) >> 8) * 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) reg = ad1889_readw(chip, AD_DS_WADA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) snd_iprintf(buffer, "Right: %s, -%d dB\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) (reg & AD_DS_WADA_RWAM) ? "mute" : "unmute",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) (reg & AD_DS_WADA_RWAA) * 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) reg = ad1889_readw(chip, AD_DS_WAS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) snd_iprintf(buffer, "Wave samplerate: %u Hz\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) reg = ad1889_readw(chip, AD_DS_RES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) snd_iprintf(buffer, "Resampler samplerate: %u Hz\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) snd_ad1889_proc_init(struct snd_ad1889 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) snd_card_ro_proc_new(chip->card, chip->card->driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) chip, snd_ad1889_proc_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) static const struct ac97_quirk ac97_quirks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .subvendor = 0x11d4, /* AD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .subdevice = 0x1889, /* AD1889 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .codec_id = AC97_ID_AD1819,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .name = "AD1889",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .type = AC97_TUNE_HP_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) { } /* terminator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) snd_ad1889_ac97_xinit(struct snd_ad1889 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) reg = ad1889_readw(chip, AD_AC97_ACIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) reg |= AD_AC97_ACIC_ACRD; /* Reset Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) ad1889_writew(chip, AD_AC97_ACIC, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) ad1889_readw(chip, AD_AC97_ACIC); /* flush posted write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /* Interface Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) reg |= AD_AC97_ACIC_ACIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) ad1889_writew(chip, AD_AC97_ACIC, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) snd_ad1889_ac97_ready(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /* Audio Stream Output | Variable Sample Rate Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) reg = ad1889_readw(chip, AD_AC97_ACIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) reg |= AD_AC97_ACIC_ASOE | AD_AC97_ACIC_VSRM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) ad1889_writew(chip, AD_AC97_ACIC, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) ad1889_readw(chip, AD_AC97_ACIC); /* flush posted write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) snd_ad1889_ac97_bus_free(struct snd_ac97_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) struct snd_ad1889 *chip = bus->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) chip->ac97_bus = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) snd_ad1889_ac97_free(struct snd_ac97 *ac97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) struct snd_ad1889 *chip = ac97->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) chip->ac97 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) snd_ad1889_ac97_init(struct snd_ad1889 *chip, const char *quirk_override)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) struct snd_ac97_template ac97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static const struct snd_ac97_bus_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .write = snd_ad1889_ac97_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .read = snd_ad1889_ac97_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) /* doing that here, it works. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) snd_ad1889_ac97_xinit(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) err = snd_ac97_bus(chip->card, 0, &ops, chip, &chip->ac97_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) chip->ac97_bus->private_free = snd_ad1889_ac97_bus_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) memset(&ac97, 0, sizeof(ac97));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) ac97.private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) ac97.private_free = snd_ad1889_ac97_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) ac97.pci = chip->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) snd_ac97_tune_hardware(chip->ac97, ac97_quirks, quirk_override);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) snd_ad1889_free(struct snd_ad1889 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (chip->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) goto skip_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) spin_lock_irq(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) ad1889_mute(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) /* Turn off interrupt on count and zero DMA registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) ad1889_channel_reset(chip, AD_CHAN_WAV | AD_CHAN_ADC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) /* clear DISR. If we don't, we'd better jump off the Eiffel Tower */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) ad1889_writel(chip, AD_DMA_DISR, AD_DMA_DISR_PTAI | AD_DMA_DISR_PMAI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) ad1889_readl(chip, AD_DMA_DISR); /* flush, dammit! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) spin_unlock_irq(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (chip->irq >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) free_irq(chip->irq, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) skip_hw:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) iounmap(chip->iobase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) pci_release_regions(chip->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) pci_disable_device(chip->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) kfree(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) snd_ad1889_dev_free(struct snd_device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) struct snd_ad1889 *chip = device->device_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) return snd_ad1889_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) snd_ad1889_init(struct snd_ad1889 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) ad1889_writew(chip, AD_DS_CCS, AD_DS_CCS_CLKEN); /* turn on clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) ad1889_readw(chip, AD_DS_CCS); /* flush posted write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) usleep_range(10000, 11000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) /* enable Master and Target abort interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) ad1889_writel(chip, AD_DMA_DISR, AD_DMA_DISR_PMAE | AD_DMA_DISR_PTAE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) snd_ad1889_create(struct snd_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) struct snd_ad1889 **rchip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) struct snd_ad1889 *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) static const struct snd_device_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .dev_free = snd_ad1889_dev_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) *rchip = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if ((err = pci_enable_device(pci)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) /* check PCI availability (32bit DMA) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (dma_set_mask(&pci->dev, DMA_BIT_MASK(32)) < 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) dev_err(card->dev, "error setting 32-bit DMA mask.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) /* allocate chip specific data with zero-filled memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if ((chip = kzalloc(sizeof(*chip), GFP_KERNEL)) == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) chip->card = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) card->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) chip->pci = pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) chip->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) /* (1) PCI resource allocation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if ((err = pci_request_regions(pci, card->driver)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) goto free_and_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) chip->bar = pci_resource_start(pci, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) chip->iobase = pci_ioremap_bar(pci, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) if (chip->iobase == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) dev_err(card->dev, "unable to reserve region.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) goto free_and_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) pci_set_master(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) spin_lock_init(&chip->lock); /* only now can we call ad1889_free */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (request_irq(pci->irq, snd_ad1889_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) IRQF_SHARED, KBUILD_MODNAME, chip)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) dev_err(card->dev, "cannot obtain IRQ %d\n", pci->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) snd_ad1889_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) chip->irq = pci->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) card->sync_irq = chip->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /* (2) initialization of the chip hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if ((err = snd_ad1889_init(chip)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) snd_ad1889_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) snd_ad1889_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) *rchip = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) free_and_ret:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) kfree(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) pci_disable_device(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) snd_ad1889_probe(struct pci_dev *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) const struct pci_device_id *pci_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) static int devno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) struct snd_ad1889 *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) /* (1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) if (devno >= SNDRV_CARDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) if (!enable[devno]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) devno++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) /* (2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) err = snd_card_new(&pci->dev, index[devno], id[devno], THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) 0, &card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) /* XXX REVISIT: we can probably allocate chip in this call */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) strcpy(card->driver, "AD1889");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) strcpy(card->shortname, "Analog Devices AD1889");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) /* (3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) err = snd_ad1889_create(card, pci, &chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) goto free_and_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) /* (4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) sprintf(card->longname, "%s at 0x%lx irq %i",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) card->shortname, chip->bar, chip->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) /* (5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) /* register AC97 mixer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) err = snd_ad1889_ac97_init(chip, ac97_quirk[devno]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) goto free_and_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) err = snd_ad1889_pcm_init(chip, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) goto free_and_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) /* register proc interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) snd_ad1889_proc_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /* (6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) err = snd_card_register(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) goto free_and_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) /* (7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) pci_set_drvdata(pci, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) devno++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) free_and_ret:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) snd_ad1889_remove(struct pci_dev *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) snd_card_free(pci_get_drvdata(pci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) static const struct pci_device_id snd_ad1889_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) { PCI_DEVICE(PCI_VENDOR_ID_ANALOG_DEVICES, PCI_DEVICE_ID_AD1889JS) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) { 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) MODULE_DEVICE_TABLE(pci, snd_ad1889_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) static struct pci_driver ad1889_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) .name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .id_table = snd_ad1889_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .probe = snd_ad1889_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) .remove = snd_ad1889_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) module_pci_driver(ad1889_pci_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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