Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #ifndef __HAL2_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #define __HAL2_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *  Driver for HAL2 sound processors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *  Copyright (c) 1999 Ulf Carlsson <ulfc@bun.falkenberg.se>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *  Copyright (c) 2001, 2002, 2003 Ladislav Michl <ladis@linux-mips.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) /* Indirect status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define H2_ISR_TSTATUS		0x01	/* RO: transaction status 1=busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define H2_ISR_USTATUS		0x02	/* RO: utime status bit 1=armed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define H2_ISR_QUAD_MODE	0x04	/* codec mode 0=indigo 1=quad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define H2_ISR_GLOBAL_RESET_N	0x08	/* chip global reset 0=reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define H2_ISR_CODEC_RESET_N	0x10	/* codec/synth reset 0=reset  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /* Revision register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define H2_REV_AUDIO_PRESENT	0x8000	/* RO: audio present 0=present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define H2_REV_BOARD_M		0x7000	/* RO: bits 14:12, board revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define H2_REV_MAJOR_CHIP_M	0x00F0	/* RO: bits 7:4, major chip revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define H2_REV_MINOR_CHIP_M	0x000F	/* RO: bits 3:0, minor chip revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /* Indirect address register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * Address of indirect internal register to be accessed. A write to this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * register initiates read or write access to the indirect registers in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * HAL2. Note that there af four indirect data registers for write access to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  * registers larger than 16 byte.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define H2_IAR_TYPE_M		0xF000	/* bits 15:12, type of functional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 					/* block the register resides in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 					/* 1=DMA Port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 					/* 9=Global DMA Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 					/* 2=Bresenham */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 					/* 3=Unix Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define H2_IAR_NUM_M		0x0F00	/* bits 11:8 instance of the */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 					/* blockin which the indirect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 					/* register resides */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 					/* If IAR_TYPE_M=DMA Port: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 					/* 1=Synth In */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 					/* 2=AES In */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 					/* 3=AES Out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 					/* 4=DAC Out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 					/* 5=ADC Out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 					/* 6=Synth Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 					/* If IAR_TYPE_M=Global DMA Control: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 					/* 1=Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 					/* If IAR_TYPE_M=Bresenham: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 					/* 1=Bresenham Clock Gen 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 					/* 2=Bresenham Clock Gen 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 					/* 3=Bresenham Clock Gen 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 					/* If IAR_TYPE_M=Unix Timer: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 					/* 1=Unix Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define H2_IAR_ACCESS_SELECT	0x0080	/* 1=read 0=write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define H2_IAR_PARAM		0x000C	/* Parameter Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define H2_IAR_RB_INDEX_M	0x0003	/* Read Back Index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 					/* 00:word0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 					/* 01:word1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 					/* 10:word2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 					/* 11:word3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  * HAL2 internal addressing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)  * The HAL2 has "indirect registers" (idr) which are accessed by writing to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72)  * Indirect Data registers. Write the address to the Indirect Address register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73)  * to transfer the data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)  * We define the H2IR_* to the read address and H2IW_* to the write address and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)  * H2I_* to be fields in whatever register is referred to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  * When we write to indirect registers which are larger than one word (16 bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  * we have to fill more than one indirect register before writing. When we read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)  * back however we have to read several times, each time with different Read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)  * Back Indexes (there are defs for doing this easily).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85)  * Relay Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define H2I_RELAY_C		0x9100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define H2I_RELAY_C_STATE	0x01		/* state of RELAY pin signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) /* DMA port enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define H2I_DMA_PORT_EN		0x9104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define H2I_DMA_PORT_EN_SY_IN	0x01		/* Synth_in DMA port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define H2I_DMA_PORT_EN_AESRX	0x02		/* AES receiver DMA port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define H2I_DMA_PORT_EN_AESTX	0x04		/* AES transmitter DMA port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define H2I_DMA_PORT_EN_CODECTX	0x08		/* CODEC transmit DMA port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define H2I_DMA_PORT_EN_CODECR	0x10		/* CODEC receive DMA port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define H2I_DMA_END		0x9108 		/* global dma endian select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define H2I_DMA_END_SY_IN	0x01		/* Synth_in DMA port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define H2I_DMA_END_AESRX	0x02		/* AES receiver DMA port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define H2I_DMA_END_AESTX	0x04		/* AES transmitter DMA port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define H2I_DMA_END_CODECTX	0x08		/* CODEC transmit DMA port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define H2I_DMA_END_CODECR	0x10		/* CODEC receive DMA port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 						/* 0=b_end 1=l_end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define H2I_DMA_DRV		0x910C  	/* global PBUS DMA enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define H2I_SYNTH_C		0x1104		/* Synth DMA control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define H2I_AESRX_C		0x1204	 	/* AES RX dma control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define H2I_C_TS_EN		0x20		/* Timestamp enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define H2I_C_TS_FRMT		0x40		/* Timestamp format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define H2I_C_NAUDIO		0x80		/* Sign extend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* AESRX CTL, 16 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define H2I_AESTX_C		0x1304		/* AES TX DMA control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define H2I_AESTX_C_CLKID_SHIFT	3		/* Bresenham Clock Gen 1-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define H2I_AESTX_C_CLKID_M	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define H2I_AESTX_C_DATAT_SHIFT	8		/* 1=mono 2=stereo (3=quad) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define H2I_AESTX_C_DATAT_M	0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* CODEC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define H2I_DAC_C1		0x1404 		/* DAC DMA control, 16 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define H2I_DAC_C2		0x1408		/* DAC DMA control, 32 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define H2I_ADC_C1		0x1504 		/* ADC DMA control, 16 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define H2I_ADC_C2		0x1508		/* ADC DMA control, 32 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Bits in CTL1 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define H2I_C1_DMA_SHIFT	0		/* DMA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define H2I_C1_DMA_M		0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define H2I_C1_CLKID_SHIFT	3		/* Bresenham Clock Gen 1-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define H2I_C1_CLKID_M		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define H2I_C1_DATAT_SHIFT	8		/* 1=mono 2=stereo (3=quad) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define H2I_C1_DATAT_M		0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Bits in CTL2 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define H2I_C2_R_GAIN_SHIFT	0		/* right a/d input gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define H2I_C2_R_GAIN_M		0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define H2I_C2_L_GAIN_SHIFT	4		/* left a/d input gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define H2I_C2_L_GAIN_M		0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define H2I_C2_R_SEL		0x100		/* right input select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define H2I_C2_L_SEL		0x200		/* left input select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define H2I_C2_MUTE		0x400		/* mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define H2I_C2_DO1		0x00010000	/* digital output port bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define H2I_C2_DO2		0x00020000	/* digital output port bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define H2I_C2_R_ATT_SHIFT	18		/* right d/a output - */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define H2I_C2_R_ATT_M		0x007c0000	/* attenuation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define H2I_C2_L_ATT_SHIFT	23		/* left d/a output - */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define H2I_C2_L_ATT_M		0x0f800000	/* attenuation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define H2I_SYNTH_MAP_C		0x1104		/* synth dma handshake ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Clock generator CTL 1, 16 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define H2I_BRES1_C1		0x2104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define H2I_BRES2_C1		0x2204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define H2I_BRES3_C1		0x2304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define H2I_BRES_C1_SHIFT	0		/* 0=48.0 1=44.1 2=aes_rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define H2I_BRES_C1_M		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* Clock generator CTL 2, 32 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define H2I_BRES1_C2		0x2108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define H2I_BRES2_C2		0x2208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define H2I_BRES3_C2		0x2308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define H2I_BRES_C2_INC_SHIFT	0		/* increment value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define H2I_BRES_C2_INC_M	0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define H2I_BRES_C2_MOD_SHIFT	16		/* modcontrol value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define H2I_BRES_C2_MOD_M	0xffff0000	/* modctrl=0xffff&(modinc-1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* Unix timer, 64 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define H2I_UTIME		0x3104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define H2I_UTIME_0_LD		0xffff		/* microseconds, LSB's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define H2I_UTIME_1_LD0		0x0f		/* microseconds, MSB's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define H2I_UTIME_1_LD1		0xf0		/* tenths of microseconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define H2I_UTIME_2_LD		0xffff		/* seconds, LSB's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define H2I_UTIME_3_LD		0xffff		/* seconds, MSB's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct hal2_ctl_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	u32 _unused0[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	u32 isr;		/* 0x10 Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	u32 _unused1[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	u32 rev;		/* 0x20 Revision Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	u32 _unused2[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	u32 iar;		/* 0x30 Indirect Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	u32 _unused3[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	u32 idr0;		/* 0x40 Indirect Data Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	u32 _unused4[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	u32 idr1;		/* 0x50 Indirect Data Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	u32 _unused5[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	u32 idr2;		/* 0x60 Indirect Data Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	u32 _unused6[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	u32 idr3;		/* 0x70 Indirect Data Register 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct hal2_aes_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	u32 rx_stat[2];	/* Status registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	u32 rx_cr[2];		/* Control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	u32 rx_ud[4];		/* User data window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	u32 rx_st[24];		/* Channel status data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	u32 tx_stat[1];	/* Status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	u32 tx_cr[3];		/* Control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	u32 tx_ud[4];		/* User data window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	u32 tx_st[24];		/* Channel status data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct hal2_vol_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	u32 right;		/* Right volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	u32 left;		/* Left volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct hal2_syn_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	u32 _unused0[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	u32 page;		/* DOC Page register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	u32 regsel;		/* DOC Register selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	u32 dlow;		/* DOC Data low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	u32 dhigh;		/* DOC Data high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	u32 irq;		/* IRQ Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	u32 dram;		/* DRAM Access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #endif	/* __HAL2_H */