^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * AD1843 low level driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2003 Vivien Chappelier <vivien.chappelier@linux-mips.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2008 Thomas Bogendoerfer <tsbogend@alpha.franken.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * inspired from vwsnd.c (SGI VW audio driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright 1999 Silicon Graphics, Inc. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <sound/ad1843.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * AD1843 bitfield definitions. All are named as in the AD1843 data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * sheet, with ad1843_ prepended and individual bit numbers removed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * E.g., bits LSS0 through LSS2 become ad1843_LSS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Only the bitfields we need are defined.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct ad1843_bitfield {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) char reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) char lo_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) char nbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static const struct ad1843_bitfield
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) ad1843_PDNO = { 0, 14, 1 }, /* Converter Power-Down Flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) ad1843_INIT = { 0, 15, 1 }, /* Clock Initialization Flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) ad1843_RIG = { 2, 0, 4 }, /* Right ADC Input Gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) ad1843_RMGE = { 2, 4, 1 }, /* Right ADC Mic Gain Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) ad1843_RSS = { 2, 5, 3 }, /* Right ADC Source Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) ad1843_LIG = { 2, 8, 4 }, /* Left ADC Input Gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) ad1843_LMGE = { 2, 12, 1 }, /* Left ADC Mic Gain Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) ad1843_LSS = { 2, 13, 3 }, /* Left ADC Source Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) ad1843_RD2M = { 3, 0, 5 }, /* Right DAC 2 Mix Gain/Atten */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ad1843_RD2MM = { 3, 7, 1 }, /* Right DAC 2 Mix Mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) ad1843_LD2M = { 3, 8, 5 }, /* Left DAC 2 Mix Gain/Atten */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) ad1843_LD2MM = { 3, 15, 1 }, /* Left DAC 2 Mix Mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ad1843_RX1M = { 4, 0, 5 }, /* Right Aux 1 Mix Gain/Atten */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ad1843_RX1MM = { 4, 7, 1 }, /* Right Aux 1 Mix Mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) ad1843_LX1M = { 4, 8, 5 }, /* Left Aux 1 Mix Gain/Atten */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ad1843_LX1MM = { 4, 15, 1 }, /* Left Aux 1 Mix Mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ad1843_RX2M = { 5, 0, 5 }, /* Right Aux 2 Mix Gain/Atten */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) ad1843_RX2MM = { 5, 7, 1 }, /* Right Aux 2 Mix Mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ad1843_LX2M = { 5, 8, 5 }, /* Left Aux 2 Mix Gain/Atten */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) ad1843_LX2MM = { 5, 15, 1 }, /* Left Aux 2 Mix Mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) ad1843_RMCM = { 7, 0, 5 }, /* Right Mic Mix Gain/Atten */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ad1843_RMCMM = { 7, 7, 1 }, /* Right Mic Mix Mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ad1843_LMCM = { 7, 8, 5 }, /* Left Mic Mix Gain/Atten */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ad1843_LMCMM = { 7, 15, 1 }, /* Left Mic Mix Mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ad1843_HPOS = { 8, 4, 1 }, /* Headphone Output Voltage Swing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ad1843_HPOM = { 8, 5, 1 }, /* Headphone Output Mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ad1843_MPOM = { 8, 6, 1 }, /* Mono Output Mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ad1843_RDA1G = { 9, 0, 6 }, /* Right DAC1 Analog/Digital Gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ad1843_RDA1GM = { 9, 7, 1 }, /* Right DAC1 Analog Mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ad1843_LDA1G = { 9, 8, 6 }, /* Left DAC1 Analog/Digital Gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ad1843_LDA1GM = { 9, 15, 1 }, /* Left DAC1 Analog Mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) ad1843_RDA2G = { 10, 0, 6 }, /* Right DAC2 Analog/Digital Gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) ad1843_RDA2GM = { 10, 7, 1 }, /* Right DAC2 Analog Mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ad1843_LDA2G = { 10, 8, 6 }, /* Left DAC2 Analog/Digital Gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) ad1843_LDA2GM = { 10, 15, 1 }, /* Left DAC2 Analog Mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ad1843_RDA1AM = { 11, 7, 1 }, /* Right DAC1 Digital Mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ad1843_LDA1AM = { 11, 15, 1 }, /* Left DAC1 Digital Mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ad1843_RDA2AM = { 12, 7, 1 }, /* Right DAC2 Digital Mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ad1843_LDA2AM = { 12, 15, 1 }, /* Left DAC2 Digital Mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ad1843_ADLC = { 15, 0, 2 }, /* ADC Left Sample Rate Source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ad1843_ADRC = { 15, 2, 2 }, /* ADC Right Sample Rate Source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ad1843_DA1C = { 15, 8, 2 }, /* DAC1 Sample Rate Source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ad1843_DA2C = { 15, 10, 2 }, /* DAC2 Sample Rate Source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ad1843_C1C = { 17, 0, 16 }, /* Clock 1 Sample Rate Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ad1843_C2C = { 20, 0, 16 }, /* Clock 2 Sample Rate Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ad1843_C3C = { 23, 0, 16 }, /* Clock 3 Sample Rate Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ad1843_DAADL = { 25, 4, 2 }, /* Digital ADC Left Source Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ad1843_DAADR = { 25, 6, 2 }, /* Digital ADC Right Source Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ad1843_DAMIX = { 25, 14, 1 }, /* DAC Digital Mix Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ad1843_DRSFLT = { 25, 15, 1 }, /* Digital Reampler Filter Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ad1843_ADLF = { 26, 0, 2 }, /* ADC Left Channel Data Format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ad1843_ADRF = { 26, 2, 2 }, /* ADC Right Channel Data Format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ad1843_ADTLK = { 26, 4, 1 }, /* ADC Transmit Lock Mode Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ad1843_SCF = { 26, 7, 1 }, /* SCLK Frequency Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ad1843_DA1F = { 26, 8, 2 }, /* DAC1 Data Format Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ad1843_DA2F = { 26, 10, 2 }, /* DAC2 Data Format Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ad1843_DA1SM = { 26, 14, 1 }, /* DAC1 Stereo/Mono Mode Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ad1843_DA2SM = { 26, 15, 1 }, /* DAC2 Stereo/Mono Mode Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ad1843_ADLEN = { 27, 0, 1 }, /* ADC Left Channel Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ad1843_ADREN = { 27, 1, 1 }, /* ADC Right Channel Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ad1843_AAMEN = { 27, 4, 1 }, /* Analog to Analog Mix Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ad1843_ANAEN = { 27, 7, 1 }, /* Analog Channel Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ad1843_DA1EN = { 27, 8, 1 }, /* DAC1 Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ad1843_DA2EN = { 27, 9, 1 }, /* DAC2 Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ad1843_DDMEN = { 27, 12, 1 }, /* DAC2 to DAC1 Mix Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ad1843_C1EN = { 28, 11, 1 }, /* Clock Generator 1 Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ad1843_C2EN = { 28, 12, 1 }, /* Clock Generator 2 Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ad1843_C3EN = { 28, 13, 1 }, /* Clock Generator 3 Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ad1843_PDNI = { 28, 15, 1 }; /* Converter Power Down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * The various registers of the AD1843 use three different formats for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * specifying gain. The ad1843_gain structure parameterizes the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * formats.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct ad1843_gain {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int negative; /* nonzero if gain is negative. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) const struct ad1843_bitfield *lfield;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) const struct ad1843_bitfield *rfield;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) const struct ad1843_bitfield *lmute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) const struct ad1843_bitfield *rmute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static const struct ad1843_gain ad1843_gain_RECLEV = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .negative = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .lfield = &ad1843_LIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .rfield = &ad1843_RIG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static const struct ad1843_gain ad1843_gain_LINE = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .negative = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .lfield = &ad1843_LX1M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .rfield = &ad1843_RX1M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .lmute = &ad1843_LX1MM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .rmute = &ad1843_RX1MM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static const struct ad1843_gain ad1843_gain_LINE_2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .negative = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .lfield = &ad1843_LDA2G,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .rfield = &ad1843_RDA2G,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .lmute = &ad1843_LDA2GM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .rmute = &ad1843_RDA2GM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static const struct ad1843_gain ad1843_gain_MIC = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .negative = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .lfield = &ad1843_LMCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .rfield = &ad1843_RMCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .lmute = &ad1843_LMCMM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .rmute = &ad1843_RMCMM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static const struct ad1843_gain ad1843_gain_PCM_0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .negative = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .lfield = &ad1843_LDA1G,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .rfield = &ad1843_RDA1G,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .lmute = &ad1843_LDA1GM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .rmute = &ad1843_RDA1GM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const struct ad1843_gain ad1843_gain_PCM_1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .negative = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .lfield = &ad1843_LD2M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .rfield = &ad1843_RD2M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .lmute = &ad1843_LD2MM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .rmute = &ad1843_RD2MM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static const struct ad1843_gain *ad1843_gain[AD1843_GAIN_SIZE] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) &ad1843_gain_RECLEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) &ad1843_gain_LINE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) &ad1843_gain_LINE_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) &ad1843_gain_MIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) &ad1843_gain_PCM_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) &ad1843_gain_PCM_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* read the current value of an AD1843 bitfield. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int ad1843_read_bits(struct snd_ad1843 *ad1843,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) const struct ad1843_bitfield *field)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) w = ad1843->read(ad1843->chip, field->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return w >> field->lo_bit & ((1 << field->nbits) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * write a new value to an AD1843 bitfield and return the old value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int ad1843_write_bits(struct snd_ad1843 *ad1843,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) const struct ad1843_bitfield *field,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int newval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) int w, mask, oldval, newbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) w = ad1843->read(ad1843->chip, field->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) mask = ((1 << field->nbits) - 1) << field->lo_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) oldval = (w & mask) >> field->lo_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) newbits = (newval << field->lo_bit) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) w = (w & ~mask) | newbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ad1843->write(ad1843->chip, field->reg, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return oldval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * ad1843_read_multi reads multiple bitfields from the same AD1843
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * register. It uses a single read cycle to do it. (Reading the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * ad1843 requires 256 bit times at 12.288 MHz, or nearly 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * microseconds.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * Called like this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * ad1843_read_multi(ad1843, nfields,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * &ad1843_FIELD1, &val1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * &ad1843_FIELD2, &val2, ...);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static void ad1843_read_multi(struct snd_ad1843 *ad1843, int argcount, ...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) va_list ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) const struct ad1843_bitfield *fp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int w = 0, mask, *value, reg = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) va_start(ap, argcount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) while (--argcount >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) fp = va_arg(ap, const struct ad1843_bitfield *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) value = va_arg(ap, int *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (reg == -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) reg = fp->reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) w = ad1843->read(ad1843->chip, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) mask = (1 << fp->nbits) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) *value = w >> fp->lo_bit & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) va_end(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * ad1843_write_multi stores multiple bitfields into the same AD1843
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * register. It uses one read and one write cycle to do it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * Called like this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * ad1843_write_multi(ad1843, nfields,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * &ad1843_FIELD1, val1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * &ad1843_FIELF2, val2, ...);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static void ad1843_write_multi(struct snd_ad1843 *ad1843, int argcount, ...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) va_list ap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) const struct ad1843_bitfield *fp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int w, m, mask, bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) reg = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) va_start(ap, argcount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) while (--argcount >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) fp = va_arg(ap, const struct ad1843_bitfield *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) value = va_arg(ap, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (reg == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) reg = fp->reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) WARN_ON(reg != fp->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) m = ((1 << fp->nbits) - 1) << fp->lo_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) mask |= m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) bits |= (value << fp->lo_bit) & m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) va_end(ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (~mask & 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) w = ad1843->read(ad1843->chip, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) w = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) w = (w & ~mask) | bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) ad1843->write(ad1843->chip, reg, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int ad1843_get_gain_max(struct snd_ad1843 *ad1843, int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) const struct ad1843_gain *gp = ad1843_gain[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ret = (1 << gp->lfield->nbits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (!gp->lmute)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ret -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * ad1843_get_gain reads the specified register and extracts the gain value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * using the supplied gain type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int ad1843_get_gain(struct snd_ad1843 *ad1843, int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) int lg, rg, lm, rm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) const struct ad1843_gain *gp = ad1843_gain[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned short mask = (1 << gp->lfield->nbits) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ad1843_read_multi(ad1843, 2, gp->lfield, &lg, gp->rfield, &rg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (gp->negative) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) lg = mask - lg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) rg = mask - rg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (gp->lmute) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) ad1843_read_multi(ad1843, 2, gp->lmute, &lm, gp->rmute, &rm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (lm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) lg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (rm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) rg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return lg << 0 | rg << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * Set an audio channel's gain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * Returns the new gain, which may be lower than the old gain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) int ad1843_set_gain(struct snd_ad1843 *ad1843, int id, int newval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) const struct ad1843_gain *gp = ad1843_gain[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) unsigned short mask = (1 << gp->lfield->nbits) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) int lg = (newval >> 0) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) int rg = (newval >> 8) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) int lm = (lg == 0) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) int rm = (rg == 0) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (gp->negative) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) lg = mask - lg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) rg = mask - rg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (gp->lmute)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ad1843_write_multi(ad1843, 2, gp->lmute, lm, gp->rmute, rm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ad1843_write_multi(ad1843, 2, gp->lfield, lg, gp->rfield, rg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return ad1843_get_gain(ad1843, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* Returns the current recording source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) int ad1843_get_recsrc(struct snd_ad1843 *ad1843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) int val = ad1843_read_bits(ad1843, &ad1843_LSS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (val < 0 || val > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) val = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ad1843_write_multi(ad1843, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) &ad1843_LSS, val, &ad1843_RSS, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * Set recording source.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * Returns newsrc on success, -errno on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) int ad1843_set_recsrc(struct snd_ad1843 *ad1843, int newsrc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (newsrc < 0 || newsrc > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ad1843_write_multi(ad1843, 2, &ad1843_LSS, newsrc, &ad1843_RSS, newsrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return newsrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* Setup ad1843 for D/A conversion. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) void ad1843_setup_dac(struct snd_ad1843 *ad1843,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) unsigned int id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) unsigned int framerate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) snd_pcm_format_t fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) unsigned int channels)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) int ad_fmt = 0, ad_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) switch (fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) case SNDRV_PCM_FORMAT_S8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ad_fmt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) case SNDRV_PCM_FORMAT_U8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ad_fmt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) case SNDRV_PCM_FORMAT_S16_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ad_fmt = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) case SNDRV_PCM_FORMAT_MU_LAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) ad_fmt = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) case SNDRV_PCM_FORMAT_A_LAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) ad_fmt = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) switch (channels) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ad_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ad_mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ad1843_write_bits(ad1843, &ad1843_C2C, framerate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ad1843_write_multi(ad1843, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) &ad1843_DA2SM, ad_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) &ad1843_DA2F, ad_fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ad1843_write_bits(ad1843, &ad1843_C1C, framerate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) ad1843_write_multi(ad1843, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) &ad1843_DA1SM, ad_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) &ad1843_DA1F, ad_fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) void ad1843_shutdown_dac(struct snd_ad1843 *ad1843, unsigned int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) ad1843_write_bits(ad1843, &ad1843_DA2F, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ad1843_write_bits(ad1843, &ad1843_DA1F, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) void ad1843_setup_adc(struct snd_ad1843 *ad1843,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) unsigned int framerate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) snd_pcm_format_t fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) unsigned int channels)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) int da_fmt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) switch (fmt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) case SNDRV_PCM_FORMAT_S8: da_fmt = 0; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) case SNDRV_PCM_FORMAT_U8: da_fmt = 0; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) case SNDRV_PCM_FORMAT_S16_LE: da_fmt = 1; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) case SNDRV_PCM_FORMAT_MU_LAW: da_fmt = 2; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) case SNDRV_PCM_FORMAT_A_LAW: da_fmt = 3; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) default: break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ad1843_write_bits(ad1843, &ad1843_C3C, framerate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) ad1843_write_multi(ad1843, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) &ad1843_ADLF, da_fmt, &ad1843_ADRF, da_fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) void ad1843_shutdown_adc(struct snd_ad1843 *ad1843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* nothing to do */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * Fully initialize the ad1843. As described in the AD1843 data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * sheet, section "START-UP SEQUENCE". The numbered comments are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * subsection headings from the data sheet. See the data sheet, pages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * 52-54, for more info.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * return 0 on success, -errno on failure. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) int ad1843_init(struct snd_ad1843 *ad1843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) unsigned long later;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (ad1843_read_bits(ad1843, &ad1843_INIT) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) printk(KERN_ERR "ad1843: AD1843 won't initialize\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) ad1843_write_bits(ad1843, &ad1843_SCF, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /* 4. Put the conversion resources into standby. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) ad1843_write_bits(ad1843, &ad1843_PDNI, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) later = jiffies + msecs_to_jiffies(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) while (ad1843_read_bits(ad1843, &ad1843_PDNO)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (time_after(jiffies, later)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) printk(KERN_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) "ad1843: AD1843 won't power up\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) schedule_timeout_interruptible(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* 5. Power up the clock generators and enable clock output pins. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) ad1843_write_multi(ad1843, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) &ad1843_C1EN, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) &ad1843_C2EN, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) &ad1843_C3EN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* 6. Configure conversion resources while they are in standby. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* DAC1/2 use clock 1/2 as source, ADC uses clock 3. Always. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) ad1843_write_multi(ad1843, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) &ad1843_DA1C, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) &ad1843_DA2C, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) &ad1843_ADLC, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) &ad1843_ADRC, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /* 7. Enable conversion resources. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) ad1843_write_bits(ad1843, &ad1843_ADTLK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) ad1843_write_multi(ad1843, 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) &ad1843_ANAEN, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) &ad1843_AAMEN, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) &ad1843_DA1EN, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) &ad1843_DA2EN, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) &ad1843_DDMEN, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) &ad1843_ADLEN, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) &ad1843_ADREN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* 8. Configure conversion resources while they are enabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /* set gain to 0 for all channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) ad1843_set_gain(ad1843, AD1843_GAIN_RECLEV, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) ad1843_set_gain(ad1843, AD1843_GAIN_LINE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) ad1843_set_gain(ad1843, AD1843_GAIN_LINE_2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) ad1843_set_gain(ad1843, AD1843_GAIN_MIC, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) ad1843_set_gain(ad1843, AD1843_GAIN_PCM_0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) ad1843_set_gain(ad1843, AD1843_GAIN_PCM_1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* Unmute all channels. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* DAC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) ad1843_write_multi(ad1843, 2, &ad1843_LDA1GM, 0, &ad1843_RDA1GM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* DAC2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) ad1843_write_multi(ad1843, 2, &ad1843_LDA2GM, 0, &ad1843_RDA2GM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /* Set default recording source to Line In and set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * mic gain to +20 dB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) ad1843_set_recsrc(ad1843, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) ad1843_write_multi(ad1843, 2, &ad1843_LMGE, 1, &ad1843_RMGE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* Set Speaker Out level to +/- 4V and unmute it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) ad1843_write_multi(ad1843, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) &ad1843_HPOS, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) &ad1843_HPOM, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) &ad1843_MPOM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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