^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Routines for control of CS4231(A)/CS4232/InterWave & compatible chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Bugs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * - sometimes record brokes playback with WSS portion of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Yamaha OPL3-SA3 chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * - CS4231 (GUS MAX) - still trouble with occasional noises
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * - broken initialization?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <sound/wss.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <sound/tlv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MODULE_DESCRIPTION("Routines for control of CS4231(A)/CS4232/InterWave & compatible chips");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SNDRV_DEBUG_MCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Some variables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static const unsigned char freq_bits[14] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* 5510 */ 0x00 | CS4231_XTAL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* 6620 */ 0x0E | CS4231_XTAL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* 8000 */ 0x00 | CS4231_XTAL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* 9600 */ 0x0E | CS4231_XTAL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* 11025 */ 0x02 | CS4231_XTAL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* 16000 */ 0x02 | CS4231_XTAL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* 18900 */ 0x04 | CS4231_XTAL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* 22050 */ 0x06 | CS4231_XTAL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* 27042 */ 0x04 | CS4231_XTAL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* 32000 */ 0x06 | CS4231_XTAL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* 33075 */ 0x0C | CS4231_XTAL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* 37800 */ 0x08 | CS4231_XTAL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* 44100 */ 0x0A | CS4231_XTAL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* 48000 */ 0x0C | CS4231_XTAL1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static const unsigned int rates[14] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 27042, 32000, 33075, 37800, 44100, 48000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static const struct snd_pcm_hw_constraint_list hw_constraints_rates = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .count = ARRAY_SIZE(rates),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .list = rates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static int snd_wss_xrate(struct snd_pcm_runtime *runtime)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) &hw_constraints_rates);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static const unsigned char snd_wss_original_image[32] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 0x00, /* 00/00 - lic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 0x00, /* 01/01 - ric */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 0x9f, /* 02/02 - la1ic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 0x9f, /* 03/03 - ra1ic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 0x9f, /* 04/04 - la2ic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 0x9f, /* 05/05 - ra2ic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 0xbf, /* 06/06 - loc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 0xbf, /* 07/07 - roc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 0x20, /* 08/08 - pdfr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) CS4231_AUTOCALIB, /* 09/09 - ic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 0x00, /* 0a/10 - pc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 0x00, /* 0b/11 - ti */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) CS4231_MODE2, /* 0c/12 - mi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 0xfc, /* 0d/13 - lbc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) 0x00, /* 0e/14 - pbru */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) 0x00, /* 0f/15 - pbrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) 0x80, /* 10/16 - afei */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) 0x01, /* 11/17 - afeii */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) 0x9f, /* 12/18 - llic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) 0x9f, /* 13/19 - rlic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) 0x00, /* 14/20 - tlb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) 0x00, /* 15/21 - thb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) 0x00, /* 16/22 - la3mic/reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 0x00, /* 17/23 - ra3mic/reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 0x00, /* 18/24 - afs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 0x00, /* 19/25 - lamoc/version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 0xcf, /* 1a/26 - mioc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 0x00, /* 1b/27 - ramoc/reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 0x20, /* 1c/28 - cdfr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 0x00, /* 1d/29 - res4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 0x00, /* 1e/30 - cbru */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 0x00, /* 1f/31 - cbrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const unsigned char snd_opti93x_original_image[32] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 0x00, /* 00/00 - l_mixout_outctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 0x00, /* 01/01 - r_mixout_outctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 0x88, /* 02/02 - l_cd_inctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 0x88, /* 03/03 - r_cd_inctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 0x88, /* 04/04 - l_a1/fm_inctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 0x88, /* 05/05 - r_a1/fm_inctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 0x80, /* 06/06 - l_dac_inctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 0x80, /* 07/07 - r_dac_inctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 0x00, /* 08/08 - ply_dataform_reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 0x00, /* 09/09 - if_conf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 0x00, /* 0a/10 - pin_ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 0x00, /* 0b/11 - err_init_reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 0x0a, /* 0c/12 - id_reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 0x00, /* 0d/13 - reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 0x00, /* 0e/14 - ply_upcount_reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 0x00, /* 0f/15 - ply_lowcount_reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 0x88, /* 10/16 - reserved/l_a1_inctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 0x88, /* 11/17 - reserved/r_a1_inctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 0x88, /* 12/18 - l_line_inctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 0x88, /* 13/19 - r_line_inctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 0x88, /* 14/20 - l_mic_inctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 0x88, /* 15/21 - r_mic_inctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 0x80, /* 16/22 - l_out_outctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 0x80, /* 17/23 - r_out_outctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 0x00, /* 18/24 - reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 0x00, /* 19/25 - reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 0x00, /* 1a/26 - reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 0x00, /* 1b/27 - reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 0x00, /* 1c/28 - cap_dataform_reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 0x00, /* 1d/29 - reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 0x00, /* 1e/30 - cap_upcount_reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 0x00 /* 1f/31 - cap_lowcount_reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * Basic I/O functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static inline void wss_outb(struct snd_wss *chip, u8 offset, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) outb(val, chip->port + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static inline u8 wss_inb(struct snd_wss *chip, u8 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return inb(chip->port + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static void snd_wss_wait(struct snd_wss *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) for (timeout = 250;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) timeout > 0 && (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) timeout--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static void snd_wss_dout(struct snd_wss *chip, unsigned char reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned char value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) for (timeout = 250;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) timeout > 0 && (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) timeout--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) wss_outb(chip, CS4231P(REG), value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) void snd_wss_out(struct snd_wss *chip, unsigned char reg, unsigned char value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) snd_wss_wait(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #ifdef CONFIG_SND_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) snd_printk(KERN_DEBUG "out: auto calibration time out "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) "- reg = 0x%x, value = 0x%x\n", reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) wss_outb(chip, CS4231P(REG), value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) chip->image[reg] = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) snd_printdd("codec out - reg 0x%x = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) chip->mce_bit | reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) EXPORT_SYMBOL(snd_wss_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned char snd_wss_in(struct snd_wss *chip, unsigned char reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) snd_wss_wait(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #ifdef CONFIG_SND_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) snd_printk(KERN_DEBUG "in: auto calibration time out "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) "- reg = 0x%x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return wss_inb(chip, CS4231P(REG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) EXPORT_SYMBOL(snd_wss_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) void snd_cs4236_ext_out(struct snd_wss *chip, unsigned char reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) unsigned char val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | 0x17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) wss_outb(chip, CS4231P(REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) reg | (chip->image[CS4236_EXT_REG] & 0x01));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) wss_outb(chip, CS4231P(REG), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) chip->eimage[CS4236_REG(reg)] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) printk(KERN_DEBUG "ext out : reg = 0x%x, val = 0x%x\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) EXPORT_SYMBOL(snd_cs4236_ext_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) unsigned char snd_cs4236_ext_in(struct snd_wss *chip, unsigned char reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | 0x17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) wss_outb(chip, CS4231P(REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) reg | (chip->image[CS4236_EXT_REG] & 0x01));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #if 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return wss_inb(chip, CS4231P(REG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) unsigned char res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) res = wss_inb(chip, CS4231P(REG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) printk(KERN_DEBUG "ext in : reg = 0x%x, val = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) reg, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) EXPORT_SYMBOL(snd_cs4236_ext_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static void snd_wss_debug(struct snd_wss *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) printk(KERN_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) "CS4231 REGS: INDEX = 0x%02x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) " STATUS = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) wss_inb(chip, CS4231P(REGSEL)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) wss_inb(chip, CS4231P(STATUS)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) printk(KERN_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) " 0x00: left input = 0x%02x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) " 0x10: alt 1 (CFIG 2) = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) snd_wss_in(chip, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) snd_wss_in(chip, 0x10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) printk(KERN_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) " 0x01: right input = 0x%02x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) " 0x11: alt 2 (CFIG 3) = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) snd_wss_in(chip, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) snd_wss_in(chip, 0x11));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) printk(KERN_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) " 0x02: GF1 left input = 0x%02x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) " 0x12: left line in = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) snd_wss_in(chip, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) snd_wss_in(chip, 0x12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) printk(KERN_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) " 0x03: GF1 right input = 0x%02x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) " 0x13: right line in = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) snd_wss_in(chip, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) snd_wss_in(chip, 0x13));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) printk(KERN_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) " 0x04: CD left input = 0x%02x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) " 0x14: timer low = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) snd_wss_in(chip, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) snd_wss_in(chip, 0x14));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) printk(KERN_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) " 0x05: CD right input = 0x%02x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) " 0x15: timer high = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) snd_wss_in(chip, 0x05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) snd_wss_in(chip, 0x15));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) printk(KERN_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) " 0x06: left output = 0x%02x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) " 0x16: left MIC (PnP) = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) snd_wss_in(chip, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) snd_wss_in(chip, 0x16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) printk(KERN_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) " 0x07: right output = 0x%02x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) " 0x17: right MIC (PnP) = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) snd_wss_in(chip, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) snd_wss_in(chip, 0x17));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) printk(KERN_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) " 0x08: playback format = 0x%02x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) " 0x18: IRQ status = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) snd_wss_in(chip, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) snd_wss_in(chip, 0x18));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) printk(KERN_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) " 0x09: iface (CFIG 1) = 0x%02x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) " 0x19: left line out = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) snd_wss_in(chip, 0x09),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) snd_wss_in(chip, 0x19));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) printk(KERN_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) " 0x0a: pin control = 0x%02x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) " 0x1a: mono control = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) snd_wss_in(chip, 0x0a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) snd_wss_in(chip, 0x1a));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) printk(KERN_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) " 0x0b: init & status = 0x%02x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) " 0x1b: right line out = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) snd_wss_in(chip, 0x0b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) snd_wss_in(chip, 0x1b));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) printk(KERN_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) " 0x0c: revision & mode = 0x%02x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) " 0x1c: record format = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) snd_wss_in(chip, 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) snd_wss_in(chip, 0x1c));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) printk(KERN_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) " 0x0d: loopback = 0x%02x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) " 0x1d: var freq (PnP) = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) snd_wss_in(chip, 0x0d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) snd_wss_in(chip, 0x1d));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) printk(KERN_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) " 0x0e: ply upr count = 0x%02x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) " 0x1e: ply lwr count = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) snd_wss_in(chip, 0x0e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) snd_wss_in(chip, 0x1e));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) printk(KERN_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) " 0x0f: rec upr count = 0x%02x "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) " 0x1f: rec lwr count = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) snd_wss_in(chip, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) snd_wss_in(chip, 0x1f));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * CS4231 detection / MCE routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static void snd_wss_busy_wait(struct snd_wss *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* huh.. looks like this sequence is proper for CS4231A chip (GUS MAX) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) for (timeout = 5; timeout > 0; timeout--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) wss_inb(chip, CS4231P(REGSEL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* end of cleanup sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) for (timeout = 25000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) timeout > 0 && (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) timeout--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) void snd_wss_mce_up(struct snd_wss *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) snd_wss_wait(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #ifdef CONFIG_SND_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) snd_printk(KERN_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) "mce_up - auto calibration time out (0)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) chip->mce_bit |= CS4231_MCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) timeout = wss_inb(chip, CS4231P(REGSEL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (timeout == 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) snd_printk(KERN_DEBUG "mce_up [0x%lx]: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) "serious init problem - codec still busy\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) chip->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (!(timeout & CS4231_MCE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) wss_outb(chip, CS4231P(REGSEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) chip->mce_bit | (timeout & 0x1f));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) EXPORT_SYMBOL(snd_wss_mce_up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) void snd_wss_mce_down(struct snd_wss *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) unsigned long end_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) int hw_mask = WSS_HW_CS4231_MASK | WSS_HW_CS4232_MASK | WSS_HW_AD1848;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) snd_wss_busy_wait(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #ifdef CONFIG_SND_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) snd_printk(KERN_DEBUG "mce_down [0x%lx] - "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) "auto calibration time out (0)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) (long)CS4231P(REGSEL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) chip->mce_bit &= ~CS4231_MCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) timeout = wss_inb(chip, CS4231P(REGSEL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (timeout == 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) snd_printk(KERN_DEBUG "mce_down [0x%lx]: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) "serious init problem - codec still busy\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) chip->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if ((timeout & CS4231_MCE) == 0 || !(chip->hardware & hw_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * Wait for (possible -- during init auto-calibration may not be set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * calibration process to start. Needs up to 5 sample periods on AD1848
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * which at the slowest possible rate of 5.5125 kHz means 907 us.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) snd_printdd("(1) jiffies = %lu\n", jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* check condition up to 250 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) end_time = jiffies + msecs_to_jiffies(250);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) while (snd_wss_in(chip, CS4231_TEST_INIT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) CS4231_CALIB_IN_PROGRESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (time_after(jiffies, end_time)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) snd_printk(KERN_ERR "mce_down - "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) "auto calibration time out (2)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) snd_printdd("(2) jiffies = %lu\n", jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* check condition up to 100 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) end_time = jiffies + msecs_to_jiffies(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) while (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (time_after(jiffies, end_time)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) snd_printk(KERN_ERR "mce_down - auto calibration time out (3)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) snd_printdd("(3) jiffies = %lu\n", jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) snd_printd("mce_down - exit = 0x%x\n", wss_inb(chip, CS4231P(REGSEL)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) EXPORT_SYMBOL(snd_wss_mce_down);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static unsigned int snd_wss_get_count(unsigned char format, unsigned int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) switch (format & 0xe0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) case CS4231_LINEAR_16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) case CS4231_LINEAR_16_BIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) size >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) case CS4231_ADPCM_16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return size >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (format & CS4231_STEREO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) size >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static int snd_wss_trigger(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct snd_wss *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) int result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) unsigned int what;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct snd_pcm_substream *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) int do_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) case SNDRV_PCM_TRIGGER_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) case SNDRV_PCM_TRIGGER_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) do_start = 1; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) case SNDRV_PCM_TRIGGER_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) case SNDRV_PCM_TRIGGER_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) do_start = 0; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) what = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) snd_pcm_group_for_each_entry(s, substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (s == chip->playback_substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) what |= CS4231_PLAYBACK_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) snd_pcm_trigger_done(s, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) } else if (s == chip->capture_substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) what |= CS4231_RECORD_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) snd_pcm_trigger_done(s, substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) spin_lock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (do_start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) chip->image[CS4231_IFACE_CTRL] |= what;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (chip->trigger)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) chip->trigger(chip, what, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) chip->image[CS4231_IFACE_CTRL] &= ~what;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (chip->trigger)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) chip->trigger(chip, what, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) snd_wss_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) spin_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) snd_wss_debug(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * CODEC I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static unsigned char snd_wss_get_rate(unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) for (i = 0; i < ARRAY_SIZE(rates); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (rate == rates[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return freq_bits[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) // snd_BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return freq_bits[ARRAY_SIZE(rates) - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static unsigned char snd_wss_get_format(struct snd_wss *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) snd_pcm_format_t format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) int channels)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) unsigned char rformat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) rformat = CS4231_LINEAR_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) switch (format) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) case SNDRV_PCM_FORMAT_MU_LAW: rformat = CS4231_ULAW_8; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) case SNDRV_PCM_FORMAT_A_LAW: rformat = CS4231_ALAW_8; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) case SNDRV_PCM_FORMAT_S16_LE: rformat = CS4231_LINEAR_16; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) case SNDRV_PCM_FORMAT_S16_BE: rformat = CS4231_LINEAR_16_BIG; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) case SNDRV_PCM_FORMAT_IMA_ADPCM: rformat = CS4231_ADPCM_16; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (channels > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) rformat |= CS4231_STEREO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) snd_printk(KERN_DEBUG "get_format: 0x%x (mode=0x%x)\n", format, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return rformat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static void snd_wss_calibrate_mute(struct snd_wss *chip, int mute)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) mute = mute ? 0x80 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (chip->calibrate_mute == mute) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (!mute) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) snd_wss_dout(chip, CS4231_LEFT_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) chip->image[CS4231_LEFT_INPUT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) snd_wss_dout(chip, CS4231_RIGHT_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) chip->image[CS4231_RIGHT_INPUT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) snd_wss_dout(chip, CS4231_LOOPBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) chip->image[CS4231_LOOPBACK]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) snd_wss_dout(chip, CS4231_LEFT_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) snd_wss_dout(chip, CS4231_RIGHT_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) snd_wss_dout(chip, CS4231_LOOPBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 0xfd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) snd_wss_dout(chip, CS4231_AUX1_LEFT_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) mute | chip->image[CS4231_AUX1_LEFT_INPUT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) snd_wss_dout(chip, CS4231_AUX1_RIGHT_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) mute | chip->image[CS4231_AUX1_RIGHT_INPUT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) snd_wss_dout(chip, CS4231_AUX2_LEFT_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) mute | chip->image[CS4231_AUX2_LEFT_INPUT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) snd_wss_dout(chip, CS4231_AUX2_RIGHT_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) mute | chip->image[CS4231_AUX2_RIGHT_INPUT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) snd_wss_dout(chip, CS4231_LEFT_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) mute | chip->image[CS4231_LEFT_OUTPUT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) snd_wss_dout(chip, CS4231_RIGHT_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) mute | chip->image[CS4231_RIGHT_OUTPUT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (!(chip->hardware & WSS_HW_AD1848_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) snd_wss_dout(chip, CS4231_LEFT_LINE_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) mute | chip->image[CS4231_LEFT_LINE_IN]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) snd_wss_dout(chip, CS4231_RIGHT_LINE_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) mute | chip->image[CS4231_RIGHT_LINE_IN]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) snd_wss_dout(chip, CS4231_MONO_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) mute ? 0xc0 : chip->image[CS4231_MONO_CTRL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (chip->hardware == WSS_HW_INTERWAVE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) snd_wss_dout(chip, CS4231_LEFT_MIC_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) mute | chip->image[CS4231_LEFT_MIC_INPUT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) snd_wss_dout(chip, CS4231_RIGHT_MIC_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) mute | chip->image[CS4231_RIGHT_MIC_INPUT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) snd_wss_dout(chip, CS4231_LINE_LEFT_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) mute | chip->image[CS4231_LINE_LEFT_OUTPUT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) snd_wss_dout(chip, CS4231_LINE_RIGHT_OUTPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) mute | chip->image[CS4231_LINE_RIGHT_OUTPUT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) chip->calibrate_mute = mute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static void snd_wss_playback_format(struct snd_wss *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) unsigned char pdfr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) int full_calib = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) mutex_lock(&chip->mce_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (chip->hardware == WSS_HW_CS4231A ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) (chip->hardware & WSS_HW_CS4232_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if ((chip->image[CS4231_PLAYBK_FORMAT] & 0x0f) == (pdfr & 0x0f)) { /* rate is same? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) snd_wss_out(chip, CS4231_ALT_FEATURE_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) chip->image[CS4231_ALT_FEATURE_1] | 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) chip->image[CS4231_PLAYBK_FORMAT] = pdfr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) snd_wss_out(chip, CS4231_PLAYBK_FORMAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) chip->image[CS4231_PLAYBK_FORMAT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) snd_wss_out(chip, CS4231_ALT_FEATURE_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) chip->image[CS4231_ALT_FEATURE_1] &= ~0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) udelay(100); /* Fixes audible clicks at least on GUS MAX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) full_calib = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) } else if (chip->hardware == WSS_HW_AD1845) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) unsigned rate = params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * Program the AD1845 correctly for the playback stream.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * Note that we do NOT need to toggle the MCE bit because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * the PLAYBACK_ENABLE bit of the Interface Configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * register is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * NOTE: We seem to need to write to the MSB before the LSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * to get the correct sample frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) snd_wss_out(chip, CS4231_PLAYBK_FORMAT, (pdfr & 0xf0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) snd_wss_out(chip, AD1845_UPR_FREQ_SEL, (rate >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) snd_wss_out(chip, AD1845_LWR_FREQ_SEL, rate & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) full_calib = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (full_calib) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) snd_wss_mce_up(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (chip->hardware != WSS_HW_INTERWAVE && !chip->single_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) pdfr = (pdfr & 0xf0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) (chip->image[CS4231_REC_FORMAT] & 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) chip->image[CS4231_PLAYBK_FORMAT] = pdfr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) snd_wss_out(chip, CS4231_PLAYBK_FORMAT, pdfr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (chip->hardware == WSS_HW_OPL3SA2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) udelay(100); /* this seems to help */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) snd_wss_mce_down(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) mutex_unlock(&chip->mce_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static void snd_wss_capture_format(struct snd_wss *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) unsigned char cdfr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) int full_calib = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) mutex_lock(&chip->mce_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (chip->hardware == WSS_HW_CS4231A ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) (chip->hardware & WSS_HW_CS4232_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if ((chip->image[CS4231_PLAYBK_FORMAT] & 0x0f) == (cdfr & 0x0f) || /* rate is same? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) (chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) snd_wss_out(chip, CS4231_ALT_FEATURE_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) chip->image[CS4231_ALT_FEATURE_1] | 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) snd_wss_out(chip, CS4231_REC_FORMAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) chip->image[CS4231_REC_FORMAT] = cdfr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) snd_wss_out(chip, CS4231_ALT_FEATURE_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) chip->image[CS4231_ALT_FEATURE_1] &= ~0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) full_calib = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) } else if (chip->hardware == WSS_HW_AD1845) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) unsigned rate = params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * Program the AD1845 correctly for the capture stream.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) * Note that we do NOT need to toggle the MCE bit because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) * the PLAYBACK_ENABLE bit of the Interface Configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) * register is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * NOTE: We seem to need to write to the MSB before the LSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * to get the correct sample frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) snd_wss_out(chip, CS4231_REC_FORMAT, (cdfr & 0xf0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) snd_wss_out(chip, AD1845_UPR_FREQ_SEL, (rate >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) snd_wss_out(chip, AD1845_LWR_FREQ_SEL, rate & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) full_calib = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (full_calib) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) snd_wss_mce_up(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (chip->hardware != WSS_HW_INTERWAVE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) !(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (chip->single_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) snd_wss_out(chip, CS4231_PLAYBK_FORMAT, cdfr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) snd_wss_out(chip, CS4231_PLAYBK_FORMAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) (chip->image[CS4231_PLAYBK_FORMAT] & 0xf0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) (cdfr & 0x0f));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) snd_wss_mce_down(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) snd_wss_mce_up(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (chip->hardware & WSS_HW_AD1848_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) snd_wss_out(chip, CS4231_PLAYBK_FORMAT, cdfr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) snd_wss_out(chip, CS4231_REC_FORMAT, cdfr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) snd_wss_mce_down(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) mutex_unlock(&chip->mce_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) * Timer interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) static unsigned long snd_wss_timer_resolution(struct snd_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) struct snd_wss *chip = snd_timer_chip(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (chip->hardware & WSS_HW_CS4236B_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) return 14467;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) return chip->image[CS4231_PLAYBK_FORMAT] & 1 ? 9969 : 9920;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) static int snd_wss_timer_start(struct snd_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) unsigned int ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) struct snd_wss *chip = snd_timer_chip(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) ticks = timer->sticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if ((chip->image[CS4231_ALT_FEATURE_1] & CS4231_TIMER_ENABLE) == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) (unsigned char)(ticks >> 8) != chip->image[CS4231_TIMER_HIGH] ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) (unsigned char)ticks != chip->image[CS4231_TIMER_LOW]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) chip->image[CS4231_TIMER_HIGH] = (unsigned char) (ticks >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) snd_wss_out(chip, CS4231_TIMER_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) chip->image[CS4231_TIMER_HIGH]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) chip->image[CS4231_TIMER_LOW] = (unsigned char) ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) snd_wss_out(chip, CS4231_TIMER_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) chip->image[CS4231_TIMER_LOW]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) snd_wss_out(chip, CS4231_ALT_FEATURE_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) chip->image[CS4231_ALT_FEATURE_1] |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) CS4231_TIMER_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) static int snd_wss_timer_stop(struct snd_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) struct snd_wss *chip = snd_timer_chip(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) chip->image[CS4231_ALT_FEATURE_1] &= ~CS4231_TIMER_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) snd_wss_out(chip, CS4231_ALT_FEATURE_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) chip->image[CS4231_ALT_FEATURE_1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static void snd_wss_init(struct snd_wss *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) snd_wss_calibrate_mute(chip, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) snd_wss_mce_down(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #ifdef SNDRV_DEBUG_MCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) snd_printk(KERN_DEBUG "init: (1)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) snd_wss_mce_up(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) CS4231_PLAYBACK_PIO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) CS4231_RECORD_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) CS4231_RECORD_PIO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) CS4231_CALIB_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) chip->image[CS4231_IFACE_CTRL] |= CS4231_AUTOCALIB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) snd_wss_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) snd_wss_mce_down(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #ifdef SNDRV_DEBUG_MCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) snd_printk(KERN_DEBUG "init: (2)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) snd_wss_mce_up(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) chip->image[CS4231_IFACE_CTRL] &= ~CS4231_AUTOCALIB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) snd_wss_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) snd_wss_out(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) snd_wss_mce_down(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #ifdef SNDRV_DEBUG_MCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) snd_printk(KERN_DEBUG "init: (3) - afei = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) chip->image[CS4231_ALT_FEATURE_1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) snd_wss_out(chip, CS4231_ALT_FEATURE_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) chip->image[CS4231_ALT_FEATURE_2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) snd_wss_mce_up(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) snd_wss_out(chip, CS4231_PLAYBK_FORMAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) chip->image[CS4231_PLAYBK_FORMAT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) snd_wss_mce_down(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #ifdef SNDRV_DEBUG_MCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) snd_printk(KERN_DEBUG "init: (4)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) snd_wss_mce_up(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (!(chip->hardware & WSS_HW_AD1848_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) snd_wss_out(chip, CS4231_REC_FORMAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) chip->image[CS4231_REC_FORMAT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) snd_wss_mce_down(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) snd_wss_calibrate_mute(chip, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #ifdef SNDRV_DEBUG_MCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) snd_printk(KERN_DEBUG "init: (5)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) static int snd_wss_open(struct snd_wss *chip, unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) mutex_lock(&chip->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) if ((chip->mode & mode) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) ((chip->mode & WSS_MODE_OPEN) && chip->single_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) mutex_unlock(&chip->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if (chip->mode & WSS_MODE_OPEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) chip->mode |= mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) mutex_unlock(&chip->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) /* ok. now enable and ack CODEC IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (!(chip->hardware & WSS_HW_AD1848_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) snd_wss_out(chip, CS4231_IRQ_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) CS4231_PLAYBACK_IRQ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) CS4231_RECORD_IRQ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) CS4231_TIMER_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) snd_wss_out(chip, CS4231_IRQ_STATUS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) chip->image[CS4231_PIN_CTRL] |= CS4231_IRQ_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) snd_wss_out(chip, CS4231_PIN_CTRL, chip->image[CS4231_PIN_CTRL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (!(chip->hardware & WSS_HW_AD1848_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) snd_wss_out(chip, CS4231_IRQ_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) CS4231_PLAYBACK_IRQ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) CS4231_RECORD_IRQ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) CS4231_TIMER_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) snd_wss_out(chip, CS4231_IRQ_STATUS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) chip->mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) mutex_unlock(&chip->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) static void snd_wss_close(struct snd_wss *chip, unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) mutex_lock(&chip->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) chip->mode &= ~mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (chip->mode & WSS_MODE_OPEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) mutex_unlock(&chip->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) /* disable IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if (!(chip->hardware & WSS_HW_AD1848_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) snd_wss_out(chip, CS4231_IRQ_STATUS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) chip->image[CS4231_PIN_CTRL] &= ~CS4231_IRQ_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) snd_wss_out(chip, CS4231_PIN_CTRL, chip->image[CS4231_PIN_CTRL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) /* now disable record & playback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (chip->image[CS4231_IFACE_CTRL] & (CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) CS4231_RECORD_ENABLE | CS4231_RECORD_PIO)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) snd_wss_mce_up(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) snd_wss_out(chip, CS4231_IFACE_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) chip->image[CS4231_IFACE_CTRL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) snd_wss_mce_down(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) /* clear IRQ again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) if (!(chip->hardware & WSS_HW_AD1848_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) snd_wss_out(chip, CS4231_IRQ_STATUS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) chip->mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) mutex_unlock(&chip->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) * timer open/close
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) static int snd_wss_timer_open(struct snd_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) struct snd_wss *chip = snd_timer_chip(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) snd_wss_open(chip, WSS_MODE_TIMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) static int snd_wss_timer_close(struct snd_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) struct snd_wss *chip = snd_timer_chip(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) snd_wss_close(chip, WSS_MODE_TIMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) static const struct snd_timer_hardware snd_wss_timer_table =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .flags = SNDRV_TIMER_HW_AUTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .resolution = 9945,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .ticks = 65535,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .open = snd_wss_timer_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .close = snd_wss_timer_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .c_resolution = snd_wss_timer_resolution,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .start = snd_wss_timer_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .stop = snd_wss_timer_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) * ok.. exported functions..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) static int snd_wss_playback_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) struct snd_pcm_hw_params *hw_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) struct snd_wss *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) unsigned char new_pdfr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) new_pdfr = snd_wss_get_format(chip, params_format(hw_params),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) params_channels(hw_params)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) snd_wss_get_rate(params_rate(hw_params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) chip->set_playback_format(chip, hw_params, new_pdfr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) static int snd_wss_playback_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) struct snd_wss *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) unsigned int size = snd_pcm_lib_buffer_bytes(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) unsigned int count = snd_pcm_lib_period_bytes(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) chip->p_dma_size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) snd_dma_program(chip->dma1, runtime->dma_addr, size, DMA_MODE_WRITE | DMA_AUTOINIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) count = snd_wss_get_count(chip->image[CS4231_PLAYBK_FORMAT], count) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) snd_wss_out(chip, CS4231_PLY_LWR_CNT, (unsigned char) count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) snd_wss_out(chip, CS4231_PLY_UPR_CNT, (unsigned char) (count >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) snd_wss_debug(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) static int snd_wss_capture_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) struct snd_pcm_hw_params *hw_params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) struct snd_wss *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) unsigned char new_cdfr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) new_cdfr = snd_wss_get_format(chip, params_format(hw_params),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) params_channels(hw_params)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) snd_wss_get_rate(params_rate(hw_params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) chip->set_capture_format(chip, hw_params, new_cdfr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) static int snd_wss_capture_prepare(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) struct snd_wss *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) unsigned int size = snd_pcm_lib_buffer_bytes(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) unsigned int count = snd_pcm_lib_period_bytes(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) chip->c_dma_size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) snd_dma_program(chip->dma2, runtime->dma_addr, size, DMA_MODE_READ | DMA_AUTOINIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) if (chip->hardware & WSS_HW_AD1848_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) count = snd_wss_get_count(chip->image[CS4231_PLAYBK_FORMAT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) count = snd_wss_get_count(chip->image[CS4231_REC_FORMAT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) if (chip->single_dma && chip->hardware != WSS_HW_INTERWAVE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) snd_wss_out(chip, CS4231_PLY_LWR_CNT, (unsigned char) count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) snd_wss_out(chip, CS4231_PLY_UPR_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) (unsigned char) (count >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) snd_wss_out(chip, CS4231_REC_LWR_CNT, (unsigned char) count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) snd_wss_out(chip, CS4231_REC_UPR_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) (unsigned char) (count >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) void snd_wss_overrange(struct snd_wss *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) unsigned char res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) res = snd_wss_in(chip, CS4231_TEST_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) if (res & (0x08 | 0x02)) /* detect overrange only above 0dB; may be user selectable? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) chip->capture_substream->runtime->overrange++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) EXPORT_SYMBOL(snd_wss_overrange);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) irqreturn_t snd_wss_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) struct snd_wss *chip = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) unsigned char status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) if (chip->hardware & WSS_HW_AD1848_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) /* pretend it was the only possible irq for AD1848 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) status = CS4231_PLAYBACK_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) status = snd_wss_in(chip, CS4231_IRQ_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) if (status & CS4231_TIMER_IRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) if (chip->timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) snd_timer_interrupt(chip->timer, chip->timer->sticks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if (chip->single_dma && chip->hardware != WSS_HW_INTERWAVE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) if (status & CS4231_PLAYBACK_IRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) if (chip->mode & WSS_MODE_PLAY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) if (chip->playback_substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) snd_pcm_period_elapsed(chip->playback_substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) if (chip->mode & WSS_MODE_RECORD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) if (chip->capture_substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) snd_wss_overrange(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) snd_pcm_period_elapsed(chip->capture_substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) if (status & CS4231_PLAYBACK_IRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) if (chip->playback_substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) snd_pcm_period_elapsed(chip->playback_substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) if (status & CS4231_RECORD_IRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) if (chip->capture_substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) snd_wss_overrange(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) snd_pcm_period_elapsed(chip->capture_substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) spin_lock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) status = ~CS4231_ALL_IRQS | ~status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) if (chip->hardware & WSS_HW_AD1848_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) wss_outb(chip, CS4231P(STATUS), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) snd_wss_out(chip, CS4231_IRQ_STATUS, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) spin_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) EXPORT_SYMBOL(snd_wss_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) static snd_pcm_uframes_t snd_wss_playback_pointer(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) struct snd_wss *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) size_t ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) ptr = snd_dma_pointer(chip->dma1, chip->p_dma_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) return bytes_to_frames(substream->runtime, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) static snd_pcm_uframes_t snd_wss_capture_pointer(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) struct snd_wss *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) size_t ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) ptr = snd_dma_pointer(chip->dma2, chip->c_dma_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) return bytes_to_frames(substream->runtime, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) static int snd_ad1848_probe(struct snd_wss *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) unsigned long timeout = jiffies + msecs_to_jiffies(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) unsigned char r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) unsigned short hardware = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) while (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) if (time_after(jiffies, timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) cond_resched();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) /* set CS423x MODE 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) snd_wss_dout(chip, CS4231_MISC_INFO, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) snd_wss_dout(chip, CS4231_RIGHT_INPUT, 0x45); /* 0x55 & ~0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) r = snd_wss_in(chip, CS4231_RIGHT_INPUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) if (r != 0x45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) /* RMGE always high on AD1847 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) if ((r & ~CS4231_ENABLE_MIC_GAIN) != 0x45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) hardware = WSS_HW_AD1847;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) snd_wss_dout(chip, CS4231_LEFT_INPUT, 0xaa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) r = snd_wss_in(chip, CS4231_LEFT_INPUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) /* L/RMGE always low on AT2320 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) if ((r | CS4231_ENABLE_MIC_GAIN) != 0xaa) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) /* clear pending IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) wss_inb(chip, CS4231P(STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) wss_outb(chip, CS4231P(STATUS), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) if ((chip->hardware & WSS_HW_TYPE_MASK) != WSS_HW_DETECT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) if (hardware) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) chip->hardware = hardware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) r = snd_wss_in(chip, CS4231_MISC_INFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) /* set CS423x MODE 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) snd_wss_dout(chip, CS4231_MISC_INFO, CS4231_MODE2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) for (i = 0; i < 16; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) if (snd_wss_in(chip, i) != snd_wss_in(chip, 16 + i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) /* we have more than 16 registers: check ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) if ((r & 0xf) != 0xa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) goto out_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) * on CMI8330, CS4231_VERSION is volume control and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) * can be set to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) snd_wss_dout(chip, CS4231_VERSION, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) r = snd_wss_in(chip, CS4231_VERSION) & 0xe7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) if (!r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) chip->hardware = WSS_HW_CMI8330;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) goto out_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) if (r & 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) chip->hardware = WSS_HW_CS4248;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) chip->hardware = WSS_HW_AD1848;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) out_mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) snd_wss_dout(chip, CS4231_MISC_INFO, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) static int snd_wss_probe(struct snd_wss *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) int i, id, rev, regnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) unsigned char *ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) unsigned int hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) id = snd_ad1848_probe(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) if (id < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) return id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) hw = chip->hardware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) if ((hw & WSS_HW_TYPE_MASK) == WSS_HW_DETECT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) for (i = 0; i < 50; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) msleep(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) snd_wss_out(chip, CS4231_MISC_INFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) CS4231_MODE2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) id = snd_wss_in(chip, CS4231_MISC_INFO) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) if (id == 0x0a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) break; /* this is valid value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) snd_printdd("wss: port = 0x%lx, id = 0x%x\n", chip->port, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) if (id != 0x0a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) return -ENODEV; /* no valid device found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) rev = snd_wss_in(chip, CS4231_VERSION) & 0xe7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) snd_printdd("CS4231: VERSION (I25) = 0x%x\n", rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) if (rev == 0x80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) unsigned char tmp = snd_wss_in(chip, 23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) snd_wss_out(chip, 23, ~tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) if (snd_wss_in(chip, 23) != tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) chip->hardware = WSS_HW_AD1845;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) chip->hardware = WSS_HW_CS4231;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) } else if (rev == 0xa0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) chip->hardware = WSS_HW_CS4231A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) } else if (rev == 0xa2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) chip->hardware = WSS_HW_CS4232;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) } else if (rev == 0xb2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) chip->hardware = WSS_HW_CS4232A;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) } else if (rev == 0x83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) chip->hardware = WSS_HW_CS4236;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) } else if (rev == 0x03) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) chip->hardware = WSS_HW_CS4236B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) snd_printk(KERN_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) "unknown CS chip with version 0x%x\n", rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) return -ENODEV; /* unknown CS4231 chip? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) wss_inb(chip, CS4231P(STATUS)); /* clear any pendings IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) wss_outb(chip, CS4231P(STATUS), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) if (!(chip->hardware & WSS_HW_AD1848_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) chip->image[CS4231_MISC_INFO] = CS4231_MODE2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) switch (chip->hardware) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) case WSS_HW_INTERWAVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) chip->image[CS4231_MISC_INFO] = CS4231_IW_MODE3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) case WSS_HW_CS4235:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) case WSS_HW_CS4236B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) case WSS_HW_CS4237B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) case WSS_HW_CS4238B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) case WSS_HW_CS4239:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) if (hw == WSS_HW_DETECT3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) chip->image[CS4231_MISC_INFO] = CS4231_4236_MODE3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) chip->hardware = WSS_HW_CS4236;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) chip->image[CS4231_IFACE_CTRL] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) (chip->image[CS4231_IFACE_CTRL] & ~CS4231_SINGLE_DMA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) (chip->single_dma ? CS4231_SINGLE_DMA : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) if (chip->hardware != WSS_HW_OPTI93X) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) chip->image[CS4231_ALT_FEATURE_1] = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) chip->image[CS4231_ALT_FEATURE_2] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) chip->hardware == WSS_HW_INTERWAVE ? 0xc2 : 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) /* enable fine grained frequency selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) if (chip->hardware == WSS_HW_AD1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) chip->image[AD1845_PWR_DOWN] = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) ptr = (unsigned char *) &chip->image;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) regnum = (chip->hardware & WSS_HW_AD1848_MASK) ? 16 : 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) snd_wss_mce_down(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) for (i = 0; i < regnum; i++) /* ok.. fill all registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) snd_wss_out(chip, i, *ptr++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) snd_wss_mce_up(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) snd_wss_mce_down(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) mdelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) /* ok.. try check hardware version for CS4236+ chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) if ((hw & WSS_HW_TYPE_MASK) == WSS_HW_DETECT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) if (chip->hardware == WSS_HW_CS4236B) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) rev = snd_cs4236_ext_in(chip, CS4236_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) snd_cs4236_ext_out(chip, CS4236_VERSION, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) id = snd_cs4236_ext_in(chip, CS4236_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) snd_cs4236_ext_out(chip, CS4236_VERSION, rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) snd_printdd("CS4231: ext version; rev = 0x%x, id = 0x%x\n", rev, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) if ((id & 0x1f) == 0x1d) { /* CS4235 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) chip->hardware = WSS_HW_CS4235;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) switch (id >> 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) snd_printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) "unknown CS4235 chip "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) "(enhanced version = 0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) } else if ((id & 0x1f) == 0x0b) { /* CS4236/B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) switch (id >> 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) chip->hardware = WSS_HW_CS4236B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) snd_printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) "unknown CS4236 chip "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) "(enhanced version = 0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) } else if ((id & 0x1f) == 0x08) { /* CS4237B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) chip->hardware = WSS_HW_CS4237B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) switch (id >> 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) snd_printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) "unknown CS4237B chip "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) "(enhanced version = 0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) } else if ((id & 0x1f) == 0x09) { /* CS4238B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) chip->hardware = WSS_HW_CS4238B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) switch (id >> 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) snd_printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) "unknown CS4238B chip "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) "(enhanced version = 0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) } else if ((id & 0x1f) == 0x1e) { /* CS4239 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) chip->hardware = WSS_HW_CS4239;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) switch (id >> 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) snd_printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) "unknown CS4239 chip "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) "(enhanced version = 0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) snd_printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) "unknown CS4236/CS423xB chip "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) "(enhanced version = 0x%x)\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) return 0; /* all things are ok.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) static const struct snd_pcm_hardware snd_wss_playback =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) SNDRV_PCM_INFO_SYNC_START),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW | SNDRV_PCM_FMTBIT_IMA_ADPCM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) .rate_min = 5510,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) .buffer_bytes_max = (128*1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) .period_bytes_min = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) .period_bytes_max = (128*1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) .periods_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) .periods_max = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) .fifo_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) static const struct snd_pcm_hardware snd_wss_capture =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) SNDRV_PCM_INFO_MMAP_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) SNDRV_PCM_INFO_RESUME |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) SNDRV_PCM_INFO_SYNC_START),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW | SNDRV_PCM_FMTBIT_IMA_ADPCM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) .rate_min = 5510,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) .rate_max = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) .channels_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) .channels_max = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) .buffer_bytes_max = (128*1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) .period_bytes_min = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) .period_bytes_max = (128*1024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) .periods_min = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) .periods_max = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) .fifo_size = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) static int snd_wss_playback_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) struct snd_wss *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) runtime->hw = snd_wss_playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) /* hardware limitation of older chipsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) if (chip->hardware & WSS_HW_AD1848_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) runtime->hw.formats &= ~(SNDRV_PCM_FMTBIT_IMA_ADPCM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) SNDRV_PCM_FMTBIT_S16_BE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) /* hardware bug in InterWave chipset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) if (chip->hardware == WSS_HW_INTERWAVE && chip->dma1 > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) runtime->hw.formats &= ~SNDRV_PCM_FMTBIT_MU_LAW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) /* hardware limitation of cheap chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) if (chip->hardware == WSS_HW_CS4235 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) chip->hardware == WSS_HW_CS4239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) runtime->hw.formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) snd_pcm_limit_isa_dma_size(chip->dma1, &runtime->hw.buffer_bytes_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) snd_pcm_limit_isa_dma_size(chip->dma1, &runtime->hw.period_bytes_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) if (chip->claim_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) if ((err = chip->claim_dma(chip, chip->dma_private_data, chip->dma1)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) err = snd_wss_open(chip, WSS_MODE_PLAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) if (chip->release_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) chip->release_dma(chip, chip->dma_private_data, chip->dma1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) chip->playback_substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) snd_pcm_set_sync(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) chip->rate_constraint(runtime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) static int snd_wss_capture_open(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) struct snd_wss *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) runtime->hw = snd_wss_capture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) /* hardware limitation of older chipsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) if (chip->hardware & WSS_HW_AD1848_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) runtime->hw.formats &= ~(SNDRV_PCM_FMTBIT_IMA_ADPCM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) SNDRV_PCM_FMTBIT_S16_BE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) /* hardware limitation of cheap chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) if (chip->hardware == WSS_HW_CS4235 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) chip->hardware == WSS_HW_CS4239 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) chip->hardware == WSS_HW_OPTI93X)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) runtime->hw.formats = SNDRV_PCM_FMTBIT_U8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) SNDRV_PCM_FMTBIT_S16_LE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) snd_pcm_limit_isa_dma_size(chip->dma2, &runtime->hw.buffer_bytes_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) snd_pcm_limit_isa_dma_size(chip->dma2, &runtime->hw.period_bytes_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) if (chip->claim_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) if ((err = chip->claim_dma(chip, chip->dma_private_data, chip->dma2)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) err = snd_wss_open(chip, WSS_MODE_RECORD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) if (chip->release_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) chip->release_dma(chip, chip->dma_private_data, chip->dma2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) chip->capture_substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) snd_pcm_set_sync(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) chip->rate_constraint(runtime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) static int snd_wss_playback_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) struct snd_wss *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) chip->playback_substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) snd_wss_close(chip, WSS_MODE_PLAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) static int snd_wss_capture_close(struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) struct snd_wss *chip = snd_pcm_substream_chip(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) chip->capture_substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) snd_wss_close(chip, WSS_MODE_RECORD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) static void snd_wss_thinkpad_twiddle(struct snd_wss *chip, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) if (!chip->thinkpad_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) outb(0x1c, AD1848_THINKPAD_CTL_PORT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) tmp = inb(AD1848_THINKPAD_CTL_PORT2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) /* turn it on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) tmp |= AD1848_THINKPAD_CS4248_ENABLE_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) /* turn it off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) tmp &= ~AD1848_THINKPAD_CS4248_ENABLE_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) outb(tmp, AD1848_THINKPAD_CTL_PORT2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) /* lowlevel suspend callback for CS4231 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) static void snd_wss_suspend(struct snd_wss *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) for (reg = 0; reg < 32; reg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) chip->image[reg] = snd_wss_in(chip, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) if (chip->thinkpad_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) snd_wss_thinkpad_twiddle(chip, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) /* lowlevel resume callback for CS4231 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) static void snd_wss_resume(struct snd_wss *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) /* int timeout; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) if (chip->thinkpad_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) snd_wss_thinkpad_twiddle(chip, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) snd_wss_mce_up(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) for (reg = 0; reg < 32; reg++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) case CS4231_VERSION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) snd_wss_out(chip, reg, chip->image[reg]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) /* Yamaha needs this to resume properly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) if (chip->hardware == WSS_HW_OPL3SA2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) snd_wss_out(chip, CS4231_PLAYBK_FORMAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) chip->image[CS4231_PLAYBK_FORMAT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) #if 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) snd_wss_mce_down(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) /* The following is a workaround to avoid freeze after resume on TP600E.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) This is the first half of copy of snd_wss_mce_down(), but doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) include rescheduling. -- iwai
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) snd_wss_busy_wait(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) chip->mce_bit &= ~CS4231_MCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) timeout = wss_inb(chip, CS4231P(REGSEL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) if (timeout == 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) snd_printk(KERN_ERR "down [0x%lx]: serious init problem "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) "- codec still busy\n", chip->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) if ((timeout & CS4231_MCE) == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) !(chip->hardware & (WSS_HW_CS4231_MASK | WSS_HW_CS4232_MASK))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) snd_wss_busy_wait(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) static int snd_wss_free(struct snd_wss *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) release_and_free_resource(chip->res_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) release_and_free_resource(chip->res_cport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) if (chip->irq >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) disable_irq(chip->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) if (!(chip->hwshare & WSS_HWSHARE_IRQ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) free_irq(chip->irq, (void *) chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) if (!(chip->hwshare & WSS_HWSHARE_DMA1) && chip->dma1 >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) snd_dma_disable(chip->dma1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) free_dma(chip->dma1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) if (!(chip->hwshare & WSS_HWSHARE_DMA2) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) chip->dma2 >= 0 && chip->dma2 != chip->dma1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) snd_dma_disable(chip->dma2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) free_dma(chip->dma2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) if (chip->timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) snd_device_free(chip->card, chip->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) kfree(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) static int snd_wss_dev_free(struct snd_device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) struct snd_wss *chip = device->device_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) return snd_wss_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) const char *snd_wss_chip_id(struct snd_wss *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) switch (chip->hardware) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) case WSS_HW_CS4231:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) return "CS4231";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) case WSS_HW_CS4231A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) return "CS4231A";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) case WSS_HW_CS4232:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) return "CS4232";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) case WSS_HW_CS4232A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) return "CS4232A";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) case WSS_HW_CS4235:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) return "CS4235";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) case WSS_HW_CS4236:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) return "CS4236";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) case WSS_HW_CS4236B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) return "CS4236B";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) case WSS_HW_CS4237B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) return "CS4237B";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) case WSS_HW_CS4238B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) return "CS4238B";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) case WSS_HW_CS4239:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) return "CS4239";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) case WSS_HW_INTERWAVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) return "AMD InterWave";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) case WSS_HW_OPL3SA2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) return chip->card->shortname;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) case WSS_HW_AD1845:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) return "AD1845";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) case WSS_HW_OPTI93X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) return "OPTi 93x";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) case WSS_HW_AD1847:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) return "AD1847";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) case WSS_HW_AD1848:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) return "AD1848";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) case WSS_HW_CS4248:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) return "CS4248";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) case WSS_HW_CMI8330:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) return "CMI8330/C3D";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) return "???";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) EXPORT_SYMBOL(snd_wss_chip_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) static int snd_wss_new(struct snd_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) unsigned short hardware,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) unsigned short hwshare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) struct snd_wss **rchip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) struct snd_wss *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) *rchip = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) chip = kzalloc(sizeof(*chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) if (chip == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) chip->hardware = hardware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) chip->hwshare = hwshare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) spin_lock_init(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) mutex_init(&chip->mce_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) mutex_init(&chip->open_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) chip->card = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) chip->rate_constraint = snd_wss_xrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) chip->set_playback_format = snd_wss_playback_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) chip->set_capture_format = snd_wss_capture_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) if (chip->hardware == WSS_HW_OPTI93X)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) memcpy(&chip->image, &snd_opti93x_original_image,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) sizeof(snd_opti93x_original_image));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) memcpy(&chip->image, &snd_wss_original_image,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) sizeof(snd_wss_original_image));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) if (chip->hardware & WSS_HW_AD1848_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) chip->image[CS4231_PIN_CTRL] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) chip->image[CS4231_TEST_INIT] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) *rchip = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) int snd_wss_create(struct snd_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) unsigned long port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) unsigned long cport,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) int irq, int dma1, int dma2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) unsigned short hardware,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) unsigned short hwshare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) struct snd_wss **rchip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) static const struct snd_device_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) .dev_free = snd_wss_dev_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) struct snd_wss *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) err = snd_wss_new(card, hardware, hwshare, &chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) chip->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) chip->dma1 = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) chip->dma2 = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) chip->res_port = request_region(port, 4, "WSS");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) if (!chip->res_port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) snd_printk(KERN_ERR "wss: can't grab port 0x%lx\n", port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) snd_wss_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) chip->port = port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) if ((long)cport >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) chip->res_cport = request_region(cport, 8, "CS4232 Control");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) if (!chip->res_cport) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) snd_printk(KERN_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) "wss: can't grab control port 0x%lx\n", cport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) snd_wss_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) chip->cport = cport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) if (!(hwshare & WSS_HWSHARE_IRQ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) if (request_irq(irq, snd_wss_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) "WSS", (void *) chip)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) snd_printk(KERN_ERR "wss: can't grab IRQ %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) snd_wss_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) chip->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) card->sync_irq = chip->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) if (!(hwshare & WSS_HWSHARE_DMA1) && request_dma(dma1, "WSS - 1")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) snd_printk(KERN_ERR "wss: can't grab DMA1 %d\n", dma1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) snd_wss_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) chip->dma1 = dma1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) if (!(hwshare & WSS_HWSHARE_DMA2) && dma1 != dma2 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) dma2 >= 0 && request_dma(dma2, "WSS - 2")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) snd_printk(KERN_ERR "wss: can't grab DMA2 %d\n", dma2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) snd_wss_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) if (dma1 == dma2 || dma2 < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) chip->single_dma = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) chip->dma2 = chip->dma1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) chip->dma2 = dma2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) if (hardware == WSS_HW_THINKPAD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) chip->thinkpad_flag = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) chip->hardware = WSS_HW_DETECT; /* reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) snd_wss_thinkpad_twiddle(chip, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) /* global setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) if (snd_wss_probe(chip) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) snd_wss_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) snd_wss_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) if (chip->hardware & WSS_HW_CS4232_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) if (chip->res_cport == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) snd_printk(KERN_ERR "CS4232 control port features are "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) "not accessible\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) /* Register device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) snd_wss_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) /* Power Management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) chip->suspend = snd_wss_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) chip->resume = snd_wss_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) *rchip = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) EXPORT_SYMBOL(snd_wss_create);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) static const struct snd_pcm_ops snd_wss_playback_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) .open = snd_wss_playback_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) .close = snd_wss_playback_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) .hw_params = snd_wss_playback_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) .prepare = snd_wss_playback_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) .trigger = snd_wss_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) .pointer = snd_wss_playback_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) static const struct snd_pcm_ops snd_wss_capture_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) .open = snd_wss_capture_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) .close = snd_wss_capture_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) .hw_params = snd_wss_capture_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) .prepare = snd_wss_capture_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) .trigger = snd_wss_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) .pointer = snd_wss_capture_pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) int snd_wss_pcm(struct snd_wss *chip, int device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) err = snd_pcm_new(chip->card, "WSS", device, 1, 1, &pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_wss_playback_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_wss_capture_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) /* global setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) pcm->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) pcm->info_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) if (chip->single_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) pcm->info_flags |= SNDRV_PCM_INFO_HALF_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) if (chip->hardware != WSS_HW_INTERWAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) pcm->info_flags |= SNDRV_PCM_INFO_JOINT_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) strcpy(pcm->name, snd_wss_chip_id(chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, chip->card->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) 64*1024, chip->dma1 > 3 || chip->dma2 > 3 ? 128*1024 : 64*1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) chip->pcm = pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) EXPORT_SYMBOL(snd_wss_pcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) static void snd_wss_timer_free(struct snd_timer *timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) struct snd_wss *chip = timer->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) chip->timer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) int snd_wss_timer(struct snd_wss *chip, int device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) struct snd_timer *timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) struct snd_timer_id tid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) /* Timer initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) tid.dev_class = SNDRV_TIMER_CLASS_CARD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) tid.card = chip->card->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) tid.device = device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) tid.subdevice = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) if ((err = snd_timer_new(chip->card, "CS4231", &tid, &timer)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) strcpy(timer->name, snd_wss_chip_id(chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) timer->private_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) timer->private_free = snd_wss_timer_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) timer->hw = snd_wss_timer_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) chip->timer = timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) EXPORT_SYMBOL(snd_wss_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) * MIXER part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) static int snd_wss_info_mux(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) static const char * const texts[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) "Line", "Aux", "Mic", "Mix"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) static const char * const opl3sa_texts[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) "Line", "CD", "Mic", "Mix"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) static const char * const gusmax_texts[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) "Line", "Synth", "Mic", "Mix"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) const char * const *ptexts = texts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) if (snd_BUG_ON(!chip->card))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) if (!strcmp(chip->card->driver, "GUS MAX"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) ptexts = gusmax_texts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) switch (chip->hardware) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) case WSS_HW_INTERWAVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) ptexts = gusmax_texts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) case WSS_HW_OPTI93X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) case WSS_HW_OPL3SA2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) ptexts = opl3sa_texts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) return snd_ctl_enum_info(uinfo, 2, 4, ptexts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) static int snd_wss_get_mux(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) ucontrol->value.enumerated.item[0] = (chip->image[CS4231_LEFT_INPUT] & CS4231_MIXS_ALL) >> 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) ucontrol->value.enumerated.item[1] = (chip->image[CS4231_RIGHT_INPUT] & CS4231_MIXS_ALL) >> 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) static int snd_wss_put_mux(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) unsigned short left, right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) if (ucontrol->value.enumerated.item[0] > 3 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) ucontrol->value.enumerated.item[1] > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) left = ucontrol->value.enumerated.item[0] << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) right = ucontrol->value.enumerated.item[1] << 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) left = (chip->image[CS4231_LEFT_INPUT] & ~CS4231_MIXS_ALL) | left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) right = (chip->image[CS4231_RIGHT_INPUT] & ~CS4231_MIXS_ALL) | right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) change = left != chip->image[CS4231_LEFT_INPUT] ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) right != chip->image[CS4231_RIGHT_INPUT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) snd_wss_out(chip, CS4231_LEFT_INPUT, left);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) snd_wss_out(chip, CS4231_RIGHT_INPUT, right);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) int snd_wss_info_single(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) int mask = (kcontrol->private_value >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) uinfo->value.integer.max = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) EXPORT_SYMBOL(snd_wss_info_single);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) int snd_wss_get_single(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) int reg = kcontrol->private_value & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) int shift = (kcontrol->private_value >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) int mask = (kcontrol->private_value >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) int invert = (kcontrol->private_value >> 24) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) if (invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) EXPORT_SYMBOL(snd_wss_get_single);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) int snd_wss_put_single(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) int reg = kcontrol->private_value & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) int shift = (kcontrol->private_value >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) int mask = (kcontrol->private_value >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) int invert = (kcontrol->private_value >> 24) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) unsigned short val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) val = (ucontrol->value.integer.value[0] & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) if (invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) val = mask - val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) val <<= shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) val = (chip->image[reg] & ~(mask << shift)) | val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) change = val != chip->image[reg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) snd_wss_out(chip, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) EXPORT_SYMBOL(snd_wss_put_single);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) int snd_wss_info_double(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) int mask = (kcontrol->private_value >> 24) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) uinfo->count = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) uinfo->value.integer.max = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) EXPORT_SYMBOL(snd_wss_info_double);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) int snd_wss_get_double(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) int left_reg = kcontrol->private_value & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) int right_reg = (kcontrol->private_value >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) int shift_left = (kcontrol->private_value >> 16) & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) int shift_right = (kcontrol->private_value >> 19) & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) int mask = (kcontrol->private_value >> 24) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) int invert = (kcontrol->private_value >> 22) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) ucontrol->value.integer.value[0] = (chip->image[left_reg] >> shift_left) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) ucontrol->value.integer.value[1] = (chip->image[right_reg] >> shift_right) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) if (invert) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) EXPORT_SYMBOL(snd_wss_get_double);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) int snd_wss_put_double(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) int left_reg = kcontrol->private_value & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) int right_reg = (kcontrol->private_value >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) int shift_left = (kcontrol->private_value >> 16) & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) int shift_right = (kcontrol->private_value >> 19) & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) int mask = (kcontrol->private_value >> 24) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) int invert = (kcontrol->private_value >> 22) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) unsigned short val1, val2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) val1 = ucontrol->value.integer.value[0] & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) val2 = ucontrol->value.integer.value[1] & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) if (invert) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) val1 = mask - val1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) val2 = mask - val2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) val1 <<= shift_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) val2 <<= shift_right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) if (left_reg != right_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) change = val1 != chip->image[left_reg] ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) val2 != chip->image[right_reg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) snd_wss_out(chip, left_reg, val1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) snd_wss_out(chip, right_reg, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) mask = (mask << shift_left) | (mask << shift_right);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) val1 = (chip->image[left_reg] & ~mask) | val1 | val2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) change = val1 != chip->image[left_reg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) snd_wss_out(chip, left_reg, val1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) EXPORT_SYMBOL(snd_wss_put_double);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) static const DECLARE_TLV_DB_SCALE(db_scale_6bit, -9450, 150, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) static const DECLARE_TLV_DB_SCALE(db_scale_5bit_12db_max, -3450, 150, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) static const DECLARE_TLV_DB_SCALE(db_scale_rec_gain, 0, 150, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) static const DECLARE_TLV_DB_SCALE(db_scale_4bit, -4500, 300, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) static const struct snd_kcontrol_new snd_wss_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) WSS_DOUBLE("PCM Playback Switch", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 7, 7, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) WSS_DOUBLE_TLV("PCM Playback Volume", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 0, 0, 63, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) db_scale_6bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) WSS_DOUBLE("Aux Playback Switch", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) WSS_DOUBLE_TLV("Aux Playback Volume", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) db_scale_5bit_12db_max),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) WSS_DOUBLE("Aux Playback Switch", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) WSS_DOUBLE_TLV("Aux Playback Volume", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) db_scale_5bit_12db_max),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) WSS_DOUBLE_TLV("Capture Volume", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) 0, 0, 15, 0, db_scale_rec_gain),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) .name = "Capture Source",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) .info = snd_wss_info_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) .get = snd_wss_get_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) .put = snd_wss_put_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) WSS_DOUBLE("Mic Boost (+20dB)", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) WSS_SINGLE("Loopback Capture Switch", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) CS4231_LOOPBACK, 0, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) WSS_SINGLE_TLV("Loopback Capture Volume", 0, CS4231_LOOPBACK, 2, 63, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) db_scale_6bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) WSS_DOUBLE("Line Playback Switch", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 7, 7, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) WSS_DOUBLE_TLV("Line Playback Volume", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 0, 0, 31, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) db_scale_5bit_12db_max),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) WSS_SINGLE("Beep Playback Switch", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) CS4231_MONO_CTRL, 7, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) WSS_SINGLE_TLV("Beep Playback Volume", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) CS4231_MONO_CTRL, 0, 15, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) db_scale_4bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) WSS_SINGLE("Mono Output Playback Switch", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) CS4231_MONO_CTRL, 6, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) WSS_SINGLE("Beep Bypass Playback Switch", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) CS4231_MONO_CTRL, 5, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) int snd_wss_mixer(struct snd_wss *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) int count = ARRAY_SIZE(snd_wss_controls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) if (snd_BUG_ON(!chip || !chip->pcm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) card = chip->card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) strcpy(card->mixername, chip->pcm->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) /* Use only the first 11 entries on AD1848 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) if (chip->hardware & WSS_HW_AD1848_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) count = 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) /* There is no loopback on OPTI93X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) else if (chip->hardware == WSS_HW_OPTI93X)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) count = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) for (idx = 0; idx < count; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) err = snd_ctl_add(card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) snd_ctl_new1(&snd_wss_controls[idx],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) EXPORT_SYMBOL(snd_wss_mixer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) const struct snd_pcm_ops *snd_wss_get_pcm_ops(int direction)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) return direction == SNDRV_PCM_STREAM_PLAYBACK ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) &snd_wss_playback_ops : &snd_wss_capture_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) EXPORT_SYMBOL(snd_wss_get_pcm_ops);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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