^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) card-opti92x-ad1848.c - driver for OPTi 82c92x based soundcards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Copyright (C) 1998-2000 by Massimo Piccioni <dafastidio@libero.it>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Part of this code was developed at the Italian Ministry of Air Defence,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) Sixth Division (oh, che pace ...), Rome.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) Thanks to Maria Grazia Pollarini, Salvatore Vassallo.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/isa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pnp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <sound/tlv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <sound/wss.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <sound/mpu401.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <sound/opl3.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #ifndef OPTi93X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <sound/opl4.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SNDRV_LEGACY_FIND_FREE_IOPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SNDRV_LEGACY_FIND_FREE_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SNDRV_LEGACY_FIND_FREE_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) MODULE_AUTHOR("Massimo Piccioni <dafastidio@libero.it>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #ifdef OPTi93X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) MODULE_DESCRIPTION("OPTi93X");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) MODULE_SUPPORTED_DEVICE("{{OPTi,82C931/3}}");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #else /* OPTi93X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #ifdef CS4231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) MODULE_DESCRIPTION("OPTi92X - CS4231");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MODULE_SUPPORTED_DEVICE("{{OPTi,82C924 (CS4231)},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) "{OPTi,82C925 (CS4231)}}");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #else /* CS4231 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MODULE_DESCRIPTION("OPTi92X - AD1848");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) MODULE_SUPPORTED_DEVICE("{{OPTi,82C924 (AD1848)},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) "{OPTi,82C925 (AD1848)},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) "{OAK,Mozart}}");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #endif /* CS4231 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #endif /* OPTi93X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) //static bool enable = SNDRV_DEFAULT_ENABLE1; /* Enable this card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #ifdef CONFIG_PNP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static bool isapnp = true; /* Enable ISA PnP detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static long port = SNDRV_DEFAULT_PORT1; /* 0x530,0xe80,0xf40,0x604 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static long mpu_port = SNDRV_DEFAULT_PORT1; /* 0x300,0x310,0x320,0x330 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static long fm_port = SNDRV_DEFAULT_PORT1; /* 0x388 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static int irq = SNDRV_DEFAULT_IRQ1; /* 5,7,9,10,11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static int mpu_irq = SNDRV_DEFAULT_IRQ1; /* 5,7,9,10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static int dma1 = SNDRV_DEFAULT_DMA1; /* 0,1,3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #if defined(CS4231) || defined(OPTi93X)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static int dma2 = SNDRV_DEFAULT_DMA1; /* 0,1,3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #endif /* CS4231 || OPTi93X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) module_param(index, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) MODULE_PARM_DESC(index, "Index value for opti9xx based soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) module_param(id, charp, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) MODULE_PARM_DESC(id, "ID string for opti9xx based soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) //module_param(enable, bool, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) //MODULE_PARM_DESC(enable, "Enable opti9xx soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #ifdef CONFIG_PNP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) module_param(isapnp, bool, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MODULE_PARM_DESC(isapnp, "Enable ISA PnP detection for specified soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) module_param_hw(port, long, ioport, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MODULE_PARM_DESC(port, "WSS port # for opti9xx driver.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) module_param_hw(mpu_port, long, ioport, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MODULE_PARM_DESC(mpu_port, "MPU-401 port # for opti9xx driver.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) module_param_hw(fm_port, long, ioport, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) MODULE_PARM_DESC(fm_port, "FM port # for opti9xx driver.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) module_param_hw(irq, int, irq, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) MODULE_PARM_DESC(irq, "WSS irq # for opti9xx driver.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) module_param_hw(mpu_irq, int, irq, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MODULE_PARM_DESC(mpu_irq, "MPU-401 irq # for opti9xx driver.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) module_param_hw(dma1, int, dma, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MODULE_PARM_DESC(dma1, "1st dma # for opti9xx driver.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #if defined(CS4231) || defined(OPTi93X)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) module_param_hw(dma2, int, dma, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) MODULE_PARM_DESC(dma2, "2nd dma # for opti9xx driver.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #endif /* CS4231 || OPTi93X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define OPTi9XX_HW_82C928 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define OPTi9XX_HW_82C929 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define OPTi9XX_HW_82C924 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define OPTi9XX_HW_82C925 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define OPTi9XX_HW_82C930 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define OPTi9XX_HW_82C931 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define OPTi9XX_HW_82C933 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define OPTi9XX_HW_LAST OPTi9XX_HW_82C933
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define OPTi9XX_MC_REG(n) n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #ifdef OPTi93X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define OPTi93X_STATUS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define OPTi93X_PORT(chip, r) ((chip)->port + OPTi93X_##r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define OPTi93X_IRQ_PLAYBACK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define OPTi93X_IRQ_CAPTURE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #endif /* OPTi93X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct snd_opti9xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned short hardware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned char password;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) char name[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned long mc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct resource *res_mc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned long mc_base_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #ifdef OPTi93X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned long mc_indir_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct resource *res_mc_indir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #endif /* OPTi93X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct snd_wss *codec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned long pwd_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) long wss_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int snd_opti9xx_pnp_is_probed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #ifdef CONFIG_PNP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static const struct pnp_card_device_id snd_opti9xx_pnpids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #ifndef OPTi93X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* OPTi 82C924 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { .id = "OPT0924",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .devs = { { "OPT0000" }, { "OPT0002" }, { "OPT0005" } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .driver_data = 0x0924 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* OPTi 82C925 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) { .id = "OPT0925",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .devs = { { "OPT9250" }, { "OPT0002" }, { "OPT0005" } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .driver_data = 0x0925 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* OPTi 82C931/3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { .id = "OPT0931", .devs = { { "OPT9310" }, { "OPT0002" } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .driver_data = 0x0931 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #endif /* OPTi93X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { .id = "" }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) MODULE_DEVICE_TABLE(pnp_card, snd_opti9xx_pnpids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #endif /* CONFIG_PNP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define DEV_NAME KBUILD_MODNAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const char * const snd_opti9xx_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) "unknown",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) "82C928", "82C929",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) "82C924", "82C925",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) "82C930", "82C931", "82C933"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static int snd_opti9xx_init(struct snd_opti9xx *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) unsigned short hardware)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static const int opti9xx_mc_size[] = {7, 7, 10, 10, 2, 2, 2};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) chip->hardware = hardware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) strcpy(chip->name, snd_opti9xx_names[hardware]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) spin_lock_init(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) chip->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #ifndef OPTi93X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #ifdef CONFIG_PNP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (isapnp && chip->mc_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* PnP resource gives the least 10 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) chip->mc_base |= 0xc00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #endif /* CONFIG_PNP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) chip->mc_base = 0xf8c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) chip->mc_base_size = opti9xx_mc_size[hardware];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) chip->mc_base_size = opti9xx_mc_size[hardware];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) switch (hardware) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #ifndef OPTi93X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) case OPTi9XX_HW_82C928:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) case OPTi9XX_HW_82C929:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) chip->password = (hardware == OPTi9XX_HW_82C928) ? 0xe2 : 0xe3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) chip->pwd_reg = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) case OPTi9XX_HW_82C924:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) case OPTi9XX_HW_82C925:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) chip->password = 0xe5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) chip->pwd_reg = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #else /* OPTi93X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) case OPTi9XX_HW_82C930:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) case OPTi9XX_HW_82C931:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) case OPTi9XX_HW_82C933:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) chip->mc_base = (hardware == OPTi9XX_HW_82C930) ? 0xf8f : 0xf8d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (!chip->mc_indir_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) chip->mc_indir_index = 0xe0e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) chip->password = 0xe4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) chip->pwd_reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #endif /* OPTi93X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) snd_printk(KERN_ERR "chip %d not supported\n", hardware);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static unsigned char snd_opti9xx_read(struct snd_opti9xx *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) unsigned char reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) unsigned char retval = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) outb(chip->password, chip->mc_base + chip->pwd_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) switch (chip->hardware) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #ifndef OPTi93X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) case OPTi9XX_HW_82C924:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) case OPTi9XX_HW_82C925:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (reg > 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) outb(reg, chip->mc_base + 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) outb(chip->password, chip->mc_base + chip->pwd_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) retval = inb(chip->mc_base + 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) case OPTi9XX_HW_82C928:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) case OPTi9XX_HW_82C929:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) retval = inb(chip->mc_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #else /* OPTi93X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) case OPTi9XX_HW_82C930:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) case OPTi9XX_HW_82C931:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) case OPTi9XX_HW_82C933:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) outb(reg, chip->mc_indir_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) outb(chip->password, chip->mc_base + chip->pwd_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) retval = inb(chip->mc_indir_index + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #endif /* OPTi93X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) snd_printk(KERN_ERR "chip %d not supported\n", chip->hardware);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static void snd_opti9xx_write(struct snd_opti9xx *chip, unsigned char reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) unsigned char value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) outb(chip->password, chip->mc_base + chip->pwd_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) switch (chip->hardware) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #ifndef OPTi93X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) case OPTi9XX_HW_82C924:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) case OPTi9XX_HW_82C925:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (reg > 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) outb(reg, chip->mc_base + 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) outb(chip->password, chip->mc_base + chip->pwd_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) outb(value, chip->mc_base + 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) case OPTi9XX_HW_82C928:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) case OPTi9XX_HW_82C929:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) outb(value, chip->mc_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #else /* OPTi93X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) case OPTi9XX_HW_82C930:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) case OPTi9XX_HW_82C931:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) case OPTi9XX_HW_82C933:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) outb(reg, chip->mc_indir_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) outb(chip->password, chip->mc_base + chip->pwd_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) outb(value, chip->mc_indir_index + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #endif /* OPTi93X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) snd_printk(KERN_ERR "chip %d not supported\n", chip->hardware);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static inline void snd_opti9xx_write_mask(struct snd_opti9xx *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) unsigned char reg, unsigned char value, unsigned char mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) unsigned char oldval = snd_opti9xx_read(chip, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) snd_opti9xx_write(chip, reg, (oldval & ~mask) | (value & mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static int snd_opti9xx_configure(struct snd_opti9xx *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) long port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) int irq, int dma1, int dma2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) long mpu_port, int mpu_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) unsigned char wss_base_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) unsigned char irq_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) unsigned char dma_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) unsigned char mpu_port_bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) unsigned char mpu_irq_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) switch (chip->hardware) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #ifndef OPTi93X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) case OPTi9XX_HW_82C924:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* opti 929 mode (?), OPL3 clock output, audio enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(4), 0xf0, 0xfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* enable wave audio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(6), 0x02, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) case OPTi9XX_HW_82C925:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* enable WSS mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(1), 0x80, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* OPL3 FM synthesis */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(2), 0x00, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* disable Sound Blaster IRQ and DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(3), 0xf0, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #ifdef CS4231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* cs4231/4248 fix enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(5), 0x02, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* cs4231/4248 fix disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(5), 0x00, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #endif /* CS4231 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) case OPTi9XX_HW_82C928:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) case OPTi9XX_HW_82C929:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(1), 0x80, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(2), 0x00, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(3), 0xa2, 0xae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(4), 0x00, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #ifdef CS4231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(5), 0x02, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(5), 0x00, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #endif /* CS4231 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #else /* OPTi93X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) case OPTi9XX_HW_82C931:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* disable 3D sound (set GPIO1 as output, low) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(20), 0x04, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) case OPTi9XX_HW_82C933:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * The BTC 1817DW has QS1000 wavetable which is connected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * to the serial digital input of the OPTI931.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(21), 0x82, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * This bit sets OPTI931 to automaticaly select FM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * or digital input signal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(26), 0x01, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) case OPTi9XX_HW_82C930:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(6), 0x02, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(3), 0x00, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(4), 0x10 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) (chip->hardware == OPTi9XX_HW_82C930 ? 0x00 : 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 0x34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(5), 0x20, 0xbf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #endif /* OPTi93X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) snd_printk(KERN_ERR "chip %d not supported\n", chip->hardware);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* PnP resource says it decodes only 10 bits of address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) switch (port & 0x3ff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) case 0x130:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) chip->wss_base = 0x530;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) wss_base_bits = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) case 0x204:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) chip->wss_base = 0x604;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) wss_base_bits = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) case 0x280:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) chip->wss_base = 0xe80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) wss_base_bits = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) case 0x340:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) chip->wss_base = 0xf40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) wss_base_bits = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) snd_printk(KERN_WARNING "WSS port 0x%lx not valid\n", port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) goto __skip_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(1), wss_base_bits << 4, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) __skip_base:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) switch (irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) //#ifdef OPTi93X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) irq_bits = 0x05;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) //#endif /* OPTi93X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) irq_bits = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) case 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) irq_bits = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) case 10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) irq_bits = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) case 11:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) irq_bits = 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) snd_printk(KERN_WARNING "WSS irq # %d not valid\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) goto __skip_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) switch (dma1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) dma_bits = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) dma_bits = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) dma_bits = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) snd_printk(KERN_WARNING "WSS dma1 # %d not valid\n", dma1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) goto __skip_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #if defined(CS4231) || defined(OPTi93X)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (dma1 == dma2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) snd_printk(KERN_ERR "don't want to share dmas\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) switch (dma2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) snd_printk(KERN_WARNING "WSS dma2 # %d not valid\n", dma2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) goto __skip_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) dma_bits |= 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #endif /* CS4231 || OPTi93X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #ifndef OPTi93X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) outb(irq_bits << 3 | dma_bits, chip->wss_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #else /* OPTi93X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) snd_opti9xx_write(chip, OPTi9XX_MC_REG(3), (irq_bits << 3 | dma_bits));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #endif /* OPTi93X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) __skip_resources:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (chip->hardware > OPTi9XX_HW_82C928) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) switch (mpu_port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) case -1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) case 0x300:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) mpu_port_bits = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) case 0x310:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) mpu_port_bits = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) case 0x320:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) mpu_port_bits = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) case 0x330:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) mpu_port_bits = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) snd_printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) "MPU-401 port 0x%lx not valid\n", mpu_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) goto __skip_mpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) switch (mpu_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) mpu_irq_bits = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) mpu_irq_bits = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) case 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) mpu_irq_bits = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) case 10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) mpu_irq_bits = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) snd_printk(KERN_WARNING "MPU-401 irq # %d not valid\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) mpu_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) goto __skip_mpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) (mpu_port <= 0) ? 0x00 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 0x80 | mpu_port_bits << 5 | mpu_irq_bits << 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 0xf8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) __skip_mpu:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #ifdef OPTi93X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static const DECLARE_TLV_DB_SCALE(db_scale_5bit_3db_step, -9300, 300, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static const DECLARE_TLV_DB_SCALE(db_scale_5bit, -4650, 150, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static const DECLARE_TLV_DB_SCALE(db_scale_4bit_12db_max, -3300, 300, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static const struct snd_kcontrol_new snd_opti93x_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) WSS_DOUBLE("Master Playback Switch", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) OPTi93X_OUT_LEFT, OPTi93X_OUT_RIGHT, 7, 7, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) WSS_DOUBLE_TLV("Master Playback Volume", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) OPTi93X_OUT_LEFT, OPTi93X_OUT_RIGHT, 1, 1, 31, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) db_scale_5bit_3db_step),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) WSS_DOUBLE_TLV("PCM Playback Volume", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 0, 0, 31, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) db_scale_5bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) WSS_DOUBLE_TLV("FM Playback Volume", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 1, 1, 15, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) db_scale_4bit_12db_max),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) WSS_DOUBLE("Line Playback Switch", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 7, 7, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) WSS_DOUBLE_TLV("Line Playback Volume", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 0, 0, 15, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) db_scale_4bit_12db_max),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) WSS_DOUBLE("Mic Playback Switch", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) OPTi93X_MIC_LEFT_INPUT, OPTi93X_MIC_RIGHT_INPUT, 7, 7, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) WSS_DOUBLE_TLV("Mic Playback Volume", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) OPTi93X_MIC_LEFT_INPUT, OPTi93X_MIC_RIGHT_INPUT, 1, 1, 15, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) db_scale_4bit_12db_max),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) WSS_DOUBLE_TLV("CD Playback Volume", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 1, 1, 15, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) db_scale_4bit_12db_max),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) WSS_DOUBLE("Aux Playback Switch", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) OPTi931_AUX_LEFT_INPUT, OPTi931_AUX_RIGHT_INPUT, 7, 7, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) WSS_DOUBLE_TLV("Aux Playback Volume", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) OPTi931_AUX_LEFT_INPUT, OPTi931_AUX_RIGHT_INPUT, 1, 1, 15, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) db_scale_4bit_12db_max),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static int snd_opti93x_mixer(struct snd_wss *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct snd_ctl_elem_id id1, id2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (snd_BUG_ON(!chip || !chip->pcm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) card = chip->card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) strcpy(card->mixername, chip->pcm->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) memset(&id1, 0, sizeof(id1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) memset(&id2, 0, sizeof(id2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) id1.iface = id2.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /* reassign AUX0 switch to CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) strcpy(id1.name, "Aux Playback Switch");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) strcpy(id2.name, "CD Playback Switch");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) err = snd_ctl_rename_id(card, &id1, &id2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) snd_printk(KERN_ERR "Cannot rename opti93x control\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /* reassign AUX1 switch to FM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) strcpy(id1.name, "Aux Playback Switch"); id1.index = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) strcpy(id2.name, "FM Playback Switch");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) err = snd_ctl_rename_id(card, &id1, &id2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) snd_printk(KERN_ERR "Cannot rename opti93x control\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /* remove AUX1 volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) strcpy(id1.name, "Aux Playback Volume"); id1.index = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) snd_ctl_remove_id(card, &id1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* Replace WSS volume controls with OPTi93x volume controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) id1.index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) for (idx = 0; idx < ARRAY_SIZE(snd_opti93x_controls); idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) strcpy(id1.name, snd_opti93x_controls[idx].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) snd_ctl_remove_id(card, &id1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) err = snd_ctl_add(card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) snd_ctl_new1(&snd_opti93x_controls[idx], chip));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static irqreturn_t snd_opti93x_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) struct snd_opti9xx *chip = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct snd_wss *codec = chip->codec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) unsigned char status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (!codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) status = snd_opti9xx_read(chip, OPTi9XX_MC_REG(11));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if ((status & OPTi93X_IRQ_PLAYBACK) && codec->playback_substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) snd_pcm_period_elapsed(codec->playback_substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if ((status & OPTi93X_IRQ_CAPTURE) && codec->capture_substream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) snd_wss_overrange(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) snd_pcm_period_elapsed(codec->capture_substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) outb(0x00, OPTi93X_PORT(codec, STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #endif /* OPTi93X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static int snd_opti9xx_read_check(struct snd_opti9xx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) unsigned char value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #ifdef OPTi93X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) chip->res_mc_base = request_region(chip->mc_base, chip->mc_base_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) "OPTi9xx MC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (chip->res_mc_base == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #ifndef OPTi93X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) value = snd_opti9xx_read(chip, OPTi9XX_MC_REG(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (value != 0xff && value != inb(chip->mc_base + OPTi9XX_MC_REG(1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (value == snd_opti9xx_read(chip, OPTi9XX_MC_REG(1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #else /* OPTi93X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) chip->res_mc_indir = request_region(chip->mc_indir_index, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) "OPTi93x MC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (chip->res_mc_indir == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) outb(chip->password, chip->mc_base + chip->pwd_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) outb(((chip->mc_indir_index & 0x1f0) >> 4), chip->mc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) value = snd_opti9xx_read(chip, OPTi9XX_MC_REG(7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) snd_opti9xx_write(chip, OPTi9XX_MC_REG(7), 0xff - value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (snd_opti9xx_read(chip, OPTi9XX_MC_REG(7)) == 0xff - value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) release_and_free_resource(chip->res_mc_indir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) chip->res_mc_indir = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #endif /* OPTi93X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) release_and_free_resource(chip->res_mc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) chip->res_mc_base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static int snd_card_opti9xx_detect(struct snd_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) struct snd_opti9xx *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #ifndef OPTi93X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) for (i = OPTi9XX_HW_82C928; i < OPTi9XX_HW_82C930; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) for (i = OPTi9XX_HW_82C931; i >= OPTi9XX_HW_82C930; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) err = snd_opti9xx_init(chip, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) err = snd_opti9xx_read_check(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (err == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #ifdef OPTi93X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) chip->mc_indir_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #ifdef CONFIG_PNP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static int snd_card_opti9xx_pnp(struct snd_opti9xx *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) struct pnp_card_link *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) const struct pnp_card_device_id *pid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) struct pnp_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) struct pnp_dev *devmpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #ifndef OPTi93X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) struct pnp_dev *devmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) pdev = pnp_request_card_device(card, pid->devs[0].id, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (pdev == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) err = pnp_activate_dev(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) snd_printk(KERN_ERR "AUDIO pnp configure failure: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #ifdef OPTi93X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) port = pnp_port_start(pdev, 0) - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) fm_port = pnp_port_start(pdev, 1) + 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /* adjust mc_indir_index - some cards report it at 0xe?d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) other at 0xe?c but it really is always at 0xe?e */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) chip->mc_indir_index = (pnp_port_start(pdev, 3) & ~0xf) | 0xe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) devmc = pnp_request_card_device(card, pid->devs[2].id, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (devmc == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) err = pnp_activate_dev(devmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) snd_printk(KERN_ERR "MC pnp configure failure: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) port = pnp_port_start(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) fm_port = pnp_port_start(pdev, 2) + 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) * The MC(0) is never accessed and card does not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) * include it in the PnP resource range. OPTI93x include it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) chip->mc_base = pnp_port_start(devmc, 0) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) chip->mc_base_size = pnp_port_len(devmc, 0) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #endif /* OPTi93X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) irq = pnp_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) dma1 = pnp_dma(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #if defined(CS4231) || defined(OPTi93X)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) dma2 = pnp_dma(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #endif /* CS4231 || OPTi93X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) devmpu = pnp_request_card_device(card, pid->devs[1].id, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (devmpu && mpu_port > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) err = pnp_activate_dev(devmpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) snd_printk(KERN_ERR "MPU401 pnp configure failure\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) mpu_port = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) mpu_port = pnp_port_start(devmpu, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) mpu_irq = pnp_irq(devmpu, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) return pid->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #endif /* CONFIG_PNP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static void snd_card_opti9xx_free(struct snd_card *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) struct snd_opti9xx *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if (chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #ifdef OPTi93X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (chip->irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) disable_irq(chip->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) free_irq(chip->irq, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) release_and_free_resource(chip->res_mc_indir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) release_and_free_resource(chip->res_mc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static int snd_opti9xx_probe(struct snd_card *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) static const long possible_ports[] = {0x530, 0xe80, 0xf40, 0x604, -1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) int xdma2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) struct snd_opti9xx *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) struct snd_wss *codec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) struct snd_rawmidi *rmidi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) struct snd_hwdep *synth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #if defined(CS4231) || defined(OPTi93X)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) xdma2 = dma2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) xdma2 = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (port == SNDRV_AUTO_PORT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) port = snd_legacy_find_free_ioport(possible_ports, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if (port < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) snd_printk(KERN_ERR "unable to find a free WSS port\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) error = snd_opti9xx_configure(chip, port, irq, dma1, xdma2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) mpu_port, mpu_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) error = snd_wss_create(card, chip->wss_base + 4, -1, irq, dma1, xdma2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #ifdef OPTi93X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) WSS_HW_OPTI93X, WSS_HWSHARE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) WSS_HW_DETECT, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) &codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if (error < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) chip->codec = codec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) error = snd_wss_pcm(codec, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if (error < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) error = snd_wss_mixer(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (error < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) #ifdef OPTi93X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) error = snd_opti93x_mixer(codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (error < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) #ifdef CS4231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) error = snd_wss_timer(codec, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (error < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #ifdef OPTi93X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) error = request_irq(irq, snd_opti93x_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) 0, DEV_NAME" - WSS", chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (error < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) snd_printk(KERN_ERR "opti9xx: can't grab IRQ %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) chip->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) card->sync_irq = chip->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) strcpy(card->driver, chip->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) sprintf(card->shortname, "OPTi %s", card->driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #if defined(CS4231) || defined(OPTi93X)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) snprintf(card->longname, sizeof(card->longname),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) "%s, %s at 0x%lx, irq %d, dma %d&%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) card->shortname, codec->pcm->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) chip->wss_base + 4, irq, dma1, xdma2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) snprintf(card->longname, sizeof(card->longname),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) "%s, %s at 0x%lx, irq %d, dma %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) card->shortname, codec->pcm->name, chip->wss_base + 4, irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) dma1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #endif /* CS4231 || OPTi93X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) if (mpu_port <= 0 || mpu_port == SNDRV_AUTO_PORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) rmidi = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) error = snd_mpu401_uart_new(card, 0, MPU401_HW_MPU401,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) mpu_port, 0, mpu_irq, &rmidi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) snd_printk(KERN_WARNING "no MPU-401 device at 0x%lx?\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) mpu_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (fm_port > 0 && fm_port != SNDRV_AUTO_PORT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) struct snd_opl3 *opl3 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #ifndef OPTi93X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (chip->hardware == OPTi9XX_HW_82C928 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) chip->hardware == OPTi9XX_HW_82C929 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) chip->hardware == OPTi9XX_HW_82C924) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) struct snd_opl4 *opl4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) /* assume we have an OPL4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) 0x20, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if (snd_opl4_create(card, fm_port, fm_port - 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) 2, &opl3, &opl4) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) /* no luck, use OPL3 instead */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) 0x00, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) #endif /* !OPTi93X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) if (!opl3 && snd_opl3_create(card, fm_port, fm_port + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) OPL3_HW_AUTO, 0, &opl3) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) snd_printk(KERN_WARNING "no OPL device at 0x%lx-0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) fm_port, fm_port + 4 - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (opl3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) error = snd_opl3_hwdep_new(opl3, 0, 1, &synth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (error < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) return snd_card_register(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) static int snd_opti9xx_card_new(struct device *pdev, struct snd_card **cardp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) err = snd_card_new(pdev, index, id, THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) sizeof(struct snd_opti9xx), &card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) card->private_free = snd_card_opti9xx_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) *cardp = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) static int snd_opti9xx_isa_match(struct device *devptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) unsigned int dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #ifdef CONFIG_PNP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (snd_opti9xx_pnp_is_probed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if (isapnp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) static int snd_opti9xx_isa_probe(struct device *devptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) unsigned int dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) static const long possible_mpu_ports[] = {0x300, 0x310, 0x320, 0x330, -1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) #ifdef OPTi93X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static const int possible_irqs[] = {5, 9, 10, 11, 7, -1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) static const int possible_irqs[] = {9, 10, 11, 7, -1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) #endif /* OPTi93X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) static const int possible_mpu_irqs[] = {5, 9, 10, 7, -1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) static const int possible_dma1s[] = {3, 1, 0, -1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) #if defined(CS4231) || defined(OPTi93X)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) static const int possible_dma2s[][2] = {{1,-1}, {0,-1}, {-1,-1}, {0,-1}};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) #endif /* CS4231 || OPTi93X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) if (mpu_port == SNDRV_AUTO_PORT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if ((mpu_port = snd_legacy_find_free_ioport(possible_mpu_ports, 2)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) snd_printk(KERN_ERR "unable to find a free MPU401 port\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) if (irq == SNDRV_AUTO_IRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) if ((irq = snd_legacy_find_free_irq(possible_irqs)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) snd_printk(KERN_ERR "unable to find a free IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (mpu_irq == SNDRV_AUTO_IRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) if ((mpu_irq = snd_legacy_find_free_irq(possible_mpu_irqs)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) snd_printk(KERN_ERR "unable to find a free MPU401 IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) if (dma1 == SNDRV_AUTO_DMA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if ((dma1 = snd_legacy_find_free_dma(possible_dma1s)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) snd_printk(KERN_ERR "unable to find a free DMA1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) #if defined(CS4231) || defined(OPTi93X)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) if (dma2 == SNDRV_AUTO_DMA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) if ((dma2 = snd_legacy_find_free_dma(possible_dma2s[dma1 % 4])) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) snd_printk(KERN_ERR "unable to find a free DMA2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) error = snd_opti9xx_card_new(devptr, &card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if (error < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) if ((error = snd_card_opti9xx_detect(card, card->private_data)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) if ((error = snd_opti9xx_probe(card)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) dev_set_drvdata(devptr, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) static int snd_opti9xx_isa_remove(struct device *devptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) unsigned int dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) snd_card_free(dev_get_drvdata(devptr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) static int snd_opti9xx_suspend(struct snd_card *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) struct snd_opti9xx *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) chip->codec->suspend(chip->codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) static int snd_opti9xx_resume(struct snd_card *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) struct snd_opti9xx *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) int error, xdma2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) #if defined(CS4231) || defined(OPTi93X)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) xdma2 = dma2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) xdma2 = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) error = snd_opti9xx_configure(chip, port, irq, dma1, xdma2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) mpu_port, mpu_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) chip->codec->resume(chip->codec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) snd_power_change_state(card, SNDRV_CTL_POWER_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) static int snd_opti9xx_isa_suspend(struct device *dev, unsigned int n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) return snd_opti9xx_suspend(dev_get_drvdata(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) static int snd_opti9xx_isa_resume(struct device *dev, unsigned int n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) return snd_opti9xx_resume(dev_get_drvdata(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) static struct isa_driver snd_opti9xx_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) .match = snd_opti9xx_isa_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .probe = snd_opti9xx_isa_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .remove = snd_opti9xx_isa_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) .suspend = snd_opti9xx_isa_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) .resume = snd_opti9xx_isa_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) .name = DEV_NAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) #ifdef CONFIG_PNP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) static int snd_opti9xx_pnp_probe(struct pnp_card_link *pcard,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) const struct pnp_card_device_id *pid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) int error, hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) struct snd_opti9xx *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) if (snd_opti9xx_pnp_is_probed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) if (! isapnp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) error = snd_opti9xx_card_new(&pcard->card->dev, &card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) if (error < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) hw = snd_card_opti9xx_pnp(chip, pcard, pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) switch (hw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) case 0x0924:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) hw = OPTi9XX_HW_82C924;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) case 0x0925:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) hw = OPTi9XX_HW_82C925;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) case 0x0931:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) hw = OPTi9XX_HW_82C931;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) if ((error = snd_opti9xx_init(chip, hw))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) error = snd_opti9xx_read_check(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) snd_printk(KERN_ERR "OPTI chip not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if ((error = snd_opti9xx_probe(card)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) pnp_set_card_drvdata(pcard, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) snd_opti9xx_pnp_is_probed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) static void snd_opti9xx_pnp_remove(struct pnp_card_link *pcard)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) snd_card_free(pnp_get_card_drvdata(pcard));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) pnp_set_card_drvdata(pcard, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) snd_opti9xx_pnp_is_probed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) static int snd_opti9xx_pnp_suspend(struct pnp_card_link *pcard,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) return snd_opti9xx_suspend(pnp_get_card_drvdata(pcard));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) static int snd_opti9xx_pnp_resume(struct pnp_card_link *pcard)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) return snd_opti9xx_resume(pnp_get_card_drvdata(pcard));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) static struct pnp_card_driver opti9xx_pnpc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .flags = PNP_DRIVER_RES_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) .name = DEV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) .id_table = snd_opti9xx_pnpids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .probe = snd_opti9xx_pnp_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) .remove = snd_opti9xx_pnp_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) .suspend = snd_opti9xx_pnp_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .resume = snd_opti9xx_pnp_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) #ifdef OPTi93X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) #define CHIP_NAME "82C93x"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) #define CHIP_NAME "82C92x"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) static int __init alsa_card_opti9xx_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) #ifdef CONFIG_PNP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) pnp_register_card_driver(&opti9xx_pnpc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) if (snd_opti9xx_pnp_is_probed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) pnp_unregister_card_driver(&opti9xx_pnpc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) return isa_register_driver(&snd_opti9xx_driver, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) static void __exit alsa_card_opti9xx_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) if (!snd_opti9xx_pnp_is_probed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) isa_unregister_driver(&snd_opti9xx_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) #ifdef CONFIG_PNP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) pnp_unregister_card_driver(&opti9xx_pnpc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) module_init(alsa_card_opti9xx_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) module_exit(alsa_card_opti9xx_exit)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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