Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  Driver for Yamaha OPL3-SA[2,3] soundcards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/isa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/pnp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <sound/wss.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <sound/mpu401.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <sound/opl3.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <sound/tlv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) MODULE_DESCRIPTION("Yamaha OPL3SA2+");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) MODULE_SUPPORTED_DEVICE("{{Yamaha,YMF719E-S},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 		"{Genius,Sound Maker 3DX},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 		"{Yamaha,OPL3SA3},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 		"{Intel,AL440LX sound},"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	        "{NeoMagic,MagicWave 3DX}}");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;	/* Index 0-MAX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;	/* ID for this card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_ISAPNP; /* Enable this card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #ifdef CONFIG_PNP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) static bool isapnp[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) static long port[SNDRV_CARDS] = SNDRV_DEFAULT_PORT;	/* 0xf86,0x370,0x100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) static long sb_port[SNDRV_CARDS] = SNDRV_DEFAULT_PORT;	/* 0x220,0x240,0x260 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) static long wss_port[SNDRV_CARDS] = SNDRV_DEFAULT_PORT;/* 0x530,0xe80,0xf40,0x604 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) static long fm_port[SNDRV_CARDS] = SNDRV_DEFAULT_PORT;	/* 0x388 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) static long midi_port[SNDRV_CARDS] = SNDRV_DEFAULT_PORT;/* 0x330,0x300 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) static int irq[SNDRV_CARDS] = SNDRV_DEFAULT_IRQ;	/* 0,1,3,5,9,11,12,15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) static int dma1[SNDRV_CARDS] = SNDRV_DEFAULT_DMA;	/* 1,3,5,6,7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) static int dma2[SNDRV_CARDS] = SNDRV_DEFAULT_DMA;	/* 1,3,5,6,7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) static int opl3sa3_ymode[SNDRV_CARDS];   /* 0,1,2,3 */ /*SL Added*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) module_param_array(index, int, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) MODULE_PARM_DESC(index, "Index value for OPL3-SA soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) module_param_array(id, charp, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) MODULE_PARM_DESC(id, "ID string for OPL3-SA soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) module_param_array(enable, bool, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) MODULE_PARM_DESC(enable, "Enable OPL3-SA soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #ifdef CONFIG_PNP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) module_param_array(isapnp, bool, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) MODULE_PARM_DESC(isapnp, "PnP detection for specified soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) module_param_hw_array(port, long, ioport, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) MODULE_PARM_DESC(port, "Port # for OPL3-SA driver.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) module_param_hw_array(sb_port, long, ioport, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) MODULE_PARM_DESC(sb_port, "SB port # for OPL3-SA driver.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) module_param_hw_array(wss_port, long, ioport, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) MODULE_PARM_DESC(wss_port, "WSS port # for OPL3-SA driver.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) module_param_hw_array(fm_port, long, ioport, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) MODULE_PARM_DESC(fm_port, "FM port # for OPL3-SA driver.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) module_param_hw_array(midi_port, long, ioport, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) MODULE_PARM_DESC(midi_port, "MIDI port # for OPL3-SA driver.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) module_param_hw_array(irq, int, irq, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) MODULE_PARM_DESC(irq, "IRQ # for OPL3-SA driver.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) module_param_hw_array(dma1, int, dma, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) MODULE_PARM_DESC(dma1, "DMA1 # for OPL3-SA driver.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) module_param_hw_array(dma2, int, dma, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) MODULE_PARM_DESC(dma2, "DMA2 # for OPL3-SA driver.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) module_param_array(opl3sa3_ymode, int, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) MODULE_PARM_DESC(opl3sa3_ymode, "Speaker size selection for 3D Enhancement mode: Desktop/Large Notebook/Small Notebook/HiFi.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #ifdef CONFIG_PNP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) static int isa_registered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) static int pnp_registered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static int pnpc_registered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) /* control ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define OPL3SA2_PM_CTRL		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define OPL3SA2_SYS_CTRL		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define OPL3SA2_IRQ_CONFIG	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define OPL3SA2_IRQ_STATUS	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define OPL3SA2_DMA_CONFIG	0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define OPL3SA2_MASTER_LEFT	0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define OPL3SA2_MASTER_RIGHT	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define OPL3SA2_MIC		0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define OPL3SA2_MISC		0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) /* opl3sa3 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define OPL3SA3_DGTL_DOWN	0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define OPL3SA3_ANLG_DOWN	0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define OPL3SA3_WIDE		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define OPL3SA3_BASS		0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define OPL3SA3_TREBLE		0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* power management bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define OPL3SA2_PM_ADOWN		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define OPL3SA2_PM_PSV		0x04		
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define OPL3SA2_PM_PDN		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define OPL3SA2_PM_PDX		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define OPL3SA2_PM_D0	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define OPL3SA2_PM_D3	(OPL3SA2_PM_ADOWN|OPL3SA2_PM_PSV|OPL3SA2_PM_PDN|OPL3SA2_PM_PDX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct snd_opl3sa2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	int version;		/* 2 or 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	unsigned long port;	/* control port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	struct resource *res_port; /* control port resource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	int single_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	spinlock_t reg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	struct snd_hwdep *synth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	struct snd_rawmidi *rmidi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	struct snd_wss *wss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	unsigned char ctlregs[0x20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	int ymode;		/* SL added */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	struct snd_kcontrol *master_switch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	struct snd_kcontrol *master_volume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PFX	"opl3sa2: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #ifdef CONFIG_PNP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static const struct pnp_device_id snd_opl3sa2_pnpbiosids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	{ .id = "YMH0021" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	{ .id = "NMX2210" },	/* Gateway Solo 2500 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	{ .id = "" }		/* end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) MODULE_DEVICE_TABLE(pnp, snd_opl3sa2_pnpbiosids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static const struct pnp_card_device_id snd_opl3sa2_pnpids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	/* Yamaha YMF719E-S (Genius Sound Maker 3DX) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	{ .id = "YMH0020", .devs = { { "YMH0021" } } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	/* Yamaha OPL3-SA3 (integrated on Intel's Pentium II AL440LX motherboard) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	{ .id = "YMH0030", .devs = { { "YMH0021" } } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	/* Yamaha OPL3-SA2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	{ .id = "YMH0800", .devs = { { "YMH0021" } } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	/* Yamaha OPL3-SA2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	{ .id = "YMH0801", .devs = { { "YMH0021" } } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	/* NeoMagic MagicWave 3DX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	{ .id = "NMX2200", .devs = { { "YMH2210" } } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	/* NeoMagic MagicWave 3D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	{ .id = "NMX2200", .devs = { { "NMX2210" } } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	/* --- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	{ .id = "" }	/* end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) MODULE_DEVICE_TABLE(pnp_card, snd_opl3sa2_pnpids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #endif /* CONFIG_PNP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* read control port (w/o spinlock) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static unsigned char __snd_opl3sa2_read(struct snd_opl3sa2 *chip, unsigned char reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	unsigned char result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	outb(0x1d, port);	/* password */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	printk(KERN_DEBUG "read [0x%lx] = 0x%x\n", port, inb(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	outb(reg, chip->port);	/* register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	result = inb(chip->port + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	printk(KERN_DEBUG "read [0x%lx] = 0x%x [0x%x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	       port, result, inb(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* read control port (with spinlock) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static unsigned char snd_opl3sa2_read(struct snd_opl3sa2 *chip, unsigned char reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	unsigned char result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	result = __snd_opl3sa2_read(chip, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* write control port (w/o spinlock) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static void __snd_opl3sa2_write(struct snd_opl3sa2 *chip, unsigned char reg, unsigned char value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	outb(0x1d, port);	/* password */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	outb(reg, chip->port);	/* register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	outb(value, chip->port + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	chip->ctlregs[reg] = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* write control port (with spinlock) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static void snd_opl3sa2_write(struct snd_opl3sa2 *chip, unsigned char reg, unsigned char value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	__snd_opl3sa2_write(chip, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int snd_opl3sa2_detect(struct snd_card *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	struct snd_opl3sa2 *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	unsigned long port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	unsigned char tmp, tmp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	char str[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	port = chip->port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	if ((chip->res_port = request_region(port, 2, "OPL3-SA control")) == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		snd_printk(KERN_ERR PFX "can't grab port 0x%lx\n", port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	snd_printk(KERN_DEBUG "REG 0A = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		   snd_opl3sa2_read(chip, 0x0a));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	chip->version = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	tmp = snd_opl3sa2_read(chip, OPL3SA2_MISC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	if (tmp == 0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		snd_printd("OPL3-SA [0x%lx] detect = 0x%x\n", port, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	switch (tmp & 0x07) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	case 0x01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		chip->version = 2; /* YMF711 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		chip->version = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		/* 0x02 - standard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		/* 0x03 - YM715B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		/* 0x04 - YM719 - OPL-SA4? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		/* 0x05 - OPL3-SA3 - Libretto 100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		/* 0x07 - unknown - Neomagic MagicWave 3D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	str[0] = chip->version + '0';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	str[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	strcat(card->shortname, str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	snd_opl3sa2_write(chip, OPL3SA2_MISC, tmp ^ 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	if ((tmp1 = snd_opl3sa2_read(chip, OPL3SA2_MISC)) != tmp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		snd_printd("OPL3-SA [0x%lx] detect (1) = 0x%x (0x%x)\n", port, tmp, tmp1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	/* try if the MIC register is accessible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	tmp = snd_opl3sa2_read(chip, OPL3SA2_MIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	snd_opl3sa2_write(chip, OPL3SA2_MIC, 0x8a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	if (((tmp1 = snd_opl3sa2_read(chip, OPL3SA2_MIC)) & 0x9f) != 0x8a) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		snd_printd("OPL3-SA [0x%lx] detect (2) = 0x%x (0x%x)\n", port, tmp, tmp1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	snd_opl3sa2_write(chip, OPL3SA2_MIC, 0x9f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	/* initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	/* Power Management - full on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	snd_opl3sa2_write(chip, OPL3SA2_PM_CTRL, OPL3SA2_PM_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	if (chip->version > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		/* ymode is bits 4&5 (of 0 to 7) on all but opl3sa2 versions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		snd_opl3sa2_write(chip, OPL3SA2_SYS_CTRL, (chip->ymode << 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		/* default for opl3sa2 versions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		snd_opl3sa2_write(chip, OPL3SA2_SYS_CTRL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	snd_opl3sa2_write(chip, OPL3SA2_IRQ_CONFIG, 0x0d);	/* Interrupt Channel Configuration - IRQ A = OPL3 + MPU + WSS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	if (chip->single_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		snd_opl3sa2_write(chip, OPL3SA2_DMA_CONFIG, 0x03);	/* DMA Configuration - DMA A = WSS-R + WSS-P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		snd_opl3sa2_write(chip, OPL3SA2_DMA_CONFIG, 0x21);	/* DMA Configuration - DMA B = WSS-R, DMA A = WSS-P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	snd_opl3sa2_write(chip, OPL3SA2_MISC, 0x80 | (tmp & 7));	/* Miscellaneous - default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	if (chip->version > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		snd_opl3sa2_write(chip, OPL3SA3_DGTL_DOWN, 0x00);	/* Digital Block Partial Power Down - default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		snd_opl3sa2_write(chip, OPL3SA3_ANLG_DOWN, 0x00);	/* Analog Block Partial Power Down - default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static irqreturn_t snd_opl3sa2_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	unsigned short status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	struct snd_card *card = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	struct snd_opl3sa2 *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	int handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	if (card == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	status = snd_opl3sa2_read(chip, OPL3SA2_IRQ_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	if (status & 0x20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		snd_opl3_interrupt(chip->synth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	if ((status & 0x10) && chip->rmidi != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	if (status & 0x07) {	/* TI,CI,PI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		snd_wss_interrupt(irq, chip->wss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	if (status & 0x40) { /* hardware volume change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		/* reading from Master Lch register at 0x07 clears this bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		snd_opl3sa2_read(chip, OPL3SA2_MASTER_RIGHT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		snd_opl3sa2_read(chip, OPL3SA2_MASTER_LEFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		if (chip->master_switch && chip->master_volume) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 			snd_ctl_notify(card, SNDRV_CTL_EVENT_MASK_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 					&chip->master_switch->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 			snd_ctl_notify(card, SNDRV_CTL_EVENT_MASK_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 					&chip->master_volume->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	return IRQ_RETVAL(handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define OPL3SA2_SINGLE(xname, xindex, reg, shift, mask, invert) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)   .info = snd_wss_info_single, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)   .get = snd_opl3sa2_get_single, .put = snd_opl3sa2_put_single, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)   .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define OPL3SA2_SINGLE_TLV(xname, xindex, reg, shift, mask, invert, xtlv) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)   .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)   .name = xname, .index = xindex, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)   .info = snd_wss_info_single, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)   .get = snd_opl3sa2_get_single, .put = snd_opl3sa2_put_single, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)   .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)   .tlv = { .p = (xtlv) } }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static int snd_opl3sa2_get_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	struct snd_opl3sa2 *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	int reg = kcontrol->private_value & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	int shift = (kcontrol->private_value >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	int mask = (kcontrol->private_value >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	int invert = (kcontrol->private_value >> 24) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	ucontrol->value.integer.value[0] = (chip->ctlregs[reg] >> shift) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	if (invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static int snd_opl3sa2_put_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	struct snd_opl3sa2 *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	int reg = kcontrol->private_value & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	int shift = (kcontrol->private_value >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	int mask = (kcontrol->private_value >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	int invert = (kcontrol->private_value >> 24) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	unsigned short val, oval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	val = (ucontrol->value.integer.value[0] & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	if (invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		val = mask - val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	val <<= shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	oval = chip->ctlregs[reg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	val = (oval & ~(mask << shift)) | val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	change = val != oval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	__snd_opl3sa2_write(chip, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define OPL3SA2_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)   .info = snd_wss_info_double, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)   .get = snd_opl3sa2_get_double, .put = snd_opl3sa2_put_double, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)   .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define OPL3SA2_DOUBLE_TLV(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert, xtlv) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)   .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)   .name = xname, .index = xindex, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)   .info = snd_wss_info_double, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)   .get = snd_opl3sa2_get_double, .put = snd_opl3sa2_put_double, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)   .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)   .tlv = { .p = (xtlv) } }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static int snd_opl3sa2_get_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	struct snd_opl3sa2 *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	int left_reg = kcontrol->private_value & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	int right_reg = (kcontrol->private_value >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	int shift_left = (kcontrol->private_value >> 16) & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	int shift_right = (kcontrol->private_value >> 19) & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	int mask = (kcontrol->private_value >> 24) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	int invert = (kcontrol->private_value >> 22) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	ucontrol->value.integer.value[0] = (chip->ctlregs[left_reg] >> shift_left) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	ucontrol->value.integer.value[1] = (chip->ctlregs[right_reg] >> shift_right) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	if (invert) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 		ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 		ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static int snd_opl3sa2_put_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	struct snd_opl3sa2 *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	int left_reg = kcontrol->private_value & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	int right_reg = (kcontrol->private_value >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	int shift_left = (kcontrol->private_value >> 16) & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	int shift_right = (kcontrol->private_value >> 19) & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	int mask = (kcontrol->private_value >> 24) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	int invert = (kcontrol->private_value >> 22) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	unsigned short val1, val2, oval1, oval2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	val1 = ucontrol->value.integer.value[0] & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	val2 = ucontrol->value.integer.value[1] & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	if (invert) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 		val1 = mask - val1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 		val2 = mask - val2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	val1 <<= shift_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	val2 <<= shift_right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	spin_lock_irqsave(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	if (left_reg != right_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 		oval1 = chip->ctlregs[left_reg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 		oval2 = chip->ctlregs[right_reg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 		val1 = (oval1 & ~(mask << shift_left)) | val1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 		val2 = (oval2 & ~(mask << shift_right)) | val2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 		change = val1 != oval1 || val2 != oval2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 		__snd_opl3sa2_write(chip, left_reg, val1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 		__snd_opl3sa2_write(chip, right_reg, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 		oval1 = chip->ctlregs[left_reg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 		val1 = (oval1 & ~((mask << shift_left) | (mask << shift_right))) | val1 | val2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 		change = val1 != oval1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 		__snd_opl3sa2_write(chip, left_reg, val1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	spin_unlock_irqrestore(&chip->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static const DECLARE_TLV_DB_SCALE(db_scale_master, -3000, 200, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static const DECLARE_TLV_DB_SCALE(db_scale_5bit_12db_max, -3450, 150, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static const struct snd_kcontrol_new snd_opl3sa2_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) OPL3SA2_DOUBLE("Master Playback Switch", 0, 0x07, 0x08, 7, 7, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) OPL3SA2_DOUBLE_TLV("Master Playback Volume", 0, 0x07, 0x08, 0, 0, 15, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 		   db_scale_master),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) OPL3SA2_SINGLE("Mic Playback Switch", 0, 0x09, 7, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) OPL3SA2_SINGLE_TLV("Mic Playback Volume", 0, 0x09, 0, 31, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 		   db_scale_5bit_12db_max),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) OPL3SA2_SINGLE("ZV Port Switch", 0, 0x02, 0, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static const struct snd_kcontrol_new snd_opl3sa2_tone_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) OPL3SA2_DOUBLE("3D Control - Wide", 0, 0x14, 0x14, 4, 0, 7, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) OPL3SA2_DOUBLE("Tone Control - Bass", 0, 0x15, 0x15, 4, 0, 7, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) OPL3SA2_DOUBLE("Tone Control - Treble", 0, 0x16, 0x16, 4, 0, 7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static void snd_opl3sa2_master_free(struct snd_kcontrol *kcontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	struct snd_opl3sa2 *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	chip->master_switch = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	chip->master_volume = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static int snd_opl3sa2_mixer(struct snd_card *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	struct snd_opl3sa2 *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	struct snd_ctl_elem_id id1, id2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	struct snd_kcontrol *kctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	memset(&id1, 0, sizeof(id1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	memset(&id2, 0, sizeof(id2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	id1.iface = id2.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	/* reassign AUX0 to CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)         strcpy(id1.name, "Aux Playback Switch");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)         strcpy(id2.name, "CD Playback Switch");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)         if ((err = snd_ctl_rename_id(card, &id1, &id2)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 		snd_printk(KERN_ERR "Cannot rename opl3sa2 control\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)                 return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)         strcpy(id1.name, "Aux Playback Volume");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)         strcpy(id2.name, "CD Playback Volume");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)         if ((err = snd_ctl_rename_id(card, &id1, &id2)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 		snd_printk(KERN_ERR "Cannot rename opl3sa2 control\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)                 return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	/* reassign AUX1 to FM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)         strcpy(id1.name, "Aux Playback Switch"); id1.index = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)         strcpy(id2.name, "FM Playback Switch");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)         if ((err = snd_ctl_rename_id(card, &id1, &id2)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 		snd_printk(KERN_ERR "Cannot rename opl3sa2 control\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)                 return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)         strcpy(id1.name, "Aux Playback Volume");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)         strcpy(id2.name, "FM Playback Volume");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)         if ((err = snd_ctl_rename_id(card, &id1, &id2)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 		snd_printk(KERN_ERR "Cannot rename opl3sa2 control\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)                 return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	/* add OPL3SA2 controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 	for (idx = 0; idx < ARRAY_SIZE(snd_opl3sa2_controls); idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 		if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_opl3sa2_controls[idx], chip))) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 		switch (idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 		case 0: chip->master_switch = kctl; kctl->private_free = snd_opl3sa2_master_free; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 		case 1: chip->master_volume = kctl; kctl->private_free = snd_opl3sa2_master_free; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 	if (chip->version > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 		for (idx = 0; idx < ARRAY_SIZE(snd_opl3sa2_tone_controls); idx++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 			if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_opl3sa2_tone_controls[idx], chip))) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 				return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /* Power Management support functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static int snd_opl3sa2_suspend(struct snd_card *card, pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 	if (card) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 		struct snd_opl3sa2 *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 		snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 		chip->wss->suspend(chip->wss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 		/* power down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 		snd_opl3sa2_write(chip, OPL3SA2_PM_CTRL, OPL3SA2_PM_D3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static int snd_opl3sa2_resume(struct snd_card *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 	struct snd_opl3sa2 *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 	if (!card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 	chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 	/* power up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 	snd_opl3sa2_write(chip, OPL3SA2_PM_CTRL, OPL3SA2_PM_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 	/* restore registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 	for (i = 2; i <= 0x0a; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 		if (i != OPL3SA2_IRQ_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 			snd_opl3sa2_write(chip, i, chip->ctlregs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 	if (chip->version > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 		for (i = 0x12; i <= 0x16; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 			snd_opl3sa2_write(chip, i, chip->ctlregs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 	/* restore wss */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 	chip->wss->resume(chip->wss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 	snd_power_change_state(card, SNDRV_CTL_POWER_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #ifdef CONFIG_PNP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static int snd_opl3sa2_pnp(int dev, struct snd_opl3sa2 *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 			   struct pnp_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 	if (pnp_activate_dev(pdev) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 		snd_printk(KERN_ERR "PnP configure failure (out of resources?)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 	sb_port[dev] = pnp_port_start(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 	wss_port[dev] = pnp_port_start(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 	fm_port[dev] = pnp_port_start(pdev, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 	midi_port[dev] = pnp_port_start(pdev, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 	port[dev] = pnp_port_start(pdev, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 	dma1[dev] = pnp_dma(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 	dma2[dev] = pnp_dma(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 	irq[dev] = pnp_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 	snd_printdd("%sPnP OPL3-SA: sb port=0x%lx, wss port=0x%lx, fm port=0x%lx, midi port=0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 		pnp_device_is_pnpbios(pdev) ? "BIOS" : "ISA", sb_port[dev], wss_port[dev], fm_port[dev], midi_port[dev]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 	snd_printdd("%sPnP OPL3-SA: control port=0x%lx, dma1=%i, dma2=%i, irq=%i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 		pnp_device_is_pnpbios(pdev) ? "BIOS" : "ISA", port[dev], dma1[dev], dma2[dev], irq[dev]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #endif /* CONFIG_PNP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static void snd_opl3sa2_free(struct snd_card *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) 	struct snd_opl3sa2 *chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 	if (chip->irq >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 		free_irq(chip->irq, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) 	release_and_free_resource(chip->res_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static int snd_opl3sa2_card_new(struct device *pdev, int dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 				struct snd_card **cardp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) 	struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) 	struct snd_opl3sa2 *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) 	err = snd_card_new(pdev, index[dev], id[dev], THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) 			   sizeof(struct snd_opl3sa2), &card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) 	strcpy(card->driver, "OPL3SA2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) 	strcpy(card->shortname, "Yamaha OPL3-SA");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) 	chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) 	spin_lock_init(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) 	chip->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) 	card->private_free = snd_opl3sa2_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) 	*cardp = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static int snd_opl3sa2_probe(struct snd_card *card, int dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) 	int xirq, xdma1, xdma2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) 	struct snd_opl3sa2 *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) 	struct snd_wss *wss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) 	struct snd_opl3 *opl3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) 	/* initialise this card from supplied (or default) parameter*/ 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) 	chip = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) 	chip->ymode = opl3sa3_ymode[dev] & 0x03 ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) 	chip->port = port[dev];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) 	xirq = irq[dev];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) 	xdma1 = dma1[dev];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) 	xdma2 = dma2[dev];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) 	if (xdma2 < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) 		chip->single_dma = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) 	err = snd_opl3sa2_detect(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) 	err = request_irq(xirq, snd_opl3sa2_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) 			  "OPL3-SA2", card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) 		snd_printk(KERN_ERR PFX "can't grab IRQ %d\n", xirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) 	chip->irq = xirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) 	card->sync_irq = chip->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) 	err = snd_wss_create(card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) 			     wss_port[dev] + 4, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) 			     xirq, xdma1, xdma2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) 			     WSS_HW_OPL3SA2, WSS_HWSHARE_IRQ, &wss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) 	if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) 		snd_printd("Oops, WSS not detected at 0x%lx\n", wss_port[dev] + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) 	chip->wss = wss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) 	err = snd_wss_pcm(wss, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) 	err = snd_wss_mixer(wss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) 	err = snd_opl3sa2_mixer(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) 	err = snd_wss_timer(wss, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) 	if (fm_port[dev] >= 0x340 && fm_port[dev] < 0x400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) 		if ((err = snd_opl3_create(card, fm_port[dev],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) 					   fm_port[dev] + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) 					   OPL3_HW_OPL3, 0, &opl3)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) 		if ((err = snd_opl3_timer_new(opl3, 1, 2)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) 		if ((err = snd_opl3_hwdep_new(opl3, 0, 1, &chip->synth)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) 	if (midi_port[dev] >= 0x300 && midi_port[dev] < 0x340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) 		if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_OPL3SA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) 					       midi_port[dev],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) 					       MPU401_INFO_IRQ_HOOK, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) 					       &chip->rmidi)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) 	sprintf(card->longname, "%s at 0x%lx, irq %d, dma %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) 		card->shortname, chip->port, xirq, xdma1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) 	if (xdma2 >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) 		sprintf(card->longname + strlen(card->longname), "&%d", xdma2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) 	return snd_card_register(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #ifdef CONFIG_PNP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) static int snd_opl3sa2_pnp_detect(struct pnp_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) 				  const struct pnp_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) 	static int dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) 	struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) 	if (pnp_device_is_isapnp(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) 		return -ENOENT;	/* we have another procedure - card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) 	for (; dev < SNDRV_CARDS; dev++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) 		if (enable[dev] && isapnp[dev])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) 	if (dev >= SNDRV_CARDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) 	err = snd_opl3sa2_card_new(&pdev->dev, dev, &card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) 	if ((err = snd_opl3sa2_pnp(dev, card->private_data, pdev)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) 		snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) 	if ((err = snd_opl3sa2_probe(card, dev)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) 		snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) 	pnp_set_drvdata(pdev, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) 	dev++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) static void snd_opl3sa2_pnp_remove(struct pnp_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) 	snd_card_free(pnp_get_drvdata(pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static int snd_opl3sa2_pnp_suspend(struct pnp_dev *pdev, pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) 	return snd_opl3sa2_suspend(pnp_get_drvdata(pdev), state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) static int snd_opl3sa2_pnp_resume(struct pnp_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) 	return snd_opl3sa2_resume(pnp_get_drvdata(pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) static struct pnp_driver opl3sa2_pnp_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) 	.name = "snd-opl3sa2-pnpbios",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) 	.id_table = snd_opl3sa2_pnpbiosids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) 	.probe = snd_opl3sa2_pnp_detect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) 	.remove = snd_opl3sa2_pnp_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) 	.suspend = snd_opl3sa2_pnp_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) 	.resume = snd_opl3sa2_pnp_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static int snd_opl3sa2_pnp_cdetect(struct pnp_card_link *pcard,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) 				   const struct pnp_card_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) 	static int dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) 	struct pnp_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) 	struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) 	pdev = pnp_request_card_device(pcard, id->devs[0].id, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) 	if (pdev == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) 		snd_printk(KERN_ERR PFX "can't get pnp device from id '%s'\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) 			   id->devs[0].id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) 	for (; dev < SNDRV_CARDS; dev++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) 		if (enable[dev] && isapnp[dev])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) 	if (dev >= SNDRV_CARDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) 	err = snd_opl3sa2_card_new(&pdev->dev, dev, &card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) 	if ((err = snd_opl3sa2_pnp(dev, card->private_data, pdev)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) 		snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) 	if ((err = snd_opl3sa2_probe(card, dev)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) 		snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) 	pnp_set_card_drvdata(pcard, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) 	dev++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static void snd_opl3sa2_pnp_cremove(struct pnp_card_link *pcard)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) 	snd_card_free(pnp_get_card_drvdata(pcard));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) 	pnp_set_card_drvdata(pcard, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) static int snd_opl3sa2_pnp_csuspend(struct pnp_card_link *pcard, pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) 	return snd_opl3sa2_suspend(pnp_get_card_drvdata(pcard), state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) static int snd_opl3sa2_pnp_cresume(struct pnp_card_link *pcard)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) 	return snd_opl3sa2_resume(pnp_get_card_drvdata(pcard));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) static struct pnp_card_driver opl3sa2_pnpc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) 	.flags = PNP_DRIVER_RES_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) 	.name = "snd-opl3sa2-cpnp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) 	.id_table = snd_opl3sa2_pnpids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) 	.probe = snd_opl3sa2_pnp_cdetect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) 	.remove = snd_opl3sa2_pnp_cremove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) 	.suspend = snd_opl3sa2_pnp_csuspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) 	.resume = snd_opl3sa2_pnp_cresume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #endif /* CONFIG_PNP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static int snd_opl3sa2_isa_match(struct device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) 				 unsigned int dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) 	if (!enable[dev])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #ifdef CONFIG_PNP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) 	if (isapnp[dev])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) 	if (port[dev] == SNDRV_AUTO_PORT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) 		snd_printk(KERN_ERR PFX "specify port\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) 	if (wss_port[dev] == SNDRV_AUTO_PORT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) 		snd_printk(KERN_ERR PFX "specify wss_port\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) 	if (fm_port[dev] == SNDRV_AUTO_PORT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) 		snd_printk(KERN_ERR PFX "specify fm_port\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) 	if (midi_port[dev] == SNDRV_AUTO_PORT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) 		snd_printk(KERN_ERR PFX "specify midi_port\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static int snd_opl3sa2_isa_probe(struct device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) 				 unsigned int dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) 	struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) 	err = snd_opl3sa2_card_new(pdev, dev, &card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) 	if ((err = snd_opl3sa2_probe(card, dev)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) 		snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) 	dev_set_drvdata(pdev, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) static int snd_opl3sa2_isa_remove(struct device *devptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) 				  unsigned int dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) 	snd_card_free(dev_get_drvdata(devptr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) static int snd_opl3sa2_isa_suspend(struct device *dev, unsigned int n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) 				   pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) 	return snd_opl3sa2_suspend(dev_get_drvdata(dev), state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) static int snd_opl3sa2_isa_resume(struct device *dev, unsigned int n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) 	return snd_opl3sa2_resume(dev_get_drvdata(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #define DEV_NAME "opl3sa2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) static struct isa_driver snd_opl3sa2_isa_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) 	.match		= snd_opl3sa2_isa_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) 	.probe		= snd_opl3sa2_isa_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) 	.remove		= snd_opl3sa2_isa_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) 	.suspend	= snd_opl3sa2_isa_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) 	.resume		= snd_opl3sa2_isa_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) 		.name	= DEV_NAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) static int __init alsa_card_opl3sa2_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) 	err = isa_register_driver(&snd_opl3sa2_isa_driver, SNDRV_CARDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) #ifdef CONFIG_PNP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) 	if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) 		isa_registered = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) 	err = pnp_register_driver(&opl3sa2_pnp_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) 	if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) 		pnp_registered = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) 	err = pnp_register_card_driver(&opl3sa2_pnpc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) 	if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) 		pnpc_registered = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) 	if (isa_registered || pnp_registered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) 		err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) static void __exit alsa_card_opl3sa2_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) #ifdef CONFIG_PNP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) 	if (pnpc_registered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) 		pnp_unregister_card_driver(&opl3sa2_pnpc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) 	if (pnp_registered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) 		pnp_unregister_driver(&opl3sa2_pnp_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) 	if (isa_registered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) 		isa_unregister_driver(&snd_opl3sa2_isa_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) module_init(alsa_card_opl3sa2_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) module_exit(alsa_card_opl3sa2_exit)