^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * msnd_pinnacle.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Turtle Beach MultiSound Sound Card Driver for Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Some parts of this header file were derived from the Turtle Beach
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * MultiSound Driver Development Kit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 1998 Andrew Veliath
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (C) 1993 Turtle Beach Systems, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) ********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #ifndef __MSND_PINNACLE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define __MSND_PINNACLE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DSP_NUMIO 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define IREG_LOGDEVICE 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define IREG_ACTIVATE 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define LD_ACTIVATE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define LD_DISACTIVATE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define IREG_EECONTROL 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IREG_MEMBASEHI 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IREG_MEMBASELO 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IREG_MEMCONTROL 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IREG_MEMRANGEHI 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IREG_MEMRANGELO 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MEMTYPE_8BIT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MEMTYPE_16BIT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MEMTYPE_RANGE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MEMTYPE_HIADDR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IREG_IO0_BASEHI 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IREG_IO0_BASELO 0x61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IREG_IO1_BASEHI 0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IREG_IO1_BASELO 0x63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IREG_IRQ_NUMBER 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IREG_IRQ_TYPE 0x71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IRQTYPE_HIGH 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IRQTYPE_LOW 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IRQTYPE_LEVEL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IRQTYPE_EDGE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define HP_DSPR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define HP_BLKS 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define HPDSPRESET_OFF 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define HPDSPRESET_ON 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define HPBLKSEL_0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define HPBLKSEL_1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define HIMT_DAT_OFF 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define HIDSP_PLAY_UNDER 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define HIDSP_INT_PLAY_UNDER 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define HIDSP_SSI_TX_UNDER 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define HIDSP_RECQ_OVERFLOW 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define HIDSP_INT_RECORD_OVER 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define HIDSP_SSI_RX_OVERFLOW 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define HIDSP_MIDI_IN_OVER 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define HIDSP_MIDI_FRAME_ERR 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define HIDSP_MIDI_PARITY_ERR 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define HIDSP_MIDI_OVERRUN_ERR 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define HIDSP_INPUT_CLIPPING 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define HIDSP_MIX_CLIPPING 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define HIDSP_DAT_IN_OFF 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TIME_PRO_RESET_DONE 0x028A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define TIME_PRO_SYSEX 0x001E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define TIME_PRO_RESET 0x0032
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DAR_BUFF_SIZE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MIDQ_BUFF_SIZE 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DSPQ_BUFF_SIZE 0x5A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DSPQ_DATA_BUFF 0x7860
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MOP_WAVEHDR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MOP_EXTOUT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MOP_HWINIT 0xfe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MOP_NONE 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MOP_MAX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MIP_EXTIN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MIP_WAVEHDR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MIP_HWINIT 0xfe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MIP_MAX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Pinnacle/Fiji SMA Common Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SMA_wCurrPlayBytes 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SMA_wCurrRecordBytes 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SMA_wCurrPlayVolLeft 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SMA_wCurrPlayVolRight 0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SMA_wCurrInVolLeft 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SMA_wCurrInVolRight 0x000a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SMA_wCurrMHdrVolLeft 0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SMA_wCurrMHdrVolRight 0x000e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SMA_dwCurrPlayPitch 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SMA_dwCurrPlayRate 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SMA_wCurrMIDIIOPatch 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SMA_wCurrPlayFormat 0x001a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SMA_wCurrPlaySampleSize 0x001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SMA_wCurrPlayChannels 0x001e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SMA_wCurrPlaySampleRate 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SMA_wCurrRecordFormat 0x0022
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SMA_wCurrRecordSampleSize 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SMA_wCurrRecordChannels 0x0026
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SMA_wCurrRecordSampleRate 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SMA_wCurrDSPStatusFlags 0x002a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SMA_wCurrHostStatusFlags 0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SMA_wCurrInputTagBits 0x002e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SMA_wCurrLeftPeak 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SMA_wCurrRightPeak 0x0032
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SMA_bMicPotPosLeft 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SMA_bMicPotPosRight 0x0035
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SMA_bMicPotMaxLeft 0x0036
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SMA_bMicPotMaxRight 0x0037
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SMA_bInPotPosLeft 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SMA_bInPotPosRight 0x0039
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SMA_bAuxPotPosLeft 0x003a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SMA_bAuxPotPosRight 0x003b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SMA_bInPotMaxLeft 0x003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SMA_bInPotMaxRight 0x003d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SMA_bAuxPotMaxLeft 0x003e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SMA_bAuxPotMaxRight 0x003f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SMA_bInPotMaxMethod 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SMA_bAuxPotMaxMethod 0x0041
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SMA_wCurrMastVolLeft 0x0042
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SMA_wCurrMastVolRight 0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SMA_wCalFreqAtoD 0x0046
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SMA_wCurrAuxVolLeft 0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SMA_wCurrAuxVolRight 0x004a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SMA_wCurrPlay1VolLeft 0x004c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SMA_wCurrPlay1VolRight 0x004e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SMA_wCurrPlay2VolLeft 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SMA_wCurrPlay2VolRight 0x0052
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SMA_wCurrPlay3VolLeft 0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SMA_wCurrPlay3VolRight 0x0056
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SMA_wCurrPlay4VolLeft 0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SMA_wCurrPlay4VolRight 0x005a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SMA_wCurrPlay1PeakLeft 0x005c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SMA_wCurrPlay1PeakRight 0x005e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SMA_wCurrPlay2PeakLeft 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SMA_wCurrPlay2PeakRight 0x0062
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define SMA_wCurrPlay3PeakLeft 0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SMA_wCurrPlay3PeakRight 0x0066
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define SMA_wCurrPlay4PeakLeft 0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SMA_wCurrPlay4PeakRight 0x006a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SMA_wCurrPlayPeakLeft 0x006c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SMA_wCurrPlayPeakRight 0x006e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SMA_wCurrDATSR 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SMA_wCurrDATRXCHNL 0x0072
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SMA_wCurrDATTXCHNL 0x0074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SMA_wCurrDATRXRate 0x0076
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SMA_dwDSPPlayCount 0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SMA__size 0x007c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define INITCODEFILE "turtlebeach/pndspini.bin"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define PERMCODEFILE "turtlebeach/pndsperm.bin"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define LONGNAME "MultiSound (Pinnacle/Fiji)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #endif /* __MSND_PINNACLE_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags