^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * msnd.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Turtle Beach MultiSound Sound Card Driver for Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Some parts of this header file were derived from the Turtle Beach
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * MultiSound Driver Development Kit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 1998 Andrew Veliath
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (C) 1993 Turtle Beach Systems, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) ********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #ifndef __MSND_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define __MSND_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DEFSAMPLERATE 44100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DEFSAMPLESIZE SNDRV_PCM_FORMAT_S16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DEFCHANNELS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SRAM_BANK_SIZE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SRAM_CNTL_START 0x7F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SMA_STRUCT_START 0x7F40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DSP_BASE_ADDR 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DSP_BANK_BASE 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AGND 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SIGNAL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define EXT_DSP_BIT_DCAL 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define EXT_DSP_BIT_MIDI_CON 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define BUFFSIZE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define HOSTQ_SIZE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DAP_BUFF_SIZE 0x2400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DAPQ_STRUCT_SIZE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DARQ_STRUCT_SIZE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DAPQ_BUFF_SIZE (3 * 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DARQ_BUFF_SIZE (3 * 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MODQ_BUFF_SIZE 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DAPQ_DATA_BUFF 0x6C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DARQ_DATA_BUFF 0x6C30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MODQ_DATA_BUFF 0x6C60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MIDQ_DATA_BUFF 0x7060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DAPQ_OFFSET SRAM_CNTL_START
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DARQ_OFFSET (SRAM_CNTL_START + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MODQ_OFFSET (SRAM_CNTL_START + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MIDQ_OFFSET (SRAM_CNTL_START + 0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DSPQ_OFFSET (SRAM_CNTL_START + 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define HP_ICR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define HP_CVR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define HP_ISR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define HP_IVR 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define HP_NU 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define HP_INFO 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define HP_TXH 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define HP_RXH 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define HP_TXM 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define HP_RXM 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define HP_TXL 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define HP_RXL 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define HP_ICR_DEF 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define HP_CVR_DEF 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define HP_ISR_DEF 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define HP_IVR_DEF 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define HP_NU_DEF 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define HP_IRQM 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define HPR_BLRC 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define HPR_SPR1 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define HPR_SPR2 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define HPR_TCL0 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define HPR_TCL1 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define HPR_TCL2 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define HPR_TCL3 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define HPR_TCL4 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define HPICR_INIT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define HPICR_HM1 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define HPICR_HM0 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define HPICR_HF1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define HPICR_HF0 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define HPICR_TREQ 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define HPICR_RREQ 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define HPCVR_HC 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define HPISR_HREQ 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define HPISR_DMA 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define HPISR_HF3 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define HPISR_HF2 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define HPISR_TRDY 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define HPISR_TXDE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define HPISR_RXDF 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define HPIO_290 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define HPIO_260 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define HPIO_250 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define HPIO_240 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define HPIO_230 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define HPIO_220 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define HPIO_210 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define HPIO_3E0 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define HPMEM_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define HPMEM_B000 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define HPMEM_C800 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define HPMEM_D000 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define HPMEM_D400 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define HPMEM_D800 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define HPMEM_E000 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define HPMEM_E800 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define HPIRQ_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define HPIRQ_5 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define HPIRQ_7 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define HPIRQ_9 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define HPIRQ_10 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define HPIRQ_11 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define HPIRQ_12 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define HPIRQ_15 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define HIMT_PLAY_DONE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define HIMT_RECORD_DONE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define HIMT_MIDI_EOS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define HIMT_MIDI_OUT 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define HIMT_MIDI_IN_UCHAR 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define HIMT_DSP 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define HDEX_BASE 0x92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define HDEX_PLAY_START (0 + HDEX_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define HDEX_PLAY_STOP (1 + HDEX_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define HDEX_PLAY_PAUSE (2 + HDEX_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define HDEX_PLAY_RESUME (3 + HDEX_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define HDEX_RECORD_START (4 + HDEX_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define HDEX_RECORD_STOP (5 + HDEX_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define HDEX_MIDI_IN_START (6 + HDEX_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define HDEX_MIDI_IN_STOP (7 + HDEX_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define HDEX_MIDI_OUT_START (8 + HDEX_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define HDEX_MIDI_OUT_STOP (9 + HDEX_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define HDEX_AUX_REQ (10 + HDEX_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define HDEXAR_CLEAR_PEAKS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define HDEXAR_IN_SET_POTS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define HDEXAR_AUX_SET_POTS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define HDEXAR_CAL_A_TO_D 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define HDEXAR_RD_EXT_DSP_BITS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Pinnacle only HDEXAR defs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define HDEXAR_SET_ANA_IN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define HDEXAR_SET_SYNTH_IN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define HDEXAR_READ_DAT_IN 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define HDEXAR_MIC_SET_POTS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define HDEXAR_SET_DAT_IN 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define HDEXAR_SET_SYNTH_48 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define HDEXAR_SET_SYNTH_44 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define HIWORD(l) ((u16)((((u32)(l)) >> 16) & 0xFFFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define LOWORD(l) ((u16)(u32)(l))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define HIBYTE(w) ((u8)(((u16)(w) >> 8) & 0xFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define LOBYTE(w) ((u8)(w))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define MAKELONG(low, hi) ((long)(((u16)(low))|(((u32)((u16)(hi)))<<16)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define MAKEWORD(low, hi) ((u16)(((u8)(low))|(((u16)((u8)(hi)))<<8)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define PCTODSP_OFFSET(w) (u16)((w)/2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define PCTODSP_BASED(w) (u16)(((w)/2) + DSP_BASE_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define DSPTOPC_BASED(w) (((w) - DSP_BASE_ADDR) * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #ifdef SLOWIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) # undef outb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) # undef inb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) # define outb outb_p
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) # define inb inb_p
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* JobQueueStruct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define JQS_wStart 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define JQS_wSize 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define JQS_wHead 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define JQS_wTail 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define JQS__size 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* DAQueueDataStruct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define DAQDS_wStart 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define DAQDS_wSize 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define DAQDS_wFormat 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define DAQDS_wSampleSize 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define DAQDS_wChannels 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define DAQDS_wSampleRate 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define DAQDS_wIntMsg 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define DAQDS_wFlags 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define DAQDS__size 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct snd_msnd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) void __iomem *mappedbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int play_period_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int playLimit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int playPeriods;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int playDMAPos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int banksPlayed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) int captureDMAPos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int capturePeriodBytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int captureLimit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int capturePeriods;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) void *msndmidi_mpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct snd_rawmidi *rmidi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* Hardware resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) long io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int memid, irqid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int irq, irq_ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) unsigned long base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* Motorola 56k DSP SMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) void __iomem *SMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) void __iomem *DAPQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) void __iomem *DARQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) void __iomem *MODQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) void __iomem *MIDQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) void __iomem *DSPQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int dspq_data_buff, dspq_buff_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* State variables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) enum { msndClassic, msndPinnacle } type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) fmode_t mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define F_RESETTING 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define F_HAVEDIGITAL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define F_AUDIO_WRITE_INUSE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define F_WRITING 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define F_WRITEBLOCK 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define F_WRITEFLUSH 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define F_AUDIO_READ_INUSE 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define F_READING 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define F_READBLOCK 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define F_EXT_MIDI_INUSE 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define F_HDR_MIDI_INUSE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define F_DISABLE_WRITE_NDELAY 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) spinlock_t mixer_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int nresets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) unsigned recsrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define LEVEL_ENTRIES 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) int left_levels[LEVEL_ENTRIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int right_levels[LEVEL_ENTRIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) int calibrate_signal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) int play_sample_size, play_sample_rate, play_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) int play_ndelay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int capture_sample_size, capture_sample_rate, capture_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) int capture_ndelay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u8 bCurrentMidiPatch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) int last_playbank, last_recbank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct snd_pcm_substream *playback_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct snd_pcm_substream *capture_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) void snd_msnd_init_queue(void __iomem *base, int start, int size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) int snd_msnd_send_dsp_cmd(struct snd_msnd *chip, u8 cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) int snd_msnd_send_word(struct snd_msnd *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) unsigned char high,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) unsigned char mid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) unsigned char low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int snd_msnd_upload_host(struct snd_msnd *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) const u8 *bin, int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) int snd_msnd_enable_irq(struct snd_msnd *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) int snd_msnd_disable_irq(struct snd_msnd *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) void snd_msnd_dsp_halt(struct snd_msnd *chip, struct file *file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) int snd_msnd_DAPQ(struct snd_msnd *chip, int start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) int snd_msnd_DARQ(struct snd_msnd *chip, int start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) int snd_msnd_pcm(struct snd_card *card, int device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) int snd_msndmidi_new(struct snd_card *card, int device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) void snd_msndmidi_input_read(void *mpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) void snd_msndmix_setup(struct snd_msnd *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) int snd_msndmix_new(struct snd_card *card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int snd_msndmix_force_recsrc(struct snd_msnd *chip, int recsrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #endif /* __MSND_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags