^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * I/O routines for GF1/InterWave synthesizer chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <sound/gus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) void snd_gf1_delay(struct snd_gus_card * gus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) for (i = 0; i < 6; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) inb(GUSP(gus, DRAM));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * =======================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * ok.. stop of control registers (wave & ramp) need some special things..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * big UltraClick (tm) elimination...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static inline void __snd_gf1_ctrl_stop(struct snd_gus_card * gus, unsigned char reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned char value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) outb(reg | 0x80, gus->gf1.reg_regsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) value = inb(gus->gf1.reg_data8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) outb(reg, gus->gf1.reg_regsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) outb((value | 0x03) & ~(0x80 | 0x20), gus->gf1.reg_data8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static inline void __snd_gf1_write8(struct snd_gus_card * gus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned char reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) unsigned char data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) outb(reg, gus->gf1.reg_regsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) outb(data, gus->gf1.reg_data8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static inline unsigned char __snd_gf1_look8(struct snd_gus_card * gus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned char reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) outb(reg, gus->gf1.reg_regsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return inb(gus->gf1.reg_data8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static inline void __snd_gf1_write16(struct snd_gus_card * gus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned char reg, unsigned int data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) outb(reg, gus->gf1.reg_regsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) outw((unsigned short) data, gus->gf1.reg_data16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static inline unsigned short __snd_gf1_look16(struct snd_gus_card * gus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned char reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) outb(reg, gus->gf1.reg_regsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return inw(gus->gf1.reg_data16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static inline void __snd_gf1_adlib_write(struct snd_gus_card * gus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned char reg, unsigned char data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) outb(reg, gus->gf1.reg_timerctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) inb(gus->gf1.reg_timerctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) inb(gus->gf1.reg_timerctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) outb(data, gus->gf1.reg_timerdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) inb(gus->gf1.reg_timerctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) inb(gus->gf1.reg_timerctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static inline void __snd_gf1_write_addr(struct snd_gus_card * gus, unsigned char reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned int addr, int w_16bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (gus->gf1.enh_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (w_16bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) addr = ((addr >> 1) & ~0x0000000f) | (addr & 0x0000000f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) __snd_gf1_write8(gus, SNDRV_GF1_VB_UPPER_ADDRESS, (unsigned char) ((addr >> 26) & 0x03));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) } else if (w_16bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) addr = (addr & 0x00c0000f) | ((addr & 0x003ffff0) >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) __snd_gf1_write16(gus, reg, (unsigned short) (addr >> 11));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) __snd_gf1_write16(gus, reg + 1, (unsigned short) (addr << 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static inline unsigned int __snd_gf1_read_addr(struct snd_gus_card * gus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned char reg, short w_16bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) res = ((unsigned int) __snd_gf1_look16(gus, reg | 0x80) << 11) & 0xfff800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) res |= ((unsigned int) __snd_gf1_look16(gus, (reg + 1) | 0x80) >> 5) & 0x0007ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (gus->gf1.enh_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) res |= (unsigned int) __snd_gf1_look8(gus, SNDRV_GF1_VB_UPPER_ADDRESS | 0x80) << 26;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (w_16bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) res = ((res << 1) & 0xffffffe0) | (res & 0x0000000f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) } else if (w_16bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) res = ((res & 0x001ffff0) << 1) | (res & 0x00c0000f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * =======================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) void snd_gf1_ctrl_stop(struct snd_gus_card * gus, unsigned char reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) __snd_gf1_ctrl_stop(gus, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) void snd_gf1_write8(struct snd_gus_card * gus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned char reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned char data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) __snd_gf1_write8(gus, reg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned char snd_gf1_look8(struct snd_gus_card * gus, unsigned char reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return __snd_gf1_look8(gus, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) void snd_gf1_write16(struct snd_gus_card * gus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned char reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) unsigned int data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) __snd_gf1_write16(gus, reg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) unsigned short snd_gf1_look16(struct snd_gus_card * gus, unsigned char reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return __snd_gf1_look16(gus, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) void snd_gf1_adlib_write(struct snd_gus_card * gus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) unsigned char reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned char data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) __snd_gf1_adlib_write(gus, reg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) void snd_gf1_write_addr(struct snd_gus_card * gus, unsigned char reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned int addr, short w_16bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) __snd_gf1_write_addr(gus, reg, addr, w_16bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) unsigned int snd_gf1_read_addr(struct snd_gus_card * gus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned char reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) short w_16bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return __snd_gf1_read_addr(gus, reg, w_16bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) void snd_gf1_i_ctrl_stop(struct snd_gus_card * gus, unsigned char reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) spin_lock_irqsave(&gus->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) __snd_gf1_ctrl_stop(gus, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) spin_unlock_irqrestore(&gus->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) void snd_gf1_i_write8(struct snd_gus_card * gus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) unsigned char reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned char data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) spin_lock_irqsave(&gus->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) __snd_gf1_write8(gus, reg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) spin_unlock_irqrestore(&gus->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned char snd_gf1_i_look8(struct snd_gus_card * gus, unsigned char reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) unsigned char res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) spin_lock_irqsave(&gus->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) res = __snd_gf1_look8(gus, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) spin_unlock_irqrestore(&gus->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) void snd_gf1_i_write16(struct snd_gus_card * gus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) unsigned char reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) unsigned int data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) spin_lock_irqsave(&gus->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) __snd_gf1_write16(gus, reg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) spin_unlock_irqrestore(&gus->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) unsigned short snd_gf1_i_look16(struct snd_gus_card * gus, unsigned char reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned short res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) spin_lock_irqsave(&gus->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) res = __snd_gf1_look16(gus, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) spin_unlock_irqrestore(&gus->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) void snd_gf1_i_adlib_write(struct snd_gus_card * gus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) unsigned char reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) unsigned char data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) spin_lock_irqsave(&gus->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) __snd_gf1_adlib_write(gus, reg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) spin_unlock_irqrestore(&gus->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) void snd_gf1_i_write_addr(struct snd_gus_card * gus, unsigned char reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) unsigned int addr, short w_16bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) spin_lock_irqsave(&gus->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) __snd_gf1_write_addr(gus, reg, addr, w_16bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) spin_unlock_irqrestore(&gus->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #endif /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #ifdef CONFIG_SND_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static unsigned int snd_gf1_i_read_addr(struct snd_gus_card * gus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) unsigned char reg, short w_16bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) unsigned int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) spin_lock_irqsave(&gus->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) res = __snd_gf1_read_addr(gus, reg, w_16bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) spin_unlock_irqrestore(&gus->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) void snd_gf1_dram_addr(struct snd_gus_card * gus, unsigned int addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) outb(0x43, gus->gf1.reg_regsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) outw((unsigned short) addr, gus->gf1.reg_data16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) outb(0x44, gus->gf1.reg_regsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) outb((unsigned char) (addr >> 16), gus->gf1.reg_data8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) void snd_gf1_poke(struct snd_gus_card * gus, unsigned int addr, unsigned char data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) spin_lock_irqsave(&gus->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) outb(SNDRV_GF1_GW_DRAM_IO_LOW, gus->gf1.reg_regsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) outw((unsigned short) addr, gus->gf1.reg_data16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) outb(SNDRV_GF1_GB_DRAM_IO_HIGH, gus->gf1.reg_regsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) outb((unsigned char) (addr >> 16), gus->gf1.reg_data8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) outb(data, gus->gf1.reg_dram);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) spin_unlock_irqrestore(&gus->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) unsigned char snd_gf1_peek(struct snd_gus_card * gus, unsigned int addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) unsigned char res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) spin_lock_irqsave(&gus->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) outb(SNDRV_GF1_GW_DRAM_IO_LOW, gus->gf1.reg_regsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) outw((unsigned short) addr, gus->gf1.reg_data16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) outb(SNDRV_GF1_GB_DRAM_IO_HIGH, gus->gf1.reg_regsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) outb((unsigned char) (addr >> 16), gus->gf1.reg_data8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) res = inb(gus->gf1.reg_dram);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) spin_unlock_irqrestore(&gus->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) void snd_gf1_pokew(struct snd_gus_card * gus, unsigned int addr, unsigned short data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #ifdef CONFIG_SND_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (!gus->interwave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) snd_printk(KERN_DEBUG "snd_gf1_pokew - GF1!!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) spin_lock_irqsave(&gus->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) outb(SNDRV_GF1_GW_DRAM_IO_LOW, gus->gf1.reg_regsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) outw((unsigned short) addr, gus->gf1.reg_data16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) outb(SNDRV_GF1_GB_DRAM_IO_HIGH, gus->gf1.reg_regsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) outb((unsigned char) (addr >> 16), gus->gf1.reg_data8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) outb(SNDRV_GF1_GW_DRAM_IO16, gus->gf1.reg_regsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) outw(data, gus->gf1.reg_data16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) spin_unlock_irqrestore(&gus->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) unsigned short snd_gf1_peekw(struct snd_gus_card * gus, unsigned int addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) unsigned short res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #ifdef CONFIG_SND_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (!gus->interwave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) snd_printk(KERN_DEBUG "snd_gf1_peekw - GF1!!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) spin_lock_irqsave(&gus->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) outb(SNDRV_GF1_GW_DRAM_IO_LOW, gus->gf1.reg_regsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) outw((unsigned short) addr, gus->gf1.reg_data16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) outb(SNDRV_GF1_GB_DRAM_IO_HIGH, gus->gf1.reg_regsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) outb((unsigned char) (addr >> 16), gus->gf1.reg_data8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) outb(SNDRV_GF1_GW_DRAM_IO16, gus->gf1.reg_regsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) res = inw(gus->gf1.reg_data16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) spin_unlock_irqrestore(&gus->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) void snd_gf1_dram_setmem(struct snd_gus_card * gus, unsigned int addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) unsigned short value, unsigned int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) unsigned long port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #ifdef CONFIG_SND_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (!gus->interwave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) snd_printk(KERN_DEBUG "snd_gf1_dram_setmem - GF1!!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) addr &= ~1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) count >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) port = GUSP(gus, GF1DATALOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) spin_lock_irqsave(&gus->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) outb(SNDRV_GF1_GW_DRAM_IO_LOW, gus->gf1.reg_regsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) outw((unsigned short) addr, gus->gf1.reg_data16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) outb(SNDRV_GF1_GB_DRAM_IO_HIGH, gus->gf1.reg_regsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) outb((unsigned char) (addr >> 16), gus->gf1.reg_data8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) outb(SNDRV_GF1_GW_DRAM_IO16, gus->gf1.reg_regsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) while (count--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) outw(value, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) spin_unlock_irqrestore(&gus->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #endif /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) void snd_gf1_select_active_voices(struct snd_gus_card * gus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) unsigned short voices;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static const unsigned short voices_tbl[32 - 14 + 1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 44100, 41160, 38587, 36317, 34300, 32494, 30870, 29400, 28063, 26843,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 25725, 24696, 23746, 22866, 22050, 21289, 20580, 19916, 19293
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) voices = gus->gf1.active_voices;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (voices > 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) voices = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (voices < 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) voices = 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (gus->gf1.enh_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) voices = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) gus->gf1.active_voices = voices;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) gus->gf1.playback_freq =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) gus->gf1.enh_mode ? 44100 : voices_tbl[voices - 14];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (!gus->gf1.enh_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) snd_gf1_i_write8(gus, SNDRV_GF1_GB_ACTIVE_VOICES, 0xc0 | (voices - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #ifdef CONFIG_SND_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) void snd_gf1_print_voice_registers(struct snd_gus_card * gus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) unsigned char mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) int voice, ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) voice = gus->gf1.active_voice;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) printk(KERN_INFO " -%i- GF1 voice ctrl, ramp ctrl = 0x%x, 0x%x\n", voice, ctrl = snd_gf1_i_read8(gus, 0), snd_gf1_i_read8(gus, 0x0d));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) printk(KERN_INFO " -%i- GF1 frequency = 0x%x\n", voice, snd_gf1_i_read16(gus, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) printk(KERN_INFO " -%i- GF1 loop start, end = 0x%x (0x%x), 0x%x (0x%x)\n", voice, snd_gf1_i_read_addr(gus, 2, ctrl & 4), snd_gf1_i_read_addr(gus, 2, (ctrl & 4) ^ 4), snd_gf1_i_read_addr(gus, 4, ctrl & 4), snd_gf1_i_read_addr(gus, 4, (ctrl & 4) ^ 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) printk(KERN_INFO " -%i- GF1 ramp start, end, rate = 0x%x, 0x%x, 0x%x\n", voice, snd_gf1_i_read8(gus, 7), snd_gf1_i_read8(gus, 8), snd_gf1_i_read8(gus, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) printk(KERN_INFO" -%i- GF1 volume = 0x%x\n", voice, snd_gf1_i_read16(gus, 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) printk(KERN_INFO " -%i- GF1 position = 0x%x (0x%x)\n", voice, snd_gf1_i_read_addr(gus, 0x0a, ctrl & 4), snd_gf1_i_read_addr(gus, 0x0a, (ctrl & 4) ^ 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (gus->interwave && snd_gf1_i_read8(gus, 0x19) & 0x01) { /* enhanced mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) mode = snd_gf1_i_read8(gus, 0x15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) printk(KERN_INFO " -%i- GFA1 mode = 0x%x\n", voice, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (mode & 0x01) { /* Effect processor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) printk(KERN_INFO " -%i- GFA1 effect address = 0x%x\n", voice, snd_gf1_i_read_addr(gus, 0x11, ctrl & 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) printk(KERN_INFO " -%i- GFA1 effect volume = 0x%x\n", voice, snd_gf1_i_read16(gus, 0x16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) printk(KERN_INFO " -%i- GFA1 effect volume final = 0x%x\n", voice, snd_gf1_i_read16(gus, 0x1d));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) printk(KERN_INFO " -%i- GFA1 effect accumulator = 0x%x\n", voice, snd_gf1_i_read8(gus, 0x14));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (mode & 0x20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) printk(KERN_INFO " -%i- GFA1 left offset = 0x%x (%i)\n", voice, snd_gf1_i_read16(gus, 0x13), snd_gf1_i_read16(gus, 0x13) >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) printk(KERN_INFO " -%i- GFA1 left offset final = 0x%x (%i)\n", voice, snd_gf1_i_read16(gus, 0x1c), snd_gf1_i_read16(gus, 0x1c) >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) printk(KERN_INFO " -%i- GFA1 right offset = 0x%x (%i)\n", voice, snd_gf1_i_read16(gus, 0x0c), snd_gf1_i_read16(gus, 0x0c) >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) printk(KERN_INFO " -%i- GFA1 right offset final = 0x%x (%i)\n", voice, snd_gf1_i_read16(gus, 0x1b), snd_gf1_i_read16(gus, 0x1b) >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) printk(KERN_INFO " -%i- GF1 pan = 0x%x\n", voice, snd_gf1_i_read8(gus, 0x0c));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) printk(KERN_INFO " -%i- GF1 pan = 0x%x\n", voice, snd_gf1_i_read8(gus, 0x0c));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) void snd_gf1_print_global_registers(struct snd_gus_card * gus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) unsigned char global_mode = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) printk(KERN_INFO " -G- GF1 active voices = 0x%x\n", snd_gf1_i_look8(gus, SNDRV_GF1_GB_ACTIVE_VOICES));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (gus->interwave) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) global_mode = snd_gf1_i_read8(gus, SNDRV_GF1_GB_GLOBAL_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) printk(KERN_INFO " -G- GF1 global mode = 0x%x\n", global_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (global_mode & 0x02) /* LFO enabled? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) printk(KERN_INFO " -G- GF1 LFO base = 0x%x\n", snd_gf1_i_look16(gus, SNDRV_GF1_GW_LFO_BASE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) printk(KERN_INFO " -G- GF1 voices IRQ read = 0x%x\n", snd_gf1_i_look8(gus, SNDRV_GF1_GB_VOICES_IRQ_READ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) printk(KERN_INFO " -G- GF1 DRAM DMA control = 0x%x\n", snd_gf1_i_look8(gus, SNDRV_GF1_GB_DRAM_DMA_CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) printk(KERN_INFO " -G- GF1 DRAM DMA high/low = 0x%x/0x%x\n", snd_gf1_i_look8(gus, SNDRV_GF1_GB_DRAM_DMA_HIGH), snd_gf1_i_read16(gus, SNDRV_GF1_GW_DRAM_DMA_LOW));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) printk(KERN_INFO " -G- GF1 DRAM IO high/low = 0x%x/0x%x\n", snd_gf1_i_look8(gus, SNDRV_GF1_GB_DRAM_IO_HIGH), snd_gf1_i_read16(gus, SNDRV_GF1_GW_DRAM_IO_LOW));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (!gus->interwave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) printk(KERN_INFO " -G- GF1 record DMA control = 0x%x\n", snd_gf1_i_look8(gus, SNDRV_GF1_GB_REC_DMA_CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) printk(KERN_INFO " -G- GF1 DRAM IO 16 = 0x%x\n", snd_gf1_i_look16(gus, SNDRV_GF1_GW_DRAM_IO16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (gus->gf1.enh_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) printk(KERN_INFO " -G- GFA1 memory config = 0x%x\n", snd_gf1_i_look16(gus, SNDRV_GF1_GW_MEMORY_CONFIG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) printk(KERN_INFO " -G- GFA1 memory control = 0x%x\n", snd_gf1_i_look8(gus, SNDRV_GF1_GB_MEMORY_CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) printk(KERN_INFO " -G- GFA1 FIFO record base = 0x%x\n", snd_gf1_i_look16(gus, SNDRV_GF1_GW_FIFO_RECORD_BASE_ADDR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) printk(KERN_INFO " -G- GFA1 FIFO playback base = 0x%x\n", snd_gf1_i_look16(gus, SNDRV_GF1_GW_FIFO_PLAY_BASE_ADDR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) printk(KERN_INFO " -G- GFA1 interleave control = 0x%x\n", snd_gf1_i_look16(gus, SNDRV_GF1_GW_INTERLEAVE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) void snd_gf1_print_setup_registers(struct snd_gus_card * gus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) printk(KERN_INFO " -S- mix control = 0x%x\n", inb(GUSP(gus, MIXCNTRLREG)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) printk(KERN_INFO " -S- IRQ status = 0x%x\n", inb(GUSP(gus, IRQSTAT)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) printk(KERN_INFO " -S- timer control = 0x%x\n", inb(GUSP(gus, TIMERCNTRL)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) printk(KERN_INFO " -S- timer data = 0x%x\n", inb(GUSP(gus, TIMERDATA)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) printk(KERN_INFO " -S- status read = 0x%x\n", inb(GUSP(gus, REGCNTRLS)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) printk(KERN_INFO " -S- Sound Blaster control = 0x%x\n", snd_gf1_i_look8(gus, SNDRV_GF1_GB_SOUND_BLASTER_CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) printk(KERN_INFO " -S- AdLib timer 1/2 = 0x%x/0x%x\n", snd_gf1_i_look8(gus, SNDRV_GF1_GB_ADLIB_TIMER_1), snd_gf1_i_look8(gus, SNDRV_GF1_GB_ADLIB_TIMER_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) printk(KERN_INFO " -S- reset = 0x%x\n", snd_gf1_i_look8(gus, SNDRV_GF1_GB_RESET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (gus->interwave) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) printk(KERN_INFO " -S- compatibility = 0x%x\n", snd_gf1_i_look8(gus, SNDRV_GF1_GB_COMPATIBILITY));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) printk(KERN_INFO " -S- decode control = 0x%x\n", snd_gf1_i_look8(gus, SNDRV_GF1_GB_DECODE_CONTROL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) printk(KERN_INFO " -S- version number = 0x%x\n", snd_gf1_i_look8(gus, SNDRV_GF1_GB_VERSION_NUMBER));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) printk(KERN_INFO " -S- MPU-401 emul. control A/B = 0x%x/0x%x\n", snd_gf1_i_look8(gus, SNDRV_GF1_GB_MPU401_CONTROL_A), snd_gf1_i_look8(gus, SNDRV_GF1_GB_MPU401_CONTROL_B));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) printk(KERN_INFO " -S- emulation IRQ = 0x%x\n", snd_gf1_i_look8(gus, SNDRV_GF1_GB_EMULATION_IRQ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) void snd_gf1_peek_print_block(struct snd_gus_card * gus, unsigned int addr, int count, int w_16bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (!w_16bit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) while (count-- > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) printk(count > 0 ? "%02x:" : "%02x", snd_gf1_peek(gus, addr++));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) while (count-- > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) printk(count > 0 ? "%04x:" : "%04x", snd_gf1_peek(gus, addr) | (snd_gf1_peek(gus, addr + 1) << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) addr += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #endif /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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