^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Aztech AZT1605/AZT2316 Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2007,2010 Rene Herman
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/isa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <sound/wss.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <sound/mpu401.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <sound/opl3.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) MODULE_DESCRIPTION(CRD_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) MODULE_AUTHOR("Rene Herman");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) module_param_array(index, int, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) MODULE_PARM_DESC(index, "Index value for " CRD_NAME " soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) module_param_array(id, charp, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MODULE_PARM_DESC(id, "ID string for " CRD_NAME " soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) module_param_array(enable, bool, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) MODULE_PARM_DESC(enable, "Enable " CRD_NAME " soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static long port[SNDRV_CARDS] = SNDRV_DEFAULT_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static long wss_port[SNDRV_CARDS] = SNDRV_DEFAULT_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static long mpu_port[SNDRV_CARDS] = SNDRV_DEFAULT_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static long fm_port[SNDRV_CARDS] = SNDRV_DEFAULT_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static int irq[SNDRV_CARDS] = SNDRV_DEFAULT_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static int mpu_irq[SNDRV_CARDS] = SNDRV_DEFAULT_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static int dma1[SNDRV_CARDS] = SNDRV_DEFAULT_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static int dma2[SNDRV_CARDS] = SNDRV_DEFAULT_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) module_param_hw_array(port, long, ioport, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) MODULE_PARM_DESC(port, "Port # for " CRD_NAME " driver.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) module_param_hw_array(wss_port, long, ioport, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MODULE_PARM_DESC(wss_port, "WSS port # for " CRD_NAME " driver.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) module_param_hw_array(mpu_port, long, ioport, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MODULE_PARM_DESC(mpu_port, "MPU-401 port # for " CRD_NAME " driver.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) module_param_hw_array(fm_port, long, ioport, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) MODULE_PARM_DESC(fm_port, "FM port # for " CRD_NAME " driver.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) module_param_hw_array(irq, int, irq, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MODULE_PARM_DESC(irq, "IRQ # for " CRD_NAME " driver.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) module_param_hw_array(mpu_irq, int, irq, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MODULE_PARM_DESC(mpu_irq, "MPU-401 IRQ # for " CRD_NAME " driver.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) module_param_hw_array(dma1, int, dma, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MODULE_PARM_DESC(dma1, "Playback DMA # for " CRD_NAME " driver.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) module_param_hw_array(dma2, int, dma, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MODULE_PARM_DESC(dma2, "Capture DMA # for " CRD_NAME " driver.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * Generic SB DSP support routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DSP_PORT_RESET 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DSP_PORT_READ 0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DSP_PORT_COMMAND 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DSP_PORT_STATUS 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DSP_PORT_DATA_AVAIL 0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DSP_SIGNATURE 0xaa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DSP_COMMAND_GET_VERSION 0xe1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static int dsp_get_byte(void __iomem *port, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int loops = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) while (!(ioread8(port + DSP_PORT_DATA_AVAIL) & 0x80)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (!loops--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) *val = ioread8(port + DSP_PORT_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static int dsp_reset(void __iomem *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) iowrite8(1, port + DSP_PORT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) iowrite8(0, port + DSP_PORT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (dsp_get_byte(port, &val) < 0 || val != DSP_SIGNATURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static int dsp_command(void __iomem *port, u8 cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int loops = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) while (ioread8(port + DSP_PORT_STATUS) & 0x80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (!loops--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) iowrite8(cmd, port + DSP_PORT_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static int dsp_get_version(void __iomem *port, u8 *major, u8 *minor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) err = dsp_command(port, DSP_COMMAND_GET_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) err = dsp_get_byte(port, major);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) err = dsp_get_byte(port, minor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * Generic WSS support routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define WSS_CONFIG_DMA_0 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define WSS_CONFIG_DMA_1 (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define WSS_CONFIG_DMA_3 (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define WSS_CONFIG_DUPLEX (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define WSS_CONFIG_IRQ_7 (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define WSS_CONFIG_IRQ_9 (2 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define WSS_CONFIG_IRQ_10 (3 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define WSS_CONFIG_IRQ_11 (4 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define WSS_PORT_CONFIG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define WSS_PORT_SIGNATURE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define WSS_SIGNATURE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int wss_detect(void __iomem *wss_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if ((ioread8(wss_port + WSS_PORT_SIGNATURE) & 0x3f) != WSS_SIGNATURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static void wss_set_config(void __iomem *wss_port, u8 wss_config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) iowrite8(wss_config, wss_port + WSS_PORT_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * Aztech Sound Galaxy specifics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define GALAXY_PORT_CONFIG 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CONFIG_PORT_SET 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define DSP_COMMAND_GALAXY_8 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define GALAXY_COMMAND_GET_TYPE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define DSP_COMMAND_GALAXY_9 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define GALAXY_COMMAND_WSSMODE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define GALAXY_COMMAND_SB8MODE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define GALAXY_MODE_WSS GALAXY_COMMAND_WSSMODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define GALAXY_MODE_SB8 GALAXY_COMMAND_SB8MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct snd_galaxy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) void __iomem *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) void __iomem *config_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) void __iomem *wss_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u32 config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct resource *res_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct resource *res_config_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct resource *res_wss_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static u32 config[SNDRV_CARDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static u8 wss_config[SNDRV_CARDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int snd_galaxy_match(struct device *dev, unsigned int n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (!enable[n])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) switch (port[n]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) case SNDRV_AUTO_PORT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) dev_err(dev, "please specify port\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) case 0x220:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) config[n] |= GALAXY_CONFIG_SBA_220;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) case 0x240:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) config[n] |= GALAXY_CONFIG_SBA_240;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) case 0x260:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) config[n] |= GALAXY_CONFIG_SBA_260;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) case 0x280:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) config[n] |= GALAXY_CONFIG_SBA_280;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) dev_err(dev, "invalid port %#lx\n", port[n]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) switch (wss_port[n]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) case SNDRV_AUTO_PORT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) dev_err(dev, "please specify wss_port\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) case 0x530:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) config[n] |= GALAXY_CONFIG_WSS_ENABLE | GALAXY_CONFIG_WSSA_530;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) case 0x604:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) config[n] |= GALAXY_CONFIG_WSS_ENABLE | GALAXY_CONFIG_WSSA_604;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) case 0xe80:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) config[n] |= GALAXY_CONFIG_WSS_ENABLE | GALAXY_CONFIG_WSSA_E80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) case 0xf40:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) config[n] |= GALAXY_CONFIG_WSS_ENABLE | GALAXY_CONFIG_WSSA_F40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) dev_err(dev, "invalid WSS port %#lx\n", wss_port[n]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) switch (irq[n]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) case SNDRV_AUTO_IRQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) dev_err(dev, "please specify irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) wss_config[n] |= WSS_CONFIG_IRQ_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) irq[n] = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) case 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) wss_config[n] |= WSS_CONFIG_IRQ_9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) case 10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) wss_config[n] |= WSS_CONFIG_IRQ_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) case 11:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) wss_config[n] |= WSS_CONFIG_IRQ_11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) dev_err(dev, "invalid IRQ %d\n", irq[n]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) switch (dma1[n]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) case SNDRV_AUTO_DMA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) dev_err(dev, "please specify dma1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) wss_config[n] |= WSS_CONFIG_DMA_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) wss_config[n] |= WSS_CONFIG_DMA_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) wss_config[n] |= WSS_CONFIG_DMA_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) dev_err(dev, "invalid playback DMA %d\n", dma1[n]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (dma2[n] == SNDRV_AUTO_DMA || dma2[n] == dma1[n]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) dma2[n] = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) goto mpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) wss_config[n] |= WSS_CONFIG_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) switch (dma2[n]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (dma1[n] == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) dev_err(dev, "invalid capture DMA %d\n", dma2[n]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) mpu:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) switch (mpu_port[n]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) case SNDRV_AUTO_PORT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) dev_warn(dev, "mpu_port not specified; not using MPU-401\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) mpu_port[n] = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) goto fm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) case 0x300:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) config[n] |= GALAXY_CONFIG_MPU_ENABLE | GALAXY_CONFIG_MPUA_300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) case 0x330:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) config[n] |= GALAXY_CONFIG_MPU_ENABLE | GALAXY_CONFIG_MPUA_330;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) dev_err(dev, "invalid MPU port %#lx\n", mpu_port[n]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) switch (mpu_irq[n]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) case SNDRV_AUTO_IRQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dev_warn(dev, "mpu_irq not specified: using polling mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) mpu_irq[n] = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) mpu_irq[n] = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) case 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) config[n] |= GALAXY_CONFIG_MPUIRQ_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #ifdef AZT1605
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) config[n] |= GALAXY_CONFIG_MPUIRQ_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) config[n] |= GALAXY_CONFIG_MPUIRQ_5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) config[n] |= GALAXY_CONFIG_MPUIRQ_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #ifdef AZT2316
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) case 10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) config[n] |= GALAXY_CONFIG_MPUIRQ_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) dev_err(dev, "invalid MPU IRQ %d\n", mpu_irq[n]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (mpu_irq[n] == irq[n]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) dev_err(dev, "cannot share IRQ between WSS and MPU-401\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) fm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) switch (fm_port[n]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) case SNDRV_AUTO_PORT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) dev_warn(dev, "fm_port not specified: not using OPL3\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) fm_port[n] = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) case 0x388:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) dev_err(dev, "illegal FM port %#lx\n", fm_port[n]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) config[n] |= GALAXY_CONFIG_GAME_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static int galaxy_init(struct snd_galaxy *galaxy, u8 *type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) u8 major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) u8 minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) err = dsp_reset(galaxy->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) err = dsp_get_version(galaxy->port, &major, &minor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (major != GALAXY_DSP_MAJOR || minor != GALAXY_DSP_MINOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) err = dsp_command(galaxy->port, DSP_COMMAND_GALAXY_8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) err = dsp_command(galaxy->port, GALAXY_COMMAND_GET_TYPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) err = dsp_get_byte(galaxy->port, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static int galaxy_set_mode(struct snd_galaxy *galaxy, u8 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) err = dsp_command(galaxy->port, DSP_COMMAND_GALAXY_9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) err = dsp_command(galaxy->port, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #ifdef AZT1605
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * Needed for MPU IRQ on AZT1605, but AZT2316 loses WSS again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) err = dsp_reset(galaxy->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static void galaxy_set_config(struct snd_galaxy *galaxy, u32 config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) u8 tmp = ioread8(galaxy->config_port + CONFIG_PORT_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) iowrite8(tmp | 0x80, galaxy->config_port + CONFIG_PORT_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) for (i = 0; i < GALAXY_CONFIG_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) iowrite8(config, galaxy->config_port + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) config >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) iowrite8(tmp & 0x7f, galaxy->config_port + CONFIG_PORT_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static void galaxy_config(struct snd_galaxy *galaxy, u32 config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) for (i = GALAXY_CONFIG_SIZE; i; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) u8 tmp = ioread8(galaxy->config_port + i - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) galaxy->config = (galaxy->config << 8) | tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) config |= galaxy->config & GALAXY_CONFIG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) galaxy_set_config(galaxy, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static int galaxy_wss_config(struct snd_galaxy *galaxy, u8 wss_config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) err = wss_detect(galaxy->wss_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) wss_set_config(galaxy->wss_port, wss_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) err = galaxy_set_mode(galaxy, GALAXY_MODE_WSS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static void snd_galaxy_free(struct snd_card *card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct snd_galaxy *galaxy = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (galaxy->wss_port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) wss_set_config(galaxy->wss_port, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) ioport_unmap(galaxy->wss_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) release_and_free_resource(galaxy->res_wss_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (galaxy->config_port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) galaxy_set_config(galaxy, galaxy->config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) ioport_unmap(galaxy->config_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) release_and_free_resource(galaxy->res_config_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (galaxy->port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) ioport_unmap(galaxy->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) release_and_free_resource(galaxy->res_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static int snd_galaxy_probe(struct device *dev, unsigned int n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct snd_galaxy *galaxy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct snd_wss *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) u8 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) err = snd_card_new(dev, index[n], id[n], THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) sizeof(*galaxy), &card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) card->private_free = snd_galaxy_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) galaxy = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) galaxy->res_port = request_region(port[n], 16, DRV_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (!galaxy->res_port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) dev_err(dev, "could not grab ports %#lx-%#lx\n", port[n],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) port[n] + 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) galaxy->port = ioport_map(port[n], 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) err = galaxy_init(galaxy, &type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) dev_err(dev, "did not find a Sound Galaxy at %#lx\n", port[n]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) dev_info(dev, "Sound Galaxy (type %d) found at %#lx\n", type, port[n]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) galaxy->res_config_port = request_region(port[n] + GALAXY_PORT_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 16, DRV_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (!galaxy->res_config_port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) dev_err(dev, "could not grab ports %#lx-%#lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) port[n] + GALAXY_PORT_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) port[n] + GALAXY_PORT_CONFIG + 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) galaxy->config_port = ioport_map(port[n] + GALAXY_PORT_CONFIG, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) galaxy_config(galaxy, config[n]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) galaxy->res_wss_port = request_region(wss_port[n], 4, DRV_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (!galaxy->res_wss_port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) dev_err(dev, "could not grab ports %#lx-%#lx\n", wss_port[n],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) wss_port[n] + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) galaxy->wss_port = ioport_map(wss_port[n], 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) err = galaxy_wss_config(galaxy, wss_config[n]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) dev_err(dev, "could not configure WSS\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) strcpy(card->driver, DRV_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) strcpy(card->shortname, DRV_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) sprintf(card->longname, "%s at %#lx/%#lx, irq %d, dma %d/%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) card->shortname, port[n], wss_port[n], irq[n], dma1[n],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) dma2[n]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) err = snd_wss_create(card, wss_port[n] + 4, -1, irq[n], dma1[n],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) dma2[n], WSS_HW_DETECT, 0, &chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) err = snd_wss_pcm(chip, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) err = snd_wss_mixer(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) err = snd_wss_timer(chip, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (mpu_port[n] >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) err = snd_mpu401_uart_new(card, 0, MPU401_HW_MPU401,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) mpu_port[n], 0, mpu_irq[n], NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (fm_port[n] >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) struct snd_opl3 *opl3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) err = snd_opl3_create(card, fm_port[n], fm_port[n] + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) OPL3_HW_AUTO, 0, &opl3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) dev_err(dev, "no OPL device at %#lx\n", fm_port[n]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) err = snd_opl3_timer_new(opl3, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) err = snd_opl3_hwdep_new(opl3, 0, 1, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) err = snd_card_register(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) dev_set_drvdata(dev, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static int snd_galaxy_remove(struct device *dev, unsigned int n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) snd_card_free(dev_get_drvdata(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static struct isa_driver snd_galaxy_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .match = snd_galaxy_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .probe = snd_galaxy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .remove = snd_galaxy_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .name = DEV_NAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) module_isa_driver(snd_galaxy_driver, SNDRV_CARDS);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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