^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for C-Media CMI8328-based soundcards, such as AudioExcel AV500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2012 Ondrej Zary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * AudioExcel AV500 card consists of:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * - CMI8328 - main chip (SB Pro emulation, gameport, OPL3, MPU401, CD-ROM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * - CS4231A - WSS codec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * - Dream SAM9233+GMS950400+RAM+ROM: Wavetable MIDI, connected to MPU401
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/isa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/gameport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <sound/wss.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <sound/opl3.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <sound/mpu401.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SNDRV_LEGACY_FIND_FREE_IOPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SNDRV_LEGACY_FIND_FREE_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SNDRV_LEGACY_FIND_FREE_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) MODULE_AUTHOR("Ondrej Zary <linux@rainbow-software.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) MODULE_DESCRIPTION("C-Media CMI8328");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #if IS_ENABLED(CONFIG_GAMEPORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SUPPORT_JOYSTICK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* I/O port is configured by jumpers on the card to one of these */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static const int cmi8328_ports[] = { 0x530, 0xe80, 0xf40, 0x604 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CMI8328_MAX ARRAY_SIZE(cmi8328_ports)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static int index[CMI8328_MAX] = {[0 ... (CMI8328_MAX-1)] = -1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static char *id[CMI8328_MAX] = {[0 ... (CMI8328_MAX-1)] = NULL};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static long port[CMI8328_MAX] = {[0 ... (CMI8328_MAX-1)] = SNDRV_AUTO_PORT};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static int irq[CMI8328_MAX] = {[0 ... (CMI8328_MAX-1)] = SNDRV_AUTO_IRQ};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static int dma1[CMI8328_MAX] = {[0 ... (CMI8328_MAX-1)] = SNDRV_AUTO_DMA};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static int dma2[CMI8328_MAX] = {[0 ... (CMI8328_MAX-1)] = SNDRV_AUTO_DMA};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static long mpuport[CMI8328_MAX] = {[0 ... (CMI8328_MAX-1)] = SNDRV_AUTO_PORT};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static int mpuirq[CMI8328_MAX] = {[0 ... (CMI8328_MAX-1)] = SNDRV_AUTO_IRQ};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #ifdef SUPPORT_JOYSTICK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static bool gameport[CMI8328_MAX] = {[0 ... (CMI8328_MAX-1)] = true};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) module_param_array(index, int, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MODULE_PARM_DESC(index, "Index value for CMI8328 soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) module_param_array(id, charp, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) MODULE_PARM_DESC(id, "ID string for CMI8328 soundcard.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) module_param_hw_array(port, long, ioport, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MODULE_PARM_DESC(port, "Port # for CMI8328 driver.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) module_param_hw_array(irq, int, irq, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MODULE_PARM_DESC(irq, "IRQ # for CMI8328 driver.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) module_param_hw_array(dma1, int, dma, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MODULE_PARM_DESC(dma1, "DMA1 for CMI8328 driver.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) module_param_hw_array(dma2, int, dma, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) MODULE_PARM_DESC(dma2, "DMA2 for CMI8328 driver.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) module_param_hw_array(mpuport, long, ioport, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) MODULE_PARM_DESC(mpuport, "MPU-401 port # for CMI8328 driver.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) module_param_hw_array(mpuirq, int, irq, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) MODULE_PARM_DESC(mpuirq, "IRQ # for CMI8328 MPU-401 port.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #ifdef SUPPORT_JOYSTICK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) module_param_array(gameport, bool, NULL, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) MODULE_PARM_DESC(gameport, "Enable gameport.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct snd_cmi8328 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u16 port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u8 cfg[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u8 wss_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct snd_wss *wss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #ifdef SUPPORT_JOYSTICK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct gameport *gameport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* CMI8328 configuration registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CFG1 0x61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CFG1_SB_DISABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CFG1_GAMEPORT (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * bit 0: SB: 0=enabled, 1=disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * bit 1: gameport: 0=disabled, 1=enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * bits 2-4: SB IRQ: 001=3, 010=5, 011=7, 100=9, 101=10, 110=11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * bits 5-6: SB DMA: 00=disabled (when SB disabled), 01=DMA0, 10=DMA1, 11=DMA3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * bit 7: SB port: 0=0x220, 1=0x240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CFG2 0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CFG2_MPU_ENABLE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * bits 0-1: CD-ROM mode: 00=disabled, 01=Panasonic, 10=Sony/Mitsumi/Wearnes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) 11=IDE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * bit 2: MPU401: 0=disabled, 1=enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * bits 3-4: MPU401 IRQ: 00=3, 01=5, 10=7, 11=9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * bits 5-7: MPU401 port: 000=0x300, 001=0x310, 010=0x320, 011=0x330, 100=0x332,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 101=0x334, 110=0x336
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CFG3 0x63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * bits 0-2: CD-ROM IRQ: 000=disabled, 001=3, 010=5, 011=7, 100=9, 101=10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 110=11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * bits 3-4: CD-ROM DMA: 00=disabled, 01=DMA0, 10=DMA1, 11=DMA3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * bits 5-7: CD-ROM port: 000=0x300, 001=0x310, 010=0x320, 011=0x330, 100=0x340,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 101=0x350, 110=0x360, 111=0x370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static u8 snd_cmi8328_cfg_read(u16 port, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) outb(0x43, port + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) outb(0x21, port + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) outb(reg, port + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return inb(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static void snd_cmi8328_cfg_write(u16 port, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) outb(0x43, port + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) outb(0x21, port + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) outb(reg, port + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) outb(val, port + 3); /* yes, value goes to the same port as index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static void snd_cmi8328_cfg_save(u16 port, u8 cfg[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) cfg[0] = snd_cmi8328_cfg_read(port, CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) cfg[1] = snd_cmi8328_cfg_read(port, CFG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) cfg[2] = snd_cmi8328_cfg_read(port, CFG3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static void snd_cmi8328_cfg_restore(u16 port, u8 cfg[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) snd_cmi8328_cfg_write(port, CFG1, cfg[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) snd_cmi8328_cfg_write(port, CFG2, cfg[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) snd_cmi8328_cfg_write(port, CFG3, cfg[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static int snd_cmi8328_mixer(struct snd_wss *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct snd_ctl_elem_id id1, id2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) card = chip->card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) memset(&id1, 0, sizeof(id1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) memset(&id2, 0, sizeof(id2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) id1.iface = id2.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* rename AUX0 switch to CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) strcpy(id1.name, "Aux Playback Switch");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) strcpy(id2.name, "CD Playback Switch");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) err = snd_ctl_rename_id(card, &id1, &id2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) snd_printk(KERN_ERR "error renaming control\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* rename AUX0 volume to CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) strcpy(id1.name, "Aux Playback Volume");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) strcpy(id2.name, "CD Playback Volume");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) err = snd_ctl_rename_id(card, &id1, &id2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) snd_printk(KERN_ERR "error renaming control\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* rename AUX1 switch to Synth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) strcpy(id1.name, "Aux Playback Switch");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) id1.index = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) strcpy(id2.name, "Synth Playback Switch");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) err = snd_ctl_rename_id(card, &id1, &id2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) snd_printk(KERN_ERR "error renaming control\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* rename AUX1 volume to Synth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) strcpy(id1.name, "Aux Playback Volume");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) id1.index = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) strcpy(id2.name, "Synth Playback Volume");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) err = snd_ctl_rename_id(card, &id1, &id2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) snd_printk(KERN_ERR "error renaming control\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* find index of an item in "-1"-ended array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static int array_find(const int array[], int item)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) for (i = 0; array[i] != -1; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (array[i] == item)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* the same for long */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static int array_find_l(const long array[], long item)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) for (i = 0; array[i] != -1; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (array[i] == item)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static int snd_cmi8328_probe(struct device *pdev, unsigned int ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct snd_opl3 *opl3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct snd_cmi8328 *cmi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #ifdef SUPPORT_JOYSTICK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) int err, pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static const long mpu_ports[] = { 0x330, 0x300, 0x310, 0x320, 0x332, 0x334,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 0x336, -1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static const u8 mpu_port_bits[] = { 3, 0, 1, 2, 4, 5, 6 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static const int mpu_irqs[] = { 9, 7, 5, 3, -1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static const u8 mpu_irq_bits[] = { 3, 2, 1, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static const int irqs[] = { 9, 10, 11, 7, -1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static const u8 irq_bits[] = { 2, 3, 4, 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static const int dma1s[] = { 3, 1, 0, -1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static const u8 dma_bits[] = { 3, 2, 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static const int dma2s[][2] = { {1, -1}, {0, -1}, {-1, -1}, {0, -1} };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u16 port = cmi8328_ports[ndev];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* 0xff is invalid configuration (but settable - hope it isn't set) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (snd_cmi8328_cfg_read(port, CFG1) == 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* the SB disable bit must NEVER EVER be cleared or the WSS dies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) snd_cmi8328_cfg_write(port, CFG1, CFG1_SB_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (snd_cmi8328_cfg_read(port, CFG1) != CFG1_SB_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* disable everything first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) snd_cmi8328_cfg_write(port, CFG2, 0); /* disable CDROM and MPU401 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) snd_cmi8328_cfg_write(port, CFG3, 0); /* disable CDROM IRQ and DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (irq[ndev] == SNDRV_AUTO_IRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) irq[ndev] = snd_legacy_find_free_irq(irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (irq[ndev] < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) snd_printk(KERN_ERR "unable to find a free IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (dma1[ndev] == SNDRV_AUTO_DMA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) dma1[ndev] = snd_legacy_find_free_dma(dma1s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (dma1[ndev] < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) snd_printk(KERN_ERR "unable to find a free DMA1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (dma2[ndev] == SNDRV_AUTO_DMA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) dma2[ndev] = snd_legacy_find_free_dma(dma2s[dma1[ndev] % 4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (dma2[ndev] < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) snd_printk(KERN_WARNING "unable to find a free DMA2, full-duplex will not work\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) dma2[ndev] = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* configure WSS IRQ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) pos = array_find(irqs, irq[ndev]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (pos < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) snd_printk(KERN_ERR "invalid IRQ %d\n", irq[ndev]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) val = irq_bits[pos] << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* ...and DMA... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) pos = array_find(dma1s, dma1[ndev]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (pos < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) snd_printk(KERN_ERR "invalid DMA1 %d\n", dma1[ndev]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) val |= dma_bits[pos];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* ...and DMA2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (dma2[ndev] >= 0 && dma1[ndev] != dma2[ndev]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) pos = array_find(dma2s[dma1[ndev]], dma2[ndev]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (pos < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) snd_printk(KERN_ERR "invalid DMA2 %d\n", dma2[ndev]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) val |= 0x04; /* enable separate capture DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) outb(val, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) err = snd_card_new(pdev, index[ndev], id[ndev], THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) sizeof(struct snd_cmi8328), &card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) cmi = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) cmi->card = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) cmi->port = port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) cmi->wss_cfg = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) err = snd_wss_create(card, port + 4, -1, irq[ndev], dma1[ndev],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) dma2[ndev], WSS_HW_DETECT, 0, &cmi->wss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) err = snd_wss_pcm(cmi->wss, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) err = snd_wss_mixer(cmi->wss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) err = snd_cmi8328_mixer(cmi->wss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (snd_wss_timer(cmi->wss, 0) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) snd_printk(KERN_WARNING "error initializing WSS timer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (mpuport[ndev] == SNDRV_AUTO_PORT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) mpuport[ndev] = snd_legacy_find_free_ioport(mpu_ports, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (mpuport[ndev] < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) snd_printk(KERN_ERR "unable to find a free MPU401 port\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (mpuirq[ndev] == SNDRV_AUTO_IRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) mpuirq[ndev] = snd_legacy_find_free_irq(mpu_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (mpuirq[ndev] < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) snd_printk(KERN_ERR "unable to find a free MPU401 IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* enable and configure MPU401 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (mpuport[ndev] > 0 && mpuirq[ndev] > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) val = CFG2_MPU_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) pos = array_find_l(mpu_ports, mpuport[ndev]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (pos < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) snd_printk(KERN_WARNING "invalid MPU401 port 0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) mpuport[ndev]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) val |= mpu_port_bits[pos] << 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) pos = array_find(mpu_irqs, mpuirq[ndev]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (pos < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) snd_printk(KERN_WARNING "invalid MPU401 IRQ %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) mpuirq[ndev]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) val |= mpu_irq_bits[pos] << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) snd_cmi8328_cfg_write(port, CFG2, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (snd_mpu401_uart_new(card, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) MPU401_HW_MPU401, mpuport[ndev],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 0, mpuirq[ndev], NULL) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) snd_printk(KERN_ERR "error initializing MPU401\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* OPL3 is hardwired to 0x388 and cannot be disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (snd_opl3_create(card, 0x388, 0x38a, OPL3_HW_AUTO, 0, &opl3) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) snd_printk(KERN_ERR "error initializing OPL3\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (snd_opl3_hwdep_new(opl3, 0, 1, NULL) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) snd_printk(KERN_WARNING "error initializing OPL3 hwdep\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) strcpy(card->driver, "CMI8328");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) strcpy(card->shortname, "C-Media CMI8328");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) sprintf(card->longname, "%s at 0x%lx, irq %d, dma %d,%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) card->shortname, cmi->wss->port, irq[ndev], dma1[ndev],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) (dma2[ndev] >= 0) ? dma2[ndev] : dma1[ndev]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) dev_set_drvdata(pdev, card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) err = snd_card_register(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #ifdef SUPPORT_JOYSTICK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (!gameport[ndev])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* gameport is hardwired to 0x200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) res = request_region(0x200, 8, "CMI8328 gameport");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) snd_printk(KERN_WARNING "unable to allocate gameport I/O port\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct gameport *gp = cmi->gameport = gameport_allocate_port();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (!cmi->gameport)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) release_and_free_resource(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) gameport_set_name(gp, "CMI8328 Gameport");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) gameport_set_phys(gp, "%s/gameport0", dev_name(pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) gameport_set_dev_parent(gp, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) gp->io = 0x200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) gameport_set_port_data(gp, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* Enable gameport */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) snd_cmi8328_cfg_write(port, CFG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) CFG1_SB_DISABLE | CFG1_GAMEPORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) gameport_register_port(gp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static int snd_cmi8328_remove(struct device *pdev, unsigned int dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct snd_card *card = dev_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct snd_cmi8328 *cmi = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #ifdef SUPPORT_JOYSTICK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (cmi->gameport) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct resource *res = gameport_get_port_data(cmi->gameport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) gameport_unregister_port(cmi->gameport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) release_and_free_resource(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* disable everything */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) snd_cmi8328_cfg_write(cmi->port, CFG1, CFG1_SB_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) snd_cmi8328_cfg_write(cmi->port, CFG2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) snd_cmi8328_cfg_write(cmi->port, CFG3, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) snd_card_free(card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static int snd_cmi8328_suspend(struct device *pdev, unsigned int n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct snd_card *card = dev_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct snd_cmi8328 *cmi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (!card) /* ignore absent devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) cmi = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) snd_cmi8328_cfg_save(cmi->port, cmi->cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) cmi->wss->suspend(cmi->wss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static int snd_cmi8328_resume(struct device *pdev, unsigned int n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct snd_card *card = dev_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct snd_cmi8328 *cmi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (!card) /* ignore absent devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) cmi = card->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) snd_cmi8328_cfg_restore(cmi->port, cmi->cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) outb(cmi->wss_cfg, cmi->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) cmi->wss->resume(cmi->wss);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) snd_power_change_state(card, SNDRV_CTL_POWER_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static struct isa_driver snd_cmi8328_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .probe = snd_cmi8328_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .remove = snd_cmi8328_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .suspend = snd_cmi8328_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .resume = snd_cmi8328_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .name = "cmi8328"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) module_isa_driver(snd_cmi8328_driver, CMI8328_MAX);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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