^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Routines for control of the AK4117 via 4-wire serial interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * IEC958 (S/PDIF) receiver by Asahi Kasei
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <sound/control.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <sound/ak4117.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <sound/asoundef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) MODULE_DESCRIPTION("AK4117 IEC958 (S/PDIF) receiver by Asahi Kasei");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define AK4117_ADDR 0x00 /* fixed address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static void snd_ak4117_timer(struct timer_list *t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static void reg_write(struct ak4117 *ak4117, unsigned char reg, unsigned char val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) ak4117->write(ak4117->private_data, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) if (reg < sizeof(ak4117->regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) ak4117->regmap[reg] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static inline unsigned char reg_read(struct ak4117 *ak4117, unsigned char reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) return ak4117->read(ak4117->private_data, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static void reg_dump(struct ak4117 *ak4117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) printk(KERN_DEBUG "AK4117 REG DUMP:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) for (i = 0; i < 0x1b; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) printk(KERN_DEBUG "reg[%02x] = %02x (%02x)\n", i, reg_read(ak4117, i), i < sizeof(ak4117->regmap) ? ak4117->regmap[i] : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static void snd_ak4117_free(struct ak4117 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) del_timer_sync(&chip->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) kfree(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static int snd_ak4117_dev_free(struct snd_device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct ak4117 *chip = device->device_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) snd_ak4117_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) int snd_ak4117_create(struct snd_card *card, ak4117_read_t *read, ak4117_write_t *write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) const unsigned char pgm[5], void *private_data, struct ak4117 **r_ak4117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct ak4117 *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned char reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static const struct snd_device_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .dev_free = snd_ak4117_dev_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) chip = kzalloc(sizeof(*chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (chip == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) spin_lock_init(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) chip->card = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) chip->read = read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) chip->write = write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) chip->private_data = private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) timer_setup(&chip->timer, snd_ak4117_timer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) for (reg = 0; reg < 5; reg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) chip->regmap[reg] = pgm[reg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) snd_ak4117_reinit(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) chip->rcs0 = reg_read(chip, AK4117_REG_RCS0) & ~(AK4117_QINT | AK4117_CINT | AK4117_STC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) chip->rcs1 = reg_read(chip, AK4117_REG_RCS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) chip->rcs2 = reg_read(chip, AK4117_REG_RCS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if ((err = snd_device_new(card, SNDRV_DEV_CODEC, chip, &ops)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) goto __fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (r_ak4117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) *r_ak4117 = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) __fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) snd_ak4117_free(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) void snd_ak4117_reg_write(struct ak4117 *chip, unsigned char reg, unsigned char mask, unsigned char val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (reg >= 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) reg_write(chip, reg, (chip->regmap[reg] & ~mask) | val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) void snd_ak4117_reinit(struct ak4117 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned char old = chip->regmap[AK4117_REG_PWRDN], reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) del_timer(&chip->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) chip->init = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* bring the chip to reset state and powerdown state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) reg_write(chip, AK4117_REG_PWRDN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) udelay(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* release reset, but leave powerdown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) reg_write(chip, AK4117_REG_PWRDN, (old | AK4117_RST) & ~AK4117_PWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) udelay(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) for (reg = 1; reg < 5; reg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) reg_write(chip, reg, chip->regmap[reg]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* release powerdown, everything is initialized now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) reg_write(chip, AK4117_REG_PWRDN, old | AK4117_RST | AK4117_PWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) chip->init = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) mod_timer(&chip->timer, 1 + jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static unsigned int external_rate(unsigned char rcs1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) switch (rcs1 & (AK4117_FS0|AK4117_FS1|AK4117_FS2|AK4117_FS3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) case AK4117_FS_32000HZ: return 32000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) case AK4117_FS_44100HZ: return 44100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) case AK4117_FS_48000HZ: return 48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) case AK4117_FS_88200HZ: return 88200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) case AK4117_FS_96000HZ: return 96000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) case AK4117_FS_176400HZ: return 176400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) case AK4117_FS_192000HZ: return 192000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) default: return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int snd_ak4117_in_error_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) uinfo->value.integer.max = LONG_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static int snd_ak4117_in_error_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct ak4117 *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) spin_lock_irq(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ucontrol->value.integer.value[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) chip->errors[kcontrol->private_value];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) chip->errors[kcontrol->private_value] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) spin_unlock_irq(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define snd_ak4117_in_bit_info snd_ctl_boolean_mono_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static int snd_ak4117_in_bit_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct ak4117 *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned char reg = kcontrol->private_value & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned char bit = (kcontrol->private_value >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned char inv = (kcontrol->private_value >> 31) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ucontrol->value.integer.value[0] = ((reg_read(chip, reg) & (1 << bit)) ? 1 : 0) ^ inv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int snd_ak4117_rx_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) uinfo->value.integer.max = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int snd_ak4117_rx_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct ak4117 *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) ucontrol->value.integer.value[0] = (chip->regmap[AK4117_REG_IO] & AK4117_IPS) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static int snd_ak4117_rx_put(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct ak4117 *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u8 old_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) spin_lock_irq(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) old_val = chip->regmap[AK4117_REG_IO];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) change = !!ucontrol->value.integer.value[0] != ((old_val & AK4117_IPS) ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (change)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) reg_write(chip, AK4117_REG_IO, (old_val & ~AK4117_IPS) | (ucontrol->value.integer.value[0] ? AK4117_IPS : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) spin_unlock_irq(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int snd_ak4117_rate_info(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) uinfo->value.integer.max = 192000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static int snd_ak4117_rate_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct ak4117 *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ucontrol->value.integer.value[0] = external_rate(reg_read(chip, AK4117_REG_RCS1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static int snd_ak4117_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static int snd_ak4117_spdif_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct ak4117 *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) for (i = 0; i < AK4117_REG_RXCSB_SIZE; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ucontrol->value.iec958.status[i] = reg_read(chip, AK4117_REG_RXCSB0 + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static int snd_ak4117_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) uinfo->count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static int snd_ak4117_spdif_mask_get(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) memset(ucontrol->value.iec958.status, 0xff, AK4117_REG_RXCSB_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static int snd_ak4117_spdif_pinfo(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) uinfo->value.integer.min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) uinfo->value.integer.max = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) uinfo->count = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static int snd_ak4117_spdif_pget(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct ak4117 *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) unsigned short tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) ucontrol->value.integer.value[0] = 0xf8f2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) ucontrol->value.integer.value[1] = 0x4e1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) tmp = reg_read(chip, AK4117_REG_Pc0) | (reg_read(chip, AK4117_REG_Pc1) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) ucontrol->value.integer.value[2] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) tmp = reg_read(chip, AK4117_REG_Pd0) | (reg_read(chip, AK4117_REG_Pd1) << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ucontrol->value.integer.value[3] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static int snd_ak4117_spdif_qinfo(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) uinfo->count = AK4117_REG_QSUB_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static int snd_ak4117_spdif_qget(struct snd_kcontrol *kcontrol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct snd_ctl_elem_value *ucontrol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct ak4117 *chip = snd_kcontrol_chip(kcontrol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) for (i = 0; i < AK4117_REG_QSUB_SIZE; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ucontrol->value.bytes.data[i] = reg_read(chip, AK4117_REG_QSUB_ADDR + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* Don't forget to change AK4117_CONTROLS define!!! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static const struct snd_kcontrol_new snd_ak4117_iec958_controls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .name = "IEC958 Parity Errors",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .info = snd_ak4117_in_error_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .get = snd_ak4117_in_error_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .private_value = AK4117_PARITY_ERRORS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .name = "IEC958 V-Bit Errors",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .info = snd_ak4117_in_error_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .get = snd_ak4117_in_error_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .private_value = AK4117_V_BIT_ERRORS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .name = "IEC958 C-CRC Errors",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .info = snd_ak4117_in_error_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .get = snd_ak4117_in_error_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .private_value = AK4117_CCRC_ERRORS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .name = "IEC958 Q-CRC Errors",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .info = snd_ak4117_in_error_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .get = snd_ak4117_in_error_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .private_value = AK4117_QCRC_ERRORS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .name = "IEC958 External Rate",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .info = snd_ak4117_rate_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .get = snd_ak4117_rate_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .name = SNDRV_CTL_NAME_IEC958("",CAPTURE,MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .access = SNDRV_CTL_ELEM_ACCESS_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .info = snd_ak4117_spdif_mask_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .get = snd_ak4117_spdif_mask_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .name = SNDRV_CTL_NAME_IEC958("",CAPTURE,DEFAULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .info = snd_ak4117_spdif_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .get = snd_ak4117_spdif_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .name = "IEC958 Preamble Capture Default",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .info = snd_ak4117_spdif_pinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .get = snd_ak4117_spdif_pget,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .name = "IEC958 Q-subcode Capture Default",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .info = snd_ak4117_spdif_qinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .get = snd_ak4117_spdif_qget,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .name = "IEC958 Audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .info = snd_ak4117_in_bit_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .get = snd_ak4117_in_bit_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .private_value = (1<<31) | (3<<8) | AK4117_REG_RCS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .name = "IEC958 Non-PCM Bitstream",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .info = snd_ak4117_in_bit_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .get = snd_ak4117_in_bit_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .private_value = (5<<8) | AK4117_REG_RCS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .name = "IEC958 DTS Bitstream",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .info = snd_ak4117_in_bit_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .get = snd_ak4117_in_bit_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .private_value = (6<<8) | AK4117_REG_RCS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .iface = SNDRV_CTL_ELEM_IFACE_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .name = "AK4117 Input Select",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .info = snd_ak4117_rx_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .get = snd_ak4117_rx_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .put = snd_ak4117_rx_put,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) int snd_ak4117_build(struct ak4117 *ak4117, struct snd_pcm_substream *cap_substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct snd_kcontrol *kctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (snd_BUG_ON(!cap_substream))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ak4117->substream = cap_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) for (idx = 0; idx < AK4117_CONTROLS; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) kctl = snd_ctl_new1(&snd_ak4117_iec958_controls[idx], ak4117);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (kctl == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) kctl->id.device = cap_substream->pcm->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) kctl->id.subdevice = cap_substream->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) err = snd_ctl_add(ak4117->card, kctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ak4117->kctls[idx] = kctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) int snd_ak4117_external_rate(struct ak4117 *ak4117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) unsigned char rcs1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) rcs1 = reg_read(ak4117, AK4117_REG_RCS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return external_rate(rcs1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) int snd_ak4117_check_rate_and_errors(struct ak4117 *ak4117, unsigned int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct snd_pcm_runtime *runtime = ak4117->substream ? ak4117->substream->runtime : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) unsigned long _flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) int res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) unsigned char rcs0, rcs1, rcs2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) unsigned char c0, c1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) rcs1 = reg_read(ak4117, AK4117_REG_RCS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (flags & AK4117_CHECK_NO_STAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) goto __rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) rcs0 = reg_read(ak4117, AK4117_REG_RCS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) rcs2 = reg_read(ak4117, AK4117_REG_RCS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) // printk(KERN_DEBUG "AK IRQ: rcs0 = 0x%x, rcs1 = 0x%x, rcs2 = 0x%x\n", rcs0, rcs1, rcs2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) spin_lock_irqsave(&ak4117->lock, _flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (rcs0 & AK4117_PAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) ak4117->errors[AK4117_PARITY_ERRORS]++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (rcs0 & AK4117_V)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) ak4117->errors[AK4117_V_BIT_ERRORS]++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (rcs2 & AK4117_CCRC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) ak4117->errors[AK4117_CCRC_ERRORS]++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (rcs2 & AK4117_QCRC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) ak4117->errors[AK4117_QCRC_ERRORS]++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) c0 = (ak4117->rcs0 & (AK4117_QINT | AK4117_CINT | AK4117_STC | AK4117_AUDION | AK4117_AUTO | AK4117_UNLCK)) ^
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) (rcs0 & (AK4117_QINT | AK4117_CINT | AK4117_STC | AK4117_AUDION | AK4117_AUTO | AK4117_UNLCK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) c1 = (ak4117->rcs1 & (AK4117_DTSCD | AK4117_NPCM | AK4117_PEM | 0x0f)) ^
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) (rcs1 & (AK4117_DTSCD | AK4117_NPCM | AK4117_PEM | 0x0f));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) ak4117->rcs0 = rcs0 & ~(AK4117_QINT | AK4117_CINT | AK4117_STC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) ak4117->rcs1 = rcs1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ak4117->rcs2 = rcs2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) spin_unlock_irqrestore(&ak4117->lock, _flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (rcs0 & AK4117_PAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) snd_ctl_notify(ak4117->card, SNDRV_CTL_EVENT_MASK_VALUE, &ak4117->kctls[0]->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (rcs0 & AK4117_V)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) snd_ctl_notify(ak4117->card, SNDRV_CTL_EVENT_MASK_VALUE, &ak4117->kctls[1]->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (rcs2 & AK4117_CCRC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) snd_ctl_notify(ak4117->card, SNDRV_CTL_EVENT_MASK_VALUE, &ak4117->kctls[2]->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (rcs2 & AK4117_QCRC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) snd_ctl_notify(ak4117->card, SNDRV_CTL_EVENT_MASK_VALUE, &ak4117->kctls[3]->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* rate change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (c1 & 0x0f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) snd_ctl_notify(ak4117->card, SNDRV_CTL_EVENT_MASK_VALUE, &ak4117->kctls[4]->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if ((c1 & AK4117_PEM) | (c0 & AK4117_CINT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) snd_ctl_notify(ak4117->card, SNDRV_CTL_EVENT_MASK_VALUE, &ak4117->kctls[6]->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (c0 & AK4117_QINT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) snd_ctl_notify(ak4117->card, SNDRV_CTL_EVENT_MASK_VALUE, &ak4117->kctls[8]->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (c0 & AK4117_AUDION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) snd_ctl_notify(ak4117->card, SNDRV_CTL_EVENT_MASK_VALUE, &ak4117->kctls[9]->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (c1 & AK4117_NPCM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) snd_ctl_notify(ak4117->card, SNDRV_CTL_EVENT_MASK_VALUE, &ak4117->kctls[10]->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (c1 & AK4117_DTSCD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) snd_ctl_notify(ak4117->card, SNDRV_CTL_EVENT_MASK_VALUE, &ak4117->kctls[11]->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (ak4117->change_callback && (c0 | c1) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) ak4117->change_callback(ak4117, c0, c1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) __rate:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* compare rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) res = external_rate(rcs1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (!(flags & AK4117_CHECK_NO_RATE) && runtime && runtime->rate != res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) snd_pcm_stream_lock_irqsave(ak4117->substream, _flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (snd_pcm_running(ak4117->substream)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) // printk(KERN_DEBUG "rate changed (%i <- %i)\n", runtime->rate, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) snd_pcm_stop(ak4117->substream, SNDRV_PCM_STATE_DRAINING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) wake_up(&runtime->sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) res = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) snd_pcm_stream_unlock_irqrestore(ak4117->substream, _flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static void snd_ak4117_timer(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct ak4117 *chip = from_timer(chip, t, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (chip->init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) snd_ak4117_check_rate_and_errors(chip, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) mod_timer(&chip->timer, 1 + jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) EXPORT_SYMBOL(snd_ak4117_create);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) EXPORT_SYMBOL(snd_ak4117_reg_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) EXPORT_SYMBOL(snd_ak4117_reinit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) EXPORT_SYMBOL(snd_ak4117_build);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) EXPORT_SYMBOL(snd_ak4117_external_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) EXPORT_SYMBOL(snd_ak4117_check_rate_and_errors);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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