^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * HD-audio stream operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <sound/hdaudio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <sound/hda_register.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "trace.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * snd_hdac_get_stream_stripe_ctl - get stripe control value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * @bus: HD-audio core bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * @substream: PCM substream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) unsigned int channels = runtime->channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) rate = runtime->rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) bits_per_sample = runtime->sample_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) max_sdo_lines, value, sdo_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* T_AZA_GCAP_NSDO is 1:2 bitfields in GCAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) max_sdo_lines = snd_hdac_chip_readl(bus, GCAP) & AZX_GCAP_NSDO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* following is from HD audio spec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) for (sdo_line = max_sdo_lines; sdo_line > 0; sdo_line >>= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) if (rate > 48000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) value = (channels * bits_per_sample *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) (rate / 48000)) / sdo_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) value = (channels * bits_per_sample) / sdo_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) if (value >= bus->sdo_limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* stripe value: 0 for 1SDO, 1 for 2SDO, 2 for 4SDO lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return sdo_line >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) EXPORT_SYMBOL_GPL(snd_hdac_get_stream_stripe_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * snd_hdac_stream_init - initialize each stream (aka device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * @bus: HD-audio core bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * @azx_dev: HD-audio core stream object to initialize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * @idx: stream index number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * @direction: stream direction (SNDRV_PCM_STREAM_PLAYBACK or SNDRV_PCM_STREAM_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * @tag: the tag id to assign
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * Assign the starting bdl address to each stream (device) and initialize.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) int idx, int direction, int tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) azx_dev->bus = bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) azx_dev->sd_addr = bus->remap_addr + (0x20 * idx + 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) azx_dev->sd_int_sta_mask = 1 << idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) azx_dev->index = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) azx_dev->direction = direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) azx_dev->stream_tag = tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) snd_hdac_dsp_lock_init(azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) list_add_tail(&azx_dev->list, &bus->stream_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) EXPORT_SYMBOL_GPL(snd_hdac_stream_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * snd_hdac_stream_start - start a stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * @azx_dev: HD-audio core stream to start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * @fresh_start: false = wallclock timestamp relative to period wallclock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * Start a stream, set start_wallclk and set the running flag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct hdac_bus *bus = azx_dev->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int stripe_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) trace_snd_hdac_stream_start(bus, azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) azx_dev->start_wallclk = snd_hdac_chip_readl(bus, WALLCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (!fresh_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) azx_dev->start_wallclk -= azx_dev->period_wallclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* enable SIE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) snd_hdac_chip_updatel(bus, INTCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) 1 << azx_dev->index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) 1 << azx_dev->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* set stripe control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (azx_dev->stripe) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (azx_dev->substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) stripe_ctl = snd_hdac_get_stream_stripe_ctl(bus, azx_dev->substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) stripe_ctl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) stripe_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* set DMA start and interrupt mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) snd_hdac_stream_updateb(azx_dev, SD_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 0, SD_CTL_DMA_START | SD_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) azx_dev->running = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) EXPORT_SYMBOL_GPL(snd_hdac_stream_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * snd_hdac_stream_clear - stop a stream DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * @azx_dev: HD-audio core stream to stop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) void snd_hdac_stream_clear(struct hdac_stream *azx_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) snd_hdac_stream_updateb(azx_dev, SD_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) SD_CTL_DMA_START | SD_INT_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (azx_dev->stripe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) azx_dev->running = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) EXPORT_SYMBOL_GPL(snd_hdac_stream_clear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * snd_hdac_stream_stop - stop a stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * @azx_dev: HD-audio core stream to stop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * Stop a stream DMA and disable stream interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) void snd_hdac_stream_stop(struct hdac_stream *azx_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) trace_snd_hdac_stream_stop(azx_dev->bus, azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) snd_hdac_stream_clear(azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* disable SIE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) snd_hdac_chip_updatel(azx_dev->bus, INTCTL, 1 << azx_dev->index, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) EXPORT_SYMBOL_GPL(snd_hdac_stream_stop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * snd_hdac_stream_reset - reset a stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * @azx_dev: HD-audio core stream to reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) void snd_hdac_stream_reset(struct hdac_stream *azx_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) unsigned char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) int dma_run_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) snd_hdac_stream_clear(azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) dma_run_state = snd_hdac_stream_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) udelay(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) timeout = 300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) val = snd_hdac_stream_readb(azx_dev, SD_CTL) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) SD_CTL_STREAM_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) } while (--timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (azx_dev->bus->dma_stop_delay && dma_run_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) udelay(azx_dev->bus->dma_stop_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) val &= ~SD_CTL_STREAM_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) snd_hdac_stream_writeb(azx_dev, SD_CTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) udelay(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) timeout = 300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* waiting for hardware to report that the stream is out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) val = snd_hdac_stream_readb(azx_dev, SD_CTL) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) SD_CTL_STREAM_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (!val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) } while (--timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* reset first position - may not be synced with hw at this time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (azx_dev->posbuf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) *azx_dev->posbuf = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) EXPORT_SYMBOL_GPL(snd_hdac_stream_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * snd_hdac_stream_setup - set up the SD for streaming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * @azx_dev: HD-audio core stream to set up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int snd_hdac_stream_setup(struct hdac_stream *azx_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct hdac_bus *bus = azx_dev->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct snd_pcm_runtime *runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (azx_dev->substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) runtime = azx_dev->substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) runtime = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* make sure the run bit is zero for SD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) snd_hdac_stream_clear(azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* program the stream_tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) val = snd_hdac_stream_readl(azx_dev, SD_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) val = (val & ~SD_CTL_STREAM_TAG_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (!bus->snoop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) val |= SD_CTL_TRAFFIC_PRIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) snd_hdac_stream_writel(azx_dev, SD_CTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* program the length of samples in cyclic buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) snd_hdac_stream_writel(azx_dev, SD_CBL, azx_dev->bufsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* program the stream format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* this value needs to be the same as the one programmed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) snd_hdac_stream_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* program the stream LVI (last valid index) of the BDL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) snd_hdac_stream_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* program the BDL address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* lower BDL address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) snd_hdac_stream_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* upper BDL address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) snd_hdac_stream_writel(azx_dev, SD_BDLPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) upper_32_bits(azx_dev->bdl.addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* enable the position buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (bus->use_posbuf && bus->posbuf.addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (!(snd_hdac_chip_readl(bus, DPLBASE) & AZX_DPLBASE_ENABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) snd_hdac_chip_writel(bus, DPLBASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) (u32)bus->posbuf.addr | AZX_DPLBASE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* set the interrupt enable bits in the descriptor control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) snd_hdac_stream_updatel(azx_dev, SD_CTL, 0, SD_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) azx_dev->fifo_size = snd_hdac_stream_readw(azx_dev, SD_FIFOSIZE) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* when LPIB delay correction gives a small negative value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * we ignore it; currently set the threshold statically to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * 64 frames
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (runtime && runtime->period_size > 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) azx_dev->delay_negative_threshold =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) -frames_to_bytes(runtime, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) azx_dev->delay_negative_threshold = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* wallclk has 24Mhz clock source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (runtime)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) azx_dev->period_wallclk = (((runtime->period_size * 24000) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) runtime->rate) * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) EXPORT_SYMBOL_GPL(snd_hdac_stream_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * snd_hdac_stream_cleanup - cleanup a stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * @azx_dev: HD-audio core stream to clean up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) azx_dev->bufsize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) azx_dev->period_bytes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) azx_dev->format_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) EXPORT_SYMBOL_GPL(snd_hdac_stream_cleanup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * snd_hdac_stream_assign - assign a stream for the PCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * @bus: HD-audio core bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * @substream: PCM substream to assign
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * Look for an unused stream for the given PCM substream, assign it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * and return the stream object. If no stream is free, returns NULL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * The function tries to keep using the same stream object when it's used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * beforehand. Also, when bus->reverse_assign flag is set, the last free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * or matching entry is returned. This is needed for some strange codecs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct snd_pcm_substream *substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct hdac_stream *azx_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct hdac_stream *res = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* make a non-zero unique key for the substream */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int key = (substream->pcm->device << 16) | (substream->number << 2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) (substream->stream + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) spin_lock_irq(&bus->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) list_for_each_entry(azx_dev, &bus->stream_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (azx_dev->direction != substream->stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (azx_dev->opened)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (azx_dev->assigned_key == key) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) res = azx_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (!res || bus->reverse_assign)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) res = azx_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) res->opened = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) res->running = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) res->assigned_key = key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) res->substream = substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) spin_unlock_irq(&bus->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) EXPORT_SYMBOL_GPL(snd_hdac_stream_assign);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * snd_hdac_stream_release - release the assigned stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * @azx_dev: HD-audio core stream to release
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * Release the stream that has been assigned by snd_hdac_stream_assign().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) void snd_hdac_stream_release(struct hdac_stream *azx_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct hdac_bus *bus = azx_dev->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) spin_lock_irq(&bus->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) azx_dev->opened = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) azx_dev->running = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) azx_dev->substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) spin_unlock_irq(&bus->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) EXPORT_SYMBOL_GPL(snd_hdac_stream_release);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * snd_hdac_get_stream - return hdac_stream based on stream_tag and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * @bus: HD-audio core bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * @dir: direction for the stream to be found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * @stream_tag: stream tag for stream to be found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) int dir, int stream_tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct hdac_stream *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) list_for_each_entry(s, &bus->stream_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (s->direction == dir && s->stream_tag == stream_tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) EXPORT_SYMBOL_GPL(snd_hdac_get_stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * set up a BDL entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static int setup_bdle(struct hdac_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct snd_dma_buffer *dmab,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct hdac_stream *azx_dev, __le32 **bdlp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) int ofs, int size, int with_ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) __le32 *bdl = *bdlp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) while (size > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) dma_addr_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) int chunk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) addr = snd_sgbuf_get_addr(dmab, ofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* program the address field of the BDL entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) bdl[0] = cpu_to_le32((u32)addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) bdl[1] = cpu_to_le32(upper_32_bits(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* program the size field of the BDL entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* one BDLE cannot cross 4K boundary on CTHDA chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (bus->align_bdle_4k) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u32 remain = 0x1000 - (ofs & 0xfff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (chunk > remain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) chunk = remain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) bdl[2] = cpu_to_le32(chunk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* program the IOC to enable interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * only when the whole fragment is processed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) size -= chunk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) bdl += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) azx_dev->frags++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) ofs += chunk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) *bdlp = bdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * snd_hdac_stream_setup_periods - set up BDL entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * @azx_dev: HD-audio core stream to set up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * Set up the buffer descriptor table of the given stream based on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * period and buffer sizes of the assigned PCM substream.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct hdac_bus *bus = azx_dev->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct snd_pcm_substream *substream = azx_dev->substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct snd_pcm_runtime *runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) __le32 *bdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) int i, ofs, periods, period_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) int pos_adj, pos_align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* reset BDL address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) period_bytes = azx_dev->period_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) periods = azx_dev->bufsize / period_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* program the initial BDL entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) bdl = (__le32 *)azx_dev->bdl.area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ofs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) azx_dev->frags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) pos_adj = bus->bdl_pos_adj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (!azx_dev->no_period_wakeup && pos_adj > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) pos_align = pos_adj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (!pos_adj)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) pos_adj = pos_align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) pos_align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) pos_adj = frames_to_bytes(runtime, pos_adj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (pos_adj >= period_bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dev_warn(bus->dev, "Too big adjustment %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) pos_adj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) pos_adj = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) azx_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) &bdl, ofs, pos_adj, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (ofs < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) pos_adj = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) for (i = 0; i < periods; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (i == periods - 1 && pos_adj)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) azx_dev, &bdl, ofs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) period_bytes - pos_adj, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) azx_dev, &bdl, ofs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) period_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) !azx_dev->no_period_wakeup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (ofs < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) dev_err(bus->dev, "Too many BDL entries: buffer=%d, period=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) azx_dev->bufsize, period_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_periods);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * snd_hdac_stream_set_params - set stream parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * @azx_dev: HD-audio core stream for which parameters are to be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * @format_val: format value parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * Setup the HD-audio core stream parameters from substream of the stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * and passed format value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) int snd_hdac_stream_set_params(struct hdac_stream *azx_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) unsigned int format_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) unsigned int bufsize, period_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct snd_pcm_substream *substream = azx_dev->substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct snd_pcm_runtime *runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (!substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) runtime = substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) bufsize = snd_pcm_lib_buffer_bytes(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) period_bytes = snd_pcm_lib_period_bytes(substream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (bufsize != azx_dev->bufsize ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) period_bytes != azx_dev->period_bytes ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) format_val != azx_dev->format_val ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) azx_dev->bufsize = bufsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) azx_dev->period_bytes = period_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) azx_dev->format_val = format_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) azx_dev->no_period_wakeup = runtime->no_period_wakeup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) err = snd_hdac_stream_setup_periods(azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) EXPORT_SYMBOL_GPL(snd_hdac_stream_set_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static u64 azx_cc_read(const struct cyclecounter *cc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct hdac_stream *azx_dev = container_of(cc, struct hdac_stream, cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return snd_hdac_chip_readl(azx_dev->bus, WALLCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static void azx_timecounter_init(struct hdac_stream *azx_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) bool force, u64 last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct timecounter *tc = &azx_dev->tc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct cyclecounter *cc = &azx_dev->cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) u64 nsec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) cc->read = azx_cc_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) cc->mask = CLOCKSOURCE_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * Converting from 24 MHz to ns means applying a 125/3 factor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * To avoid any saturation issues in intermediate operations,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * the 125 factor is applied first. The division is applied
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * last after reading the timecounter value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * Applying the 1/3 factor as part of the multiplication
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * requires at least 20 bits for a decent precision, however
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * overflows occur after about 4 hours or less, not a option.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) cc->mult = 125; /* saturation after 195 years */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) cc->shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) nsec = 0; /* audio time is elapsed time since trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) timecounter_init(tc, cc, nsec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (force) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * force timecounter to use predefined value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * used for synchronized starts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) tc->cycle_last = last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * snd_hdac_stream_timecounter_init - initialize time counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * @azx_dev: HD-audio core stream (master stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * @streams: bit flags of streams to set up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * Initializes the time counter of streams marked by the bit flags (each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * bit corresponds to the stream index).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * The trigger timestamp of PCM substream assigned to the given stream is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * updated accordingly, too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) unsigned int streams)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) struct hdac_bus *bus = azx_dev->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct snd_pcm_runtime *runtime = azx_dev->substream->runtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) struct hdac_stream *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) bool inited = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) u64 cycle_last = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) list_for_each_entry(s, &bus->stream_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (streams & (1 << i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) azx_timecounter_init(s, inited, cycle_last);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (!inited) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) inited = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) cycle_last = s->tc.cycle_last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) snd_pcm_gettime(runtime, &runtime->trigger_tstamp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) runtime->trigger_tstamp_latched = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) EXPORT_SYMBOL_GPL(snd_hdac_stream_timecounter_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * snd_hdac_stream_sync_trigger - turn on/off stream sync register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * @azx_dev: HD-audio core stream (master stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * @set: true = set, false = clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * @streams: bit flags of streams to sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * @reg: the stream sync register address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) unsigned int streams, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) struct hdac_bus *bus = azx_dev->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (!reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) reg = AZX_REG_SSYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) val = _snd_hdac_chip_readl(bus, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) val |= streams;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) val &= ~streams;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) _snd_hdac_chip_writel(bus, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) EXPORT_SYMBOL_GPL(snd_hdac_stream_sync_trigger);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * snd_hdac_stream_sync - sync with start/strop trigger operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * @azx_dev: HD-audio core stream (master stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * @start: true = start, false = stop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * @streams: bit flags of streams to sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * For @start = true, wait until all FIFOs get ready.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * For @start = false, wait until all RUN bits are cleared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) unsigned int streams)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) struct hdac_bus *bus = azx_dev->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) int i, nwait, timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) struct hdac_stream *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) for (timeout = 5000; timeout; timeout--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) nwait = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) list_for_each_entry(s, &bus->stream_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (!(streams & (1 << i++)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /* check FIFO gets ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (!(snd_hdac_stream_readb(s, SD_STS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) SD_STS_FIFO_READY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) nwait++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /* check RUN bit is cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (snd_hdac_stream_readb(s, SD_CTL) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) SD_CTL_DMA_START) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) nwait++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * Perform stream reset if DMA RUN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * bit not cleared within given timeout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (timeout == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) snd_hdac_stream_reset(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (!nwait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) EXPORT_SYMBOL_GPL(snd_hdac_stream_sync);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #ifdef CONFIG_SND_HDA_DSP_LOADER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * snd_hdac_dsp_prepare - prepare for DSP loading
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * @azx_dev: HD-audio core stream used for DSP loading
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) * @format: HD-audio stream format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) * @byte_size: data chunk byte size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) * @bufp: allocated buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) * Allocate the buffer for the given size and set up the given stream for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) * DSP loading. Returns the stream tag (>= 0), or a negative error code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) unsigned int byte_size, struct snd_dma_buffer *bufp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) struct hdac_bus *bus = azx_dev->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) __le32 *bdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) snd_hdac_dsp_lock(azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) spin_lock_irq(&bus->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (azx_dev->running || azx_dev->locked) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) spin_unlock_irq(&bus->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) azx_dev->locked = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) spin_unlock_irq(&bus->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) byte_size, bufp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) goto err_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) azx_dev->substream = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) azx_dev->bufsize = byte_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) azx_dev->period_bytes = byte_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) azx_dev->format_val = format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) snd_hdac_stream_reset(azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /* reset BDL address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) azx_dev->frags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) bdl = (__le32 *)azx_dev->bdl.area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) err = setup_bdle(bus, bufp, azx_dev, &bdl, 0, byte_size, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) snd_hdac_stream_setup(azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) snd_hdac_dsp_unlock(azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return azx_dev->stream_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) snd_dma_free_pages(bufp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) err_alloc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) spin_lock_irq(&bus->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) azx_dev->locked = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) spin_unlock_irq(&bus->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) snd_hdac_dsp_unlock(azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) EXPORT_SYMBOL_GPL(snd_hdac_dsp_prepare);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * snd_hdac_dsp_trigger - start / stop DSP loading
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) * @azx_dev: HD-audio core stream used for DSP loading
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) * @start: trigger start or stop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) snd_hdac_stream_start(azx_dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) snd_hdac_stream_stop(azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) EXPORT_SYMBOL_GPL(snd_hdac_dsp_trigger);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) * snd_hdac_dsp_cleanup - clean up the stream from DSP loading to normal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) * @azx_dev: HD-audio core stream used for DSP loading
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) * @dmab: buffer used by DSP loading
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) struct snd_dma_buffer *dmab)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) struct hdac_bus *bus = azx_dev->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (!dmab->area || !azx_dev->locked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) snd_hdac_dsp_lock(azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /* reset BDL address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) azx_dev->bufsize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) azx_dev->period_bytes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) azx_dev->format_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) snd_dma_free_pages(dmab);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) dmab->area = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) spin_lock_irq(&bus->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) azx_dev->locked = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) spin_unlock_irq(&bus->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) snd_hdac_dsp_unlock(azx_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) EXPORT_SYMBOL_GPL(snd_hdac_dsp_cleanup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #endif /* CONFIG_SND_HDA_DSP_LOADER */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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