^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * HD-audio core bus driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <sound/hdaudio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "local.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "trace.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static void snd_hdac_bus_process_unsol_events(struct work_struct *work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) static const struct hdac_bus_ops default_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) .command = snd_hdac_bus_send_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) .get_response = snd_hdac_bus_get_response,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * snd_hdac_bus_init - initialize a HD-audio bas bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * @bus: the pointer to bus object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * @dev: device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * @ops: bus verb operators
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * Returns 0 if successful, or a negative error code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) int snd_hdac_bus_init(struct hdac_bus *bus, struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) const struct hdac_bus_ops *ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) memset(bus, 0, sizeof(*bus));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) bus->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) if (ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) bus->ops = ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) bus->ops = &default_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) bus->dma_type = SNDRV_DMA_TYPE_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) INIT_LIST_HEAD(&bus->stream_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) INIT_LIST_HEAD(&bus->codec_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) INIT_WORK(&bus->unsol_work, snd_hdac_bus_process_unsol_events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) spin_lock_init(&bus->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) mutex_init(&bus->cmd_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) mutex_init(&bus->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) INIT_LIST_HEAD(&bus->hlink_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) init_waitqueue_head(&bus->rirb_wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) bus->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * Default value of '8' is as per the HD audio specification (Rev 1.0a).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Following relation is used to derive STRIPE control value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * For sample rate <= 48K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * { ((num_channels * bits_per_sample) / number of SDOs) >= 8 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * For sample rate > 48K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * { ((num_channels * bits_per_sample * rate/48000) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * number of SDOs) >= 8 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) bus->sdo_limit = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) EXPORT_SYMBOL_GPL(snd_hdac_bus_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * snd_hdac_bus_exit - clean up a HD-audio bas bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * @bus: the pointer to bus object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) void snd_hdac_bus_exit(struct hdac_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) WARN_ON(!list_empty(&bus->stream_list));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) WARN_ON(!list_empty(&bus->codec_list));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) cancel_work_sync(&bus->unsol_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) EXPORT_SYMBOL_GPL(snd_hdac_bus_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * snd_hdac_bus_exec_verb - execute a HD-audio verb on the given bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * @bus: bus object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * @addr: the HDAC device address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * @cmd: HD-audio encoded verb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * @res: pointer to store the response, NULL if performing asynchronously
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * Returns 0 if successful, or a negative error code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int snd_hdac_bus_exec_verb(struct hdac_bus *bus, unsigned int addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned int cmd, unsigned int *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) mutex_lock(&bus->cmd_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) err = snd_hdac_bus_exec_verb_unlocked(bus, addr, cmd, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) mutex_unlock(&bus->cmd_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * snd_hdac_bus_exec_verb_unlocked - unlocked version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * @bus: bus object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * @addr: the HDAC device address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * @cmd: HD-audio encoded verb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * @res: pointer to store the response, NULL if performing asynchronously
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * Returns 0 if successful, or a negative error code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int snd_hdac_bus_exec_verb_unlocked(struct hdac_bus *bus, unsigned int addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned int cmd, unsigned int *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (cmd == ~0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) *res = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) else if (bus->sync_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) res = &tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) trace_hda_send_cmd(bus, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) err = bus->ops->command(bus, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (err != -EAGAIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* process pending verbs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) err = bus->ops->get_response(bus, addr, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (!err && res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) err = bus->ops->get_response(bus, addr, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) trace_hda_get_response(bus, addr, *res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) EXPORT_SYMBOL_GPL(snd_hdac_bus_exec_verb_unlocked);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * snd_hdac_bus_queue_event - add an unsolicited event to queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * @bus: the BUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * @res: unsolicited event (lower 32bit of RIRB entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * @res_ex: codec addr and flags (upper 32bit or RIRB entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * Adds the given event to the queue. The events are processed in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * the workqueue asynchronously. Call this function in the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * hanlder when RIRB receives an unsolicited event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) void snd_hdac_bus_queue_event(struct hdac_bus *bus, u32 res, u32 res_ex)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) unsigned int wp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (!bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) trace_hda_unsol_event(bus, res, res_ex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) wp = (bus->unsol_wp + 1) % HDA_UNSOL_QUEUE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) bus->unsol_wp = wp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) wp <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) bus->unsol_queue[wp] = res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) bus->unsol_queue[wp + 1] = res_ex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) schedule_work(&bus->unsol_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * process queued unsolicited events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static void snd_hdac_bus_process_unsol_events(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct hdac_bus *bus = container_of(work, struct hdac_bus, unsol_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct hdac_device *codec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct hdac_driver *drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned int rp, caddr, res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) spin_lock_irq(&bus->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) while (bus->unsol_rp != bus->unsol_wp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) rp = (bus->unsol_rp + 1) % HDA_UNSOL_QUEUE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) bus->unsol_rp = rp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) rp <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) res = bus->unsol_queue[rp];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) caddr = bus->unsol_queue[rp + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (!(caddr & (1 << 4))) /* no unsolicited event? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) codec = bus->caddr_tbl[caddr & 0x0f];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (!codec || !codec->dev.driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) spin_unlock_irq(&bus->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) drv = drv_to_hdac_driver(codec->dev.driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (drv->unsol_event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) drv->unsol_event(codec, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) spin_lock_irq(&bus->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) spin_unlock_irq(&bus->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * snd_hdac_bus_add_device - Add a codec to bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * @bus: HDA core bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * @codec: HDA core device to add
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * Adds the given codec to the list in the bus. The caddr_tbl array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * and codec_powered bits are updated, as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * Returns zero if success, or a negative error code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) int snd_hdac_bus_add_device(struct hdac_bus *bus, struct hdac_device *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (bus->caddr_tbl[codec->addr]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) dev_err(bus->dev, "address 0x%x is already occupied\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) codec->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) list_add_tail(&codec->list, &bus->codec_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) bus->caddr_tbl[codec->addr] = codec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) set_bit(codec->addr, &bus->codec_powered);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) bus->num_codecs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * snd_hdac_bus_remove_device - Remove a codec from bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * @bus: HDA core bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * @codec: HDA core device to remove
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) void snd_hdac_bus_remove_device(struct hdac_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct hdac_device *codec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) WARN_ON(bus != codec->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (list_empty(&codec->list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) list_del_init(&codec->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) bus->caddr_tbl[codec->addr] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) clear_bit(codec->addr, &bus->codec_powered);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) bus->num_codecs--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) flush_work(&bus->unsol_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #ifdef CONFIG_SND_HDA_ALIGNED_MMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* Helpers for aligned read/write of mmio space, for Tegra */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) unsigned int snd_hdac_aligned_read(void __iomem *addr, unsigned int mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) void __iomem *aligned_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) (void __iomem *)((unsigned long)(addr) & ~0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) unsigned int v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) v = readl(aligned_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return (v >> shift) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) EXPORT_SYMBOL_GPL(snd_hdac_aligned_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) void snd_hdac_aligned_write(unsigned int val, void __iomem *addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) unsigned int mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) void __iomem *aligned_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) (void __iomem *)((unsigned long)(addr) & ~0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) unsigned int shift = ((unsigned long)(addr) & 0x3) << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) unsigned int v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) v = readl(aligned_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) v &= ~(mask << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) v |= val << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) writel(v, aligned_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) EXPORT_SYMBOL_GPL(snd_hdac_aligned_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #endif /* CONFIG_SND_HDA_ALIGNED_MMIO */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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