^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * tascam-stream.c - a part of driver for TASCAM FireWire series
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2015 Takashi Sakamoto
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include "tascam.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define CLOCK_STATUS_MASK 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define CLOCK_CONFIG_MASK 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CALLBACK_TIMEOUT 500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) static int get_clock(struct snd_tscm *tscm, u32 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) int trial = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) __be32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) while (trial++ < 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) err = snd_fw_transaction(tscm->unit, TCODE_READ_QUADLET_REQUEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) TSCM_ADDR_BASE + TSCM_OFFSET_CLOCK_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) ®, sizeof(reg), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) *data = be32_to_cpu(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) if (*data & CLOCK_STATUS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) // In intermediate state after changing clock status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) // Still in the intermediate state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) if (trial >= 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static int set_clock(struct snd_tscm *tscm, unsigned int rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) enum snd_tscm_clock clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) __be32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) err = get_clock(tscm, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) data &= CLOCK_CONFIG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (rate > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) data &= 0x000000ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Base rate. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if ((rate % 44100) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) data |= 0x00000100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Multiplier. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (rate / 44100 == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) data |= 0x00008000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) } else if ((rate % 48000) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) data |= 0x00000200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Multiplier. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (rate / 48000 == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) data |= 0x00008000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (clock != INT_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) data &= 0x0000ff00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) data |= clock + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) reg = cpu_to_be32(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) TSCM_ADDR_BASE + TSCM_OFFSET_CLOCK_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ®, sizeof(reg), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (data & 0x00008000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) reg = cpu_to_be32(0x0000001a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) reg = cpu_to_be32(0x0000000d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) TSCM_ADDR_BASE + TSCM_OFFSET_MULTIPLEX_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ®, sizeof(reg), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int snd_tscm_stream_get_rate(struct snd_tscm *tscm, unsigned int *rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) err = get_clock(tscm, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) data = (data & 0xff000000) >> 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Check base rate. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if ((data & 0x0f) == 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) *rate = 44100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) else if ((data & 0x0f) == 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) *rate = 48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Check multiplier. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if ((data & 0xf0) == 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) *rate *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) else if ((data & 0xf0) != 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int snd_tscm_stream_get_clock(struct snd_tscm *tscm, enum snd_tscm_clock *clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) err = get_clock(tscm, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) *clock = ((data & 0x00ff0000) >> 16) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (*clock < 0 || *clock > SND_TSCM_CLOCK_ADAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int enable_data_channels(struct snd_tscm *tscm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) __be32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) for (i = 0; i < tscm->spec->pcm_capture_analog_channels; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) data |= BIT(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (tscm->spec->has_adat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) data |= 0x0000ff00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (tscm->spec->has_spdif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) data |= 0x00030000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) reg = cpu_to_be32(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) TSCM_ADDR_BASE + TSCM_OFFSET_TX_PCM_CHANNELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ®, sizeof(reg), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) for (i = 0; i < tscm->spec->pcm_playback_analog_channels; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) data |= BIT(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (tscm->spec->has_adat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) data |= 0x0000ff00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (tscm->spec->has_spdif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) data |= 0x00030000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) reg = cpu_to_be32(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) TSCM_ADDR_BASE + TSCM_OFFSET_RX_PCM_CHANNELS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ®, sizeof(reg), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static int set_stream_formats(struct snd_tscm *tscm, unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) __be32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) // Set an option for unknown purpose.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) reg = cpu_to_be32(0x00200000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) TSCM_ADDR_BASE + TSCM_OFFSET_SET_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ®, sizeof(reg), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return enable_data_channels(tscm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static void finish_session(struct snd_tscm *tscm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) __be32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) TSCM_ADDR_BASE + TSCM_OFFSET_START_STREAMING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ®, sizeof(reg), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) TSCM_ADDR_BASE + TSCM_OFFSET_ISOC_RX_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ®, sizeof(reg), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) // Unregister channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) reg = cpu_to_be32(0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) TSCM_ADDR_BASE + TSCM_OFFSET_ISOC_TX_CH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ®, sizeof(reg), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) reg = cpu_to_be32(0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) TSCM_ADDR_BASE + TSCM_OFFSET_UNKNOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ®, sizeof(reg), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) reg = cpu_to_be32(0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) TSCM_ADDR_BASE + TSCM_OFFSET_ISOC_RX_CH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ®, sizeof(reg), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static int begin_session(struct snd_tscm *tscm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) __be32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) // Register the isochronous channel for transmitting stream.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) reg = cpu_to_be32(tscm->tx_resources.channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) TSCM_ADDR_BASE + TSCM_OFFSET_ISOC_TX_CH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ®, sizeof(reg), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) // Unknown.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) reg = cpu_to_be32(0x00000002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) TSCM_ADDR_BASE + TSCM_OFFSET_UNKNOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ®, sizeof(reg), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) // Register the isochronous channel for receiving stream.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) reg = cpu_to_be32(tscm->rx_resources.channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) TSCM_ADDR_BASE + TSCM_OFFSET_ISOC_RX_CH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ®, sizeof(reg), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) reg = cpu_to_be32(0x00000001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) TSCM_ADDR_BASE + TSCM_OFFSET_START_STREAMING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ®, sizeof(reg), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) reg = cpu_to_be32(0x00000001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) TSCM_ADDR_BASE + TSCM_OFFSET_ISOC_RX_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) ®, sizeof(reg), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) // Set an option for unknown purpose.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) reg = cpu_to_be32(0x00002000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) TSCM_ADDR_BASE + TSCM_OFFSET_SET_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ®, sizeof(reg), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) // Start multiplexing PCM samples on packets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) reg = cpu_to_be32(0x00000001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return snd_fw_transaction(tscm->unit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) TCODE_WRITE_QUADLET_REQUEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) TSCM_ADDR_BASE + TSCM_OFFSET_ISOC_TX_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) ®, sizeof(reg), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static int keep_resources(struct snd_tscm *tscm, unsigned int rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct amdtp_stream *stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct fw_iso_resources *resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (stream == &tscm->tx_stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) resources = &tscm->tx_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) resources = &tscm->rx_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) err = amdtp_tscm_set_parameters(stream, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return fw_iso_resources_allocate(resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) amdtp_stream_get_max_payload(stream),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) fw_parent_device(tscm->unit)->max_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static int init_stream(struct snd_tscm *tscm, struct amdtp_stream *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct fw_iso_resources *resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) enum amdtp_stream_direction dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) unsigned int pcm_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (s == &tscm->tx_stream) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) resources = &tscm->tx_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) dir = AMDTP_IN_STREAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) pcm_channels = tscm->spec->pcm_capture_analog_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) resources = &tscm->rx_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) dir = AMDTP_OUT_STREAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) pcm_channels = tscm->spec->pcm_playback_analog_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (tscm->spec->has_adat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) pcm_channels += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (tscm->spec->has_spdif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) pcm_channels += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) err = fw_iso_resources_init(resources, tscm->unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) err = amdtp_tscm_init(s, tscm->unit, dir, pcm_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) fw_iso_resources_free(resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static void destroy_stream(struct snd_tscm *tscm, struct amdtp_stream *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) amdtp_stream_destroy(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (s == &tscm->tx_stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) fw_iso_resources_destroy(&tscm->tx_resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) fw_iso_resources_destroy(&tscm->rx_resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) int snd_tscm_stream_init_duplex(struct snd_tscm *tscm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) err = init_stream(tscm, &tscm->tx_stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) err = init_stream(tscm, &tscm->rx_stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) destroy_stream(tscm, &tscm->tx_stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) err = amdtp_domain_init(&tscm->domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) destroy_stream(tscm, &tscm->tx_stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) destroy_stream(tscm, &tscm->rx_stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) // At bus reset, streaming is stopped and some registers are clear.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) void snd_tscm_stream_update_duplex(struct snd_tscm *tscm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) amdtp_domain_stop(&tscm->domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) amdtp_stream_pcm_abort(&tscm->tx_stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) amdtp_stream_pcm_abort(&tscm->rx_stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) // This function should be called before starting streams or after stopping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) // streams.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) void snd_tscm_stream_destroy_duplex(struct snd_tscm *tscm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) amdtp_domain_destroy(&tscm->domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) destroy_stream(tscm, &tscm->rx_stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) destroy_stream(tscm, &tscm->tx_stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) int snd_tscm_stream_reserve_duplex(struct snd_tscm *tscm, unsigned int rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) unsigned int frames_per_period,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) unsigned int frames_per_buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) unsigned int curr_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) err = snd_tscm_stream_get_rate(tscm, &curr_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (tscm->substreams_counter == 0 || rate != curr_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) amdtp_domain_stop(&tscm->domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) finish_session(tscm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) fw_iso_resources_free(&tscm->tx_resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) fw_iso_resources_free(&tscm->rx_resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) err = set_clock(tscm, rate, INT_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) err = keep_resources(tscm, rate, &tscm->tx_stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) err = keep_resources(tscm, rate, &tscm->rx_stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) fw_iso_resources_free(&tscm->tx_resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) err = amdtp_domain_set_events_per_period(&tscm->domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) frames_per_period, frames_per_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) fw_iso_resources_free(&tscm->tx_resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) fw_iso_resources_free(&tscm->rx_resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) int snd_tscm_stream_start_duplex(struct snd_tscm *tscm, unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) unsigned int generation = tscm->rx_resources.generation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (tscm->substreams_counter == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (amdtp_streaming_error(&tscm->rx_stream) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) amdtp_streaming_error(&tscm->tx_stream)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) amdtp_domain_stop(&tscm->domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) finish_session(tscm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (generation != fw_parent_device(tscm->unit)->card->generation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) err = fw_iso_resources_update(&tscm->tx_resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) err = fw_iso_resources_update(&tscm->rx_resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (!amdtp_stream_running(&tscm->rx_stream)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) int spd = fw_parent_device(tscm->unit)->max_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) err = set_stream_formats(tscm, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) err = begin_session(tscm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) err = amdtp_domain_add_stream(&tscm->domain, &tscm->rx_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) tscm->rx_resources.channel, spd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) err = amdtp_domain_add_stream(&tscm->domain, &tscm->tx_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) tscm->tx_resources.channel, spd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) err = amdtp_domain_start(&tscm->domain, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (!amdtp_stream_wait_callback(&tscm->rx_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) CALLBACK_TIMEOUT) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) !amdtp_stream_wait_callback(&tscm->tx_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) CALLBACK_TIMEOUT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) err = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) amdtp_domain_stop(&tscm->domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) finish_session(tscm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) void snd_tscm_stream_stop_duplex(struct snd_tscm *tscm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (tscm->substreams_counter == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) amdtp_domain_stop(&tscm->domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) finish_session(tscm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) fw_iso_resources_free(&tscm->tx_resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) fw_iso_resources_free(&tscm->rx_resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) void snd_tscm_stream_lock_changed(struct snd_tscm *tscm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) tscm->dev_lock_changed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) wake_up(&tscm->hwdep_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) int snd_tscm_stream_lock_try(struct snd_tscm *tscm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) spin_lock_irq(&tscm->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /* user land lock this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (tscm->dev_lock_count < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) goto end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* this is the first time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (tscm->dev_lock_count++ == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) snd_tscm_stream_lock_changed(tscm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) spin_unlock_irq(&tscm->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) void snd_tscm_stream_lock_release(struct snd_tscm *tscm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) spin_lock_irq(&tscm->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (WARN_ON(tscm->dev_lock_count <= 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) goto end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (--tscm->dev_lock_count == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) snd_tscm_stream_lock_changed(tscm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) spin_unlock_irq(&tscm->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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