^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // ff-protocol-former.c - a part of driver for RME Fireface series
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // Copyright (c) 2019 Takashi Sakamoto
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Licensed under the terms of the GNU General Public License, version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "ff.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define FORMER_REG_SYNC_STATUS 0x0000801c0000ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* For block write request. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define FORMER_REG_FETCH_PCM_FRAMES 0x0000801c0000ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define FORMER_REG_CLOCK_CONFIG 0x0000801c0004ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) static int parse_clock_bits(u32 data, unsigned int *rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) enum snd_ff_clock_src *src)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) unsigned int rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) } *rate_entry, rate_entries[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) { 32000, 0x00000002, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) { 44100, 0x00000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) { 48000, 0x00000006, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) { 64000, 0x0000000a, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) { 88200, 0x00000008, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) { 96000, 0x0000000e, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) { 128000, 0x00000012, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) { 176400, 0x00000010, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) { 192000, 0x00000016, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) enum snd_ff_clock_src src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) } *clk_entry, clk_entries[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) { SND_FF_CLOCK_SRC_ADAT1, 0x00000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) { SND_FF_CLOCK_SRC_ADAT2, 0x00000400, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) { SND_FF_CLOCK_SRC_SPDIF, 0x00000c00, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) { SND_FF_CLOCK_SRC_WORD, 0x00001000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) { SND_FF_CLOCK_SRC_LTC, 0x00001800, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) for (i = 0; i < ARRAY_SIZE(rate_entries); ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) rate_entry = rate_entries + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) if ((data & 0x0000001e) == rate_entry->mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) *rate = rate_entry->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (i == ARRAY_SIZE(rate_entries))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (data & 0x00000001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) *src = SND_FF_CLOCK_SRC_INTERNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) for (i = 0; i < ARRAY_SIZE(clk_entries); ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) clk_entry = clk_entries + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if ((data & 0x00001c00) == clk_entry->mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) *src = clk_entry->src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (i == ARRAY_SIZE(clk_entries))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static int former_get_clock(struct snd_ff *ff, unsigned int *rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) enum snd_ff_clock_src *src)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) __le32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) err = snd_fw_transaction(ff->unit, TCODE_READ_QUADLET_REQUEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) FORMER_REG_CLOCK_CONFIG, ®, sizeof(reg), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) data = le32_to_cpu(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return parse_clock_bits(data, rate, src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static int former_switch_fetching_mode(struct snd_ff *ff, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) __le32 *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) for (i = 0; i < SND_FF_STREAM_MODE_COUNT; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) count = max(count, ff->spec->pcm_playback_channels[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) reg = kcalloc(count, sizeof(__le32), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (!reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (!enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * Each quadlet is corresponding to data channels in a data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * blocks in reverse order. Precisely, quadlets for available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * data channels should be enabled. Here, I take second best
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * to fetch PCM frames from all of data channels regardless of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * stf.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) for (i = 0; i < count; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) reg[i] = cpu_to_le32(0x00000001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) err = snd_fw_transaction(ff->unit, TCODE_WRITE_BLOCK_REQUEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) FORMER_REG_FETCH_PCM_FRAMES, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) sizeof(__le32) * count, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) kfree(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static void dump_clock_config(struct snd_ff *ff, struct snd_info_buffer *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) __le32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned int rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) enum snd_ff_clock_src src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) const char *label;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) err = snd_fw_transaction(ff->unit, TCODE_READ_BLOCK_REQUEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) FORMER_REG_CLOCK_CONFIG, ®, sizeof(reg), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) data = le32_to_cpu(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) snd_iprintf(buffer, "Output S/PDIF format: %s (Emphasis: %s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) (data & 0x00000020) ? "Professional" : "Consumer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) (data & 0x00000040) ? "on" : "off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) snd_iprintf(buffer, "Optical output interface format: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) (data & 0x00000100) ? "S/PDIF" : "ADAT");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) snd_iprintf(buffer, "Word output single speed: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) (data & 0x00002000) ? "on" : "off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) snd_iprintf(buffer, "S/PDIF input interface: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) (data & 0x00000200) ? "Optical" : "Coaxial");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) err = parse_clock_bits(data, &rate, &src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) label = snd_ff_proc_get_clk_label(src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (!label)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) snd_iprintf(buffer, "Clock configuration: %d %s\n", rate, label);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static void dump_sync_status(struct snd_ff *ff, struct snd_info_buffer *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) char *const label;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u32 locked_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u32 synced_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) } *clk_entry, clk_entries[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { "WDClk", 0x40000000, 0x20000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { "S/PDIF", 0x00080000, 0x00040000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { "ADAT1", 0x00000400, 0x00001000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { "ADAT2", 0x00000800, 0x00002000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) char *const label;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) } *referred_entry, referred_entries[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { "ADAT1", 0x00000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { "ADAT2", 0x00400000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { "S/PDIF", 0x00c00000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { "WDclk", 0x01000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { "TCO", 0x01400000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned int rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) } *rate_entry, rate_entries[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { 32000, 0x02000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { 44100, 0x04000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { 48000, 0x06000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { 64000, 0x08000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { 88200, 0x0a000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { 96000, 0x0c000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { 128000, 0x0e000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) { 176400, 0x10000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) { 192000, 0x12000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) __le32 reg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u32 data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) err = snd_fw_transaction(ff->unit, TCODE_READ_BLOCK_REQUEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) FORMER_REG_SYNC_STATUS, reg, sizeof(reg), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) data[0] = le32_to_cpu(reg[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) data[1] = le32_to_cpu(reg[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) snd_iprintf(buffer, "External source detection:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) for (i = 0; i < ARRAY_SIZE(clk_entries); ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) const char *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) clk_entry = clk_entries + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (data[0] & clk_entry->locked_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (data[0] & clk_entry->synced_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) state = "sync";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) state = "lock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) state = "none";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) snd_iprintf(buffer, "%s: %s\n", clk_entry->label, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) snd_iprintf(buffer, "Referred clock:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (data[1] & 0x00000001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) snd_iprintf(buffer, "Internal\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) unsigned int rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) const char *label;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) for (i = 0; i < ARRAY_SIZE(referred_entries); ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) referred_entry = referred_entries + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if ((data[0] & 0x1e0000) == referred_entry->mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) label = referred_entry->label;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (i == ARRAY_SIZE(referred_entries))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) label = "none";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) for (i = 0; i < ARRAY_SIZE(rate_entries); ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) rate_entry = rate_entries + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if ((data[0] & 0x1e000000) == rate_entry->mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) rate = rate_entry->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (i == ARRAY_SIZE(rate_entries))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) snd_iprintf(buffer, "%s %d\n", label, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static void former_dump_status(struct snd_ff *ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct snd_info_buffer *buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) dump_clock_config(ff, buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) dump_sync_status(ff, buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static int former_fill_midi_msg(struct snd_ff *ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct snd_rawmidi_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) unsigned int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u8 *buf = (u8 *)ff->msg_buf[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) len = snd_rawmidi_transmit_peek(substream, buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) SND_FF_MAXIMIM_MIDI_QUADS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (len <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) // One quadlet includes one byte.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) for (i = len - 1; i >= 0; --i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) ff->msg_buf[port][i] = cpu_to_le32(buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ff->rx_bytes[port] = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define FF800_STF 0x0000fc88f000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define FF800_RX_PACKET_FORMAT 0x0000fc88f004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define FF800_ALLOC_TX_STREAM 0x0000fc88f008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define FF800_ISOC_COMM_START 0x0000fc88f00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define FF800_TX_S800_FLAG 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define FF800_ISOC_COMM_STOP 0x0000fc88f010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define FF800_TX_PACKET_ISOC_CH 0x0000801c0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static int allocate_tx_resources(struct snd_ff *ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) __le32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) unsigned int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned int tx_isoc_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) reg = cpu_to_le32(ff->tx_stream.data_block_quadlets);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) err = snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) FF800_ALLOC_TX_STREAM, ®, sizeof(reg), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) // Wait till the format of tx packet is available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) while (count++ < 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) err = snd_fw_transaction(ff->unit, TCODE_READ_QUADLET_REQUEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) FF800_TX_PACKET_ISOC_CH, ®, sizeof(reg), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) data = le32_to_cpu(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (data != 0xffffffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) tx_isoc_channel = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) msleep(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (count >= 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) // NOTE: this is a makeshift to start OHCI 1394 IR context in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) // channel. On the other hand, 'struct fw_iso_resources.allocated' is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) // not true and it's not deallocated at stop.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ff->tx_resources.channel = tx_isoc_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static int ff800_allocate_resources(struct snd_ff *ff, unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) __le32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) reg = cpu_to_le32(rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) err = snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) FF800_STF, ®, sizeof(reg), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) // If starting isochronous communication immediately, change of STF has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) // no effect. In this case, the communication runs based on former STF.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) // Let's sleep for a bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) // Controllers should allocate isochronous resources for rx stream.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) err = fw_iso_resources_allocate(&ff->rx_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) amdtp_stream_get_max_payload(&ff->rx_stream),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) fw_parent_device(ff->unit)->max_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) // Set isochronous channel and the number of quadlets of rx packets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) // This should be done before the allocation of tx resources to avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) // periodical noise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) data = ff->rx_stream.data_block_quadlets << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) data = (data << 8) | ff->rx_resources.channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) reg = cpu_to_le32(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) err = snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) FF800_RX_PACKET_FORMAT, ®, sizeof(reg), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return allocate_tx_resources(ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static int ff800_begin_session(struct snd_ff *ff, unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) unsigned int generation = ff->rx_resources.generation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) __le32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (generation != fw_parent_device(ff->unit)->card->generation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) int err = fw_iso_resources_update(&ff->rx_resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) reg = cpu_to_le32(0x80000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) reg |= cpu_to_le32(ff->tx_stream.data_block_quadlets);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (fw_parent_device(ff->unit)->max_speed == SCODE_800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) reg |= cpu_to_le32(FF800_TX_S800_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) FF800_ISOC_COMM_START, ®, sizeof(reg), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static void ff800_finish_session(struct snd_ff *ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) __le32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) reg = cpu_to_le32(0x80000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) FF800_ISOC_COMM_STOP, ®, sizeof(reg), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) // Fireface 800 doesn't allow drivers to register lower 4 bytes of destination
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) // address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) // A write transaction to clear registered higher 4 bytes of destination address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) // has an effect to suppress asynchronous transaction from device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static void ff800_handle_midi_msg(struct snd_ff *ff, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) __le32 *buf, size_t length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) for (i = 0; i < length / 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) u8 byte = le32_to_cpu(buf[i]) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct snd_rawmidi_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) substream = READ_ONCE(ff->tx_midi_substreams[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (substream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) snd_rawmidi_receive(substream, &byte, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) const struct snd_ff_protocol snd_ff_protocol_ff800 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .handle_midi_msg = ff800_handle_midi_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .fill_midi_msg = former_fill_midi_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .get_clock = former_get_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .switch_fetching_mode = former_switch_fetching_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .allocate_resources = ff800_allocate_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .begin_session = ff800_begin_session,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .finish_session = ff800_finish_session,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .dump_status = former_dump_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define FF400_STF 0x000080100500ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define FF400_RX_PACKET_FORMAT 0x000080100504ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define FF400_ISOC_COMM_START 0x000080100508ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define FF400_TX_PACKET_FORMAT 0x00008010050cull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define FF400_ISOC_COMM_STOP 0x000080100510ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) // Fireface 400 manages isochronous channel number in 3 bit field. Therefore,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) // we can allocate between 0 and 7 channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static int ff400_allocate_resources(struct snd_ff *ff, unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) __le32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) enum snd_ff_stream_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) // Check whether the given value is supported or not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) for (i = 0; i < CIP_SFC_COUNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (amdtp_rate_table[i] == rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (i >= CIP_SFC_COUNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) // Set the number of data blocks transferred in a second.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) reg = cpu_to_le32(rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) err = snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) FF400_STF, ®, sizeof(reg), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) err = snd_ff_stream_get_multiplier_mode(i, &mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) // Keep resources for in-stream.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ff->tx_resources.channels_mask = 0x00000000000000ffuLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) err = fw_iso_resources_allocate(&ff->tx_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) amdtp_stream_get_max_payload(&ff->tx_stream),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) fw_parent_device(ff->unit)->max_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) // Keep resources for out-stream.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) ff->rx_resources.channels_mask = 0x00000000000000ffuLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) err = fw_iso_resources_allocate(&ff->rx_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) amdtp_stream_get_max_payload(&ff->rx_stream),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) fw_parent_device(ff->unit)->max_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) fw_iso_resources_free(&ff->tx_resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static int ff400_begin_session(struct snd_ff *ff, unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) unsigned int generation = ff->rx_resources.generation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) __le32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (generation != fw_parent_device(ff->unit)->card->generation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) err = fw_iso_resources_update(&ff->tx_resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) err = fw_iso_resources_update(&ff->rx_resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) // Set isochronous channel and the number of quadlets of received
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) // packets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) reg = cpu_to_le32(((ff->rx_stream.data_block_quadlets << 3) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) ff->rx_resources.channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) err = snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) FF400_RX_PACKET_FORMAT, ®, sizeof(reg), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) // Set isochronous channel and the number of quadlets of transmitted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) // packet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) // TODO: investigate the purpose of this 0x80.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) reg = cpu_to_le32((0x80 << 24) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) (ff->tx_resources.channel << 5) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) (ff->tx_stream.data_block_quadlets));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) err = snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) FF400_TX_PACKET_FORMAT, ®, sizeof(reg), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) // Allow to transmit packets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) reg = cpu_to_le32(0x00000001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) FF400_ISOC_COMM_START, ®, sizeof(reg), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static void ff400_finish_session(struct snd_ff *ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) __le32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) reg = cpu_to_le32(0x80000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) snd_fw_transaction(ff->unit, TCODE_WRITE_QUADLET_REQUEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) FF400_ISOC_COMM_STOP, ®, sizeof(reg), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) // For Fireface 400, lower 4 bytes of destination address is configured by bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) // flag in quadlet register (little endian) at 0x'0000'801'0051c. Drivers can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) // select one of 4 options:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) // bit flags: offset of destination address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) // - 0x04000000: 0x'....'....'0000'0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) // - 0x08000000: 0x'....'....'0000'0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) // - 0x10000000: 0x'....'....'0000'0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) // - 0x20000000: 0x'....'....'0000'0180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) // Drivers can suppress the device to transfer asynchronous transactions by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) // using below 2 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) // - 0x01000000: suppress transmission
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) // - 0x02000000: suppress transmission
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) // Actually, the register is write-only and includes the other options such as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) // input attenuation. This driver allocates destination address with '0000'0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) // in its lower offset and expects userspace application to configure the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) // register for it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static void ff400_handle_midi_msg(struct snd_ff *ff, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) __le32 *buf, size_t length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) for (i = 0; i < length / 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) u32 quad = le32_to_cpu(buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) u8 byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) unsigned int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) struct snd_rawmidi_substream *substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /* Message in first port. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * This value may represent the index of this unit when the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * units are on the same IEEE 1394 bus. This driver doesn't use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) index = (quad >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (index > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) substream = READ_ONCE(ff->tx_midi_substreams[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (substream != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) byte = quad & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) snd_rawmidi_receive(substream, &byte, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /* Message in second port. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) index = (quad >> 24) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (index > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) substream = READ_ONCE(ff->tx_midi_substreams[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (substream != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) byte = (quad >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) snd_rawmidi_receive(substream, &byte, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) const struct snd_ff_protocol snd_ff_protocol_ff400 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .handle_midi_msg = ff400_handle_midi_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .fill_midi_msg = former_fill_midi_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .get_clock = former_get_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .switch_fetching_mode = former_switch_fetching_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .allocate_resources = ff400_allocate_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .begin_session = ff400_begin_session,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .finish_session = ff400_finish_session,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .dump_status = former_dump_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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