^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * digi00x.h - a part of driver for Digidesign Digi 002/003 family
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2014-2015 Takashi Sakamoto
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef SOUND_DIGI00X_H_INCLUDED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define SOUND_DIGI00X_H_INCLUDED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/compat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/firewire.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/sched/signal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <sound/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <sound/info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <sound/pcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <sound/firewire.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <sound/hwdep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <sound/rawmidi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "../lib.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "../iso-resources.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "../amdtp-stream.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct snd_dg00x {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct fw_unit *unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) bool registered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct delayed_work dwork;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct amdtp_stream tx_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct fw_iso_resources tx_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct amdtp_stream rx_stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct fw_iso_resources rx_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned int substreams_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* for uapi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) int dev_lock_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) bool dev_lock_changed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) wait_queue_head_t hwdep_wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* For asynchronous messages. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct fw_address_handler async_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Console models have additional MIDI ports for control surface. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) bool is_console;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct amdtp_domain domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DG00X_ADDR_BASE 0xffffe0000000ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DG00X_OFFSET_STREAMING_STATE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DG00X_OFFSET_STREAMING_SET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* unknown but address in host space 0x0008 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* For LSB of the address 0x000c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* unknown 0x0010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DG00X_OFFSET_MESSAGE_ADDR 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* For LSB of the address 0x0018 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* unknown 0x001c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* unknown 0x0020 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* not used 0x0024--0x00ff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DG00X_OFFSET_ISOC_CHANNELS 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* unknown 0x0104 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* unknown 0x0108 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* unknown 0x010c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DG00X_OFFSET_LOCAL_RATE 0x0110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DG00X_OFFSET_EXTERNAL_RATE 0x0114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DG00X_OFFSET_CLOCK_SOURCE 0x0118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define DG00X_OFFSET_OPT_IFACE_MODE 0x011c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* unknown 0x0120 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Mixer control on/off 0x0124 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* unknown 0x0128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define DG00X_OFFSET_DETECT_EXTERNAL 0x012c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* unknown 0x0138 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DG00X_OFFSET_MMC 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) enum snd_dg00x_rate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) SND_DG00X_RATE_44100 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) SND_DG00X_RATE_48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) SND_DG00X_RATE_88200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) SND_DG00X_RATE_96000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) SND_DG00X_RATE_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) enum snd_dg00x_clock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) SND_DG00X_CLOCK_INTERNAL = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) SND_DG00X_CLOCK_SPDIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) SND_DG00X_CLOCK_ADAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) SND_DG00X_CLOCK_WORD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) SND_DG00X_CLOCK_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) enum snd_dg00x_optical_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) SND_DG00X_OPT_IFACE_MODE_ADAT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) SND_DG00X_OPT_IFACE_MODE_SPDIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) SND_DG00X_OPT_IFACE_MODE_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define DOT_MIDI_IN_PORTS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define DOT_MIDI_OUT_PORTS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int amdtp_dot_init(struct amdtp_stream *s, struct fw_unit *unit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) enum amdtp_stream_direction dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) int amdtp_dot_set_parameters(struct amdtp_stream *s, unsigned int rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned int pcm_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) void amdtp_dot_reset(struct amdtp_stream *s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int amdtp_dot_add_pcm_hw_constraints(struct amdtp_stream *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct snd_pcm_runtime *runtime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) void amdtp_dot_midi_trigger(struct amdtp_stream *s, unsigned int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct snd_rawmidi_substream *midi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int snd_dg00x_transaction_register(struct snd_dg00x *dg00x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int snd_dg00x_transaction_reregister(struct snd_dg00x *dg00x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) void snd_dg00x_transaction_unregister(struct snd_dg00x *dg00x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) extern const unsigned int snd_dg00x_stream_rates[SND_DG00X_RATE_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) extern const unsigned int snd_dg00x_stream_pcm_channels[SND_DG00X_RATE_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) int snd_dg00x_stream_get_external_rate(struct snd_dg00x *dg00x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned int *rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) int snd_dg00x_stream_get_local_rate(struct snd_dg00x *dg00x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned int *rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int snd_dg00x_stream_set_local_rate(struct snd_dg00x *dg00x, unsigned int rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int snd_dg00x_stream_get_clock(struct snd_dg00x *dg00x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) enum snd_dg00x_clock *clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int snd_dg00x_stream_check_external_clock(struct snd_dg00x *dg00x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) bool *detect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int snd_dg00x_stream_init_duplex(struct snd_dg00x *dg00x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int snd_dg00x_stream_reserve_duplex(struct snd_dg00x *dg00x, unsigned int rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned int frames_per_period,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned int frames_per_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int snd_dg00x_stream_start_duplex(struct snd_dg00x *dg00x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) void snd_dg00x_stream_stop_duplex(struct snd_dg00x *dg00x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) void snd_dg00x_stream_update_duplex(struct snd_dg00x *dg00x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) void snd_dg00x_stream_destroy_duplex(struct snd_dg00x *dg00x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) void snd_dg00x_stream_lock_changed(struct snd_dg00x *dg00x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) int snd_dg00x_stream_lock_try(struct snd_dg00x *dg00x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) void snd_dg00x_stream_lock_release(struct snd_dg00x *dg00x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) void snd_dg00x_proc_init(struct snd_dg00x *dg00x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int snd_dg00x_create_pcm_devices(struct snd_dg00x *dg00x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int snd_dg00x_create_midi_devices(struct snd_dg00x *dg00x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int snd_dg00x_create_hwdep_device(struct snd_dg00x *dg00x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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