Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * dice-mytek.c - a part of driver for DICE based devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (c) 2018 Melvin Vermeeren
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include "dice.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) struct dice_mytek_spec {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 	unsigned int tx_pcm_chs[MAX_STREAMS][SND_DICE_RATE_MODE_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	unsigned int rx_pcm_chs[MAX_STREAMS][SND_DICE_RATE_MODE_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static const struct dice_mytek_spec stereo_192_dsd_dac = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	/* AES, TOSLINK, SPDIF, ADAT inputs on device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	.tx_pcm_chs = {{8, 8, 8}, {0, 0, 0} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	/* PCM 44.1-192, native DSD64/DSD128 to device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	.rx_pcm_chs = {{4, 4, 4}, {0, 0, 0} }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  * Mytek has a few other firewire-capable devices, though newer models appear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  * to lack the port more often than not. As I don't have access to any of them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  * they are missing here. An example is the Mytek 8x192 ADDA, which is DICE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) int snd_dice_detect_mytek_formats(struct snd_dice *dice)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	const struct dice_mytek_spec *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	dev = &stereo_192_dsd_dac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	memcpy(dice->tx_pcm_chs, dev->tx_pcm_chs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	       MAX_STREAMS * SND_DICE_RATE_MODE_COUNT * sizeof(unsigned int));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	memcpy(dice->rx_pcm_chs, dev->rx_pcm_chs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	       MAX_STREAMS * SND_DICE_RATE_MODE_COUNT * sizeof(unsigned int));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	for (i = 0; i < MAX_STREAMS; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		dice->tx_midi_ports[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		dice->rx_midi_ports[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }