Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #ifndef SOUND_FIREWIRE_DICE_INTERFACE_H_INCLUDED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #define SOUND_FIREWIRE_DICE_INTERFACE_H_INCLUDED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * DICE device interface definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Generally, all registers can be read like memory, i.e., with quadlet read or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * block read transactions with at least quadlet-aligned offset and length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * Writes are not allowed except where noted; quadlet-sized registers must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * written with a quadlet write transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * All values are in big endian.  The DICE firmware runs on a little-endian CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * and just byte-swaps _all_ quadlets on the bus, so values without endianness
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * (e.g. strings) get scrambled and must be byte-swapped again by the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * Streaming is handled by the "DICE driver" interface.  Its registers are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * located in this private address space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define DICE_PRIVATE_SPACE		0xffffe0000000uLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * The registers are organized in several sections, which are organized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * separately to allow them to be extended individually.  Whether a register is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * supported can be detected by checking its offset against its section's size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * The section offset values are relative to DICE_PRIVATE_SPACE; the offset/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * size values are measured in quadlets.  Read-only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define DICE_GLOBAL_OFFSET		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define DICE_GLOBAL_SIZE		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define DICE_TX_OFFSET			0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define DICE_TX_SIZE			0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define DICE_RX_OFFSET			0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define DICE_RX_SIZE			0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define DICE_EXT_SYNC_OFFSET		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define DICE_EXT_SYNC_SIZE		0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define DICE_UNUSED2_OFFSET		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define DICE_UNUSED2_SIZE		0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  * Global settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  * Stores the full 64-bit address (node ID and offset in the node's address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  * space) where the device will send notifications.  Must be changed with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  * a compare/swap transaction by the owner.  This register is automatically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  * cleared on a bus reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define GLOBAL_OWNER			0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define  OWNER_NO_OWNER			0xffff000000000000uLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define  OWNER_NODE_SHIFT		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  * A bitmask with asynchronous events; read-only.  When any event(s) happen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  * the bits of previous events are cleared, and the value of this register is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  * also written to the address stored in the owner register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define GLOBAL_NOTIFICATION		0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) /* Some registers in the Rx/Tx sections may have changed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define  NOTIFY_RX_CFG_CHG		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define  NOTIFY_TX_CFG_CHG		0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) /* Lock status of the current clock source may have changed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define  NOTIFY_LOCK_CHG		0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) /* Write to the clock select register has been finished. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define  NOTIFY_CLOCK_ACCEPTED		0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) /* Lock status of some clock source has changed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define  NOTIFY_EXT_STATUS		0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) /* Other bits may be used for device-specific events. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  * A name that can be customized for each device; read/write.  Padded with zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  * bytes.  Quadlets are byte-swapped.  The encoding is whatever the host driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  * happens to be using.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define GLOBAL_NICK_NAME		0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define  NICK_NAME_SIZE			64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85)  * The current sample rate and clock source; read/write.  Whether a clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86)  * source or sample rate is supported is device-specific; the internal clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87)  * source is always available.  Low/mid/high = up to 48/96/192 kHz.  This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88)  * register can be changed even while streams are running.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define GLOBAL_CLOCK_SELECT		0x04c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define  CLOCK_SOURCE_MASK		0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define  CLOCK_SOURCE_AES1		0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define  CLOCK_SOURCE_AES2		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define  CLOCK_SOURCE_AES3		0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define  CLOCK_SOURCE_AES4		0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define  CLOCK_SOURCE_AES_ANY		0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define  CLOCK_SOURCE_ADAT		0x00000005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define  CLOCK_SOURCE_TDIF		0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define  CLOCK_SOURCE_WC		0x00000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define  CLOCK_SOURCE_ARX1		0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define  CLOCK_SOURCE_ARX2		0x00000009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define  CLOCK_SOURCE_ARX3		0x0000000a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define  CLOCK_SOURCE_ARX4		0x0000000b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define  CLOCK_SOURCE_INTERNAL		0x0000000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define  CLOCK_RATE_MASK		0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define  CLOCK_RATE_32000		0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define  CLOCK_RATE_44100		0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define  CLOCK_RATE_48000		0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define  CLOCK_RATE_88200		0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define  CLOCK_RATE_96000		0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define  CLOCK_RATE_176400		0x00000500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define  CLOCK_RATE_192000		0x00000600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define  CLOCK_RATE_ANY_LOW		0x00000700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define  CLOCK_RATE_ANY_MID		0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define  CLOCK_RATE_ANY_HIGH		0x00000900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define  CLOCK_RATE_NONE		0x00000a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define  CLOCK_RATE_SHIFT		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)  * Enable streaming; read/write.  Writing a non-zero value (re)starts all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)  * streams that have a valid iso channel set; zero stops all streams.  The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)  * streams' parameters must be configured before starting.  This register is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)  * automatically cleared on a bus reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define GLOBAL_ENABLE			0x050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)  * Status of the sample clock; read-only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define GLOBAL_STATUS			0x054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* The current clock source is locked. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define  STATUS_SOURCE_LOCKED		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* The actual sample rate; CLOCK_RATE_32000-_192000 or _NONE. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define  STATUS_NOMINAL_RATE_MASK	0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)  * Status of all clock sources; read-only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define GLOBAL_EXTENDED_STATUS		0x058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)  * The _LOCKED bits always show the current status; any change generates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)  * a notification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define  EXT_STATUS_AES1_LOCKED		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define  EXT_STATUS_AES2_LOCKED		0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define  EXT_STATUS_AES3_LOCKED		0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define  EXT_STATUS_AES4_LOCKED		0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define  EXT_STATUS_ADAT_LOCKED		0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define  EXT_STATUS_TDIF_LOCKED		0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define  EXT_STATUS_ARX1_LOCKED		0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define  EXT_STATUS_ARX2_LOCKED		0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define  EXT_STATUS_ARX3_LOCKED		0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define  EXT_STATUS_ARX4_LOCKED		0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define  EXT_STATUS_WC_LOCKED		0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)  * The _SLIP bits do not generate notifications; a set bit indicates that an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)  * error occurred since the last time when this register was read with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)  * a quadlet read transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define  EXT_STATUS_AES1_SLIP		0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define  EXT_STATUS_AES2_SLIP		0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define  EXT_STATUS_AES3_SLIP		0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define  EXT_STATUS_AES4_SLIP		0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define  EXT_STATUS_ADAT_SLIP		0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define  EXT_STATUS_TDIF_SLIP		0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define  EXT_STATUS_ARX1_SLIP		0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define  EXT_STATUS_ARX2_SLIP		0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define  EXT_STATUS_ARX3_SLIP		0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define  EXT_STATUS_ARX4_SLIP		0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define  EXT_STATUS_WC_SLIP		0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)  * The measured rate of the current clock source, in Hz; read-only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define GLOBAL_SAMPLE_RATE		0x05c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)  * Some old firmware versions do not have the following global registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)  * Windows drivers produced by TCAT lost backward compatibility in its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)  * early release because they can handle firmware only which supports the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)  * following registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)  * The version of the DICE driver specification that this device conforms to;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)  * read-only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define GLOBAL_VERSION			0x060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)  * Supported sample rates and clock sources; read-only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define GLOBAL_CLOCK_CAPABILITIES	0x064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define  CLOCK_CAP_RATE_32000		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define  CLOCK_CAP_RATE_44100		0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define  CLOCK_CAP_RATE_48000		0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define  CLOCK_CAP_RATE_88200		0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define  CLOCK_CAP_RATE_96000		0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define  CLOCK_CAP_RATE_176400		0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define  CLOCK_CAP_RATE_192000		0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define  CLOCK_CAP_SOURCE_AES1		0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define  CLOCK_CAP_SOURCE_AES2		0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define  CLOCK_CAP_SOURCE_AES3		0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define  CLOCK_CAP_SOURCE_AES4		0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define  CLOCK_CAP_SOURCE_AES_ANY	0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define  CLOCK_CAP_SOURCE_ADAT		0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define  CLOCK_CAP_SOURCE_TDIF		0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define  CLOCK_CAP_SOURCE_WC		0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define  CLOCK_CAP_SOURCE_ARX1		0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define  CLOCK_CAP_SOURCE_ARX2		0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define  CLOCK_CAP_SOURCE_ARX3		0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define  CLOCK_CAP_SOURCE_ARX4		0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define  CLOCK_CAP_SOURCE_INTERNAL	0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)  * Names of all clock sources; read-only.  Quadlets are byte-swapped.  Names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)  * are separated with one backslash, the list is terminated with two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)  * backslashes.  Unused clock sources are included.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define GLOBAL_CLOCK_SOURCE_NAMES	0x068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define  CLOCK_SOURCE_NAMES_SIZE	256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)  * Capture stream settings.  This section includes the number/size registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)  * and the registers of all streams.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)  * The number of supported capture streams; read-only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define TX_NUMBER			0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)  * The size of one stream's register block, in quadlets; read-only.  The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)  * registers of the first stream follow immediately afterwards; the registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)  * of the following streams are offset by this register's value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define TX_SIZE				0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)  * The isochronous channel number on which packets are sent, or -1 if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)  * stream is not to be used; read/write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define TX_ISOCHRONOUS			0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)  * The number of audio channels; read-only.  There will be one quadlet per
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)  * channel; the first channel is the first quadlet in a data block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define TX_NUMBER_AUDIO			0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)  * The number of MIDI ports, 0-8; read-only.  If > 0, there will be one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)  * additional quadlet in each data block, following the audio quadlets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define TX_NUMBER_MIDI			0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)  * The speed at which the packets are sent, SCODE_100-_400; read/write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)  * SCODE_800 is only available in Dice III.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define TX_SPEED			0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)  * Names of all audio channels; read-only.  Quadlets are byte-swapped.  Names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)  * are separated with one backslash, the list is terminated with two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)  * backslashes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define TX_NAMES			0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define  TX_NAMES_SIZE			256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)  * Audio IEC60958 capabilities; read-only.  Bitmask with one bit per audio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)  * channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define TX_AC3_CAPABILITIES		0x118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)  * Send audio data with IEC60958 label; read/write.  Bitmask with one bit per
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)  * audio channel.  This register can be changed even while the stream is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)  * running.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define TX_AC3_ENABLE			0x11c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)  * Playback stream settings.  This section includes the number/size registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)  * and the registers of all streams.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)  * The number of supported playback streams; read-only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define RX_NUMBER			0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)  * The size of one stream's register block, in quadlets; read-only.  The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)  * registers of the first stream follow immediately afterwards; the registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)  * of the following streams are offset by this register's value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define RX_SIZE				0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)  * The isochronous channel number on which packets are received, or -1 if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)  * stream is not to be used; read/write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define RX_ISOCHRONOUS			0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)  * Index of first quadlet to be interpreted; read/write.  If > 0, that many
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)  * quadlets at the beginning of each data block will be ignored, and all the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)  * audio and MIDI quadlets will follow.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define RX_SEQ_START			0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)  * The number of audio channels; read-only.  There will be one quadlet per
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)  * channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define RX_NUMBER_AUDIO			0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)  * The number of MIDI ports, 0-8; read-only.  If > 0, there will be one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)  * additional quadlet in each data block, following the audio quadlets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define RX_NUMBER_MIDI			0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)  * Names of all audio channels; read-only.  Quadlets are byte-swapped.  Names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)  * are separated with one backslash, the list is terminated with two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)  * backslashes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define RX_NAMES			0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define  RX_NAMES_SIZE			256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)  * Audio IEC60958 capabilities; read-only.  Bitmask with one bit per audio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)  * channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define RX_AC3_CAPABILITIES		0x118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)  * Receive audio data with IEC60958 label; read/write.  Bitmask with one bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)  * per audio channel.  This register can be changed even while the stream is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)  * running.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define RX_AC3_ENABLE			0x11c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)  * Extended synchronization information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)  * This section can be read completely with a block read request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)  * Current clock source; read-only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define EXT_SYNC_CLOCK_SOURCE		0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)  * Clock source is locked (boolean); read-only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define EXT_SYNC_LOCKED			0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)  * Current sample rate (CLOCK_RATE_* >> CLOCK_RATE_SHIFT), _32000-_192000 or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)  * _NONE; read-only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define EXT_SYNC_RATE			0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)  * ADAT user data bits; read-only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define EXT_SYNC_ADAT_USER_DATA		0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* The data bits, if available. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define  ADAT_USER_DATA_MASK		0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* The data bits are not available. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define  ADAT_USER_DATA_NO_DATA		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #endif