^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PC-Speaker driver for Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1993-1997 Michael Beck
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1997-2001 David Woodhouse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2001-2008 Stas Sergeev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __PCSP_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define __PCSP_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/hrtimer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/i8253.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/timex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PCSP_SOUND_VERSION 0x400 /* read 4.00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PCSP_DEBUG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* default timer freq for PC-Speaker: 18643 Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DIV_18KHZ 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MAX_DIV DIV_18KHZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CALC_DIV(d) (MAX_DIV >> (d))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CUR_DIV() CALC_DIV(chip->treble)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PCSP_MAX_TREBLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* unfortunately, with hrtimers 37KHz does not work very well :( */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PCSP_DEFAULT_TREBLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MIN_DIV (MAX_DIV >> PCSP_MAX_TREBLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* wild guess */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PCSP_MIN_LPJ 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PCSP_DEFAULT_SDIV (DIV_18KHZ >> 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PCSP_DEFAULT_SRATE (PIT_TICK_RATE / PCSP_DEFAULT_SDIV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PCSP_INDEX_INC() (1 << (PCSP_MAX_TREBLE - chip->treble))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PCSP_CALC_RATE(i) (PIT_TICK_RATE / CALC_DIV(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PCSP_RATE() PCSP_CALC_RATE(chip->treble)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PCSP_MIN_RATE__1 MAX_DIV/PIT_TICK_RATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PCSP_MAX_RATE__1 MIN_DIV/PIT_TICK_RATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PCSP_MAX_PERIOD_NS (1000000000ULL * PCSP_MIN_RATE__1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PCSP_MIN_PERIOD_NS (1000000000ULL * PCSP_MAX_RATE__1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PCSP_CALC_NS(div) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u64 __val = 1000000000ULL * (div); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) do_div(__val, PIT_TICK_RATE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) __val; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PCSP_PERIOD_NS() PCSP_CALC_NS(CUR_DIV())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PCSP_MAX_PERIOD_SIZE (64*1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PCSP_MAX_PERIODS 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PCSP_BUFFER_SIZE (128*1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct snd_pcsp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct snd_card *card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct snd_pcm *pcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct input_dev *input_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct hrtimer timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned short port, irq, dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) spinlock_t substream_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct snd_pcm_substream *playback_substream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned int fmt_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned int is_signed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) size_t playback_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) size_t period_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) atomic_t timer_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) int thalf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u64 ns_rem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned char val61;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int max_treble;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int treble;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int pcspkr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) extern struct snd_pcsp pcsp_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) extern enum hrtimer_restart pcsp_do_timer(struct hrtimer *handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) extern void pcsp_sync_stop(struct snd_pcsp *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) extern int snd_pcsp_new_pcm(struct snd_pcsp *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) extern int snd_pcsp_new_mixer(struct snd_pcsp *chip, int nopcm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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