Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Functions for accessing OPL4 devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (c) 2003 by Clemens Ladisch <clemens@ladisch.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include "opl4_local.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <sound/initval.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) MODULE_DESCRIPTION("OPL4 driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) static inline void snd_opl4_wait(struct snd_opl4 *opl4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	int timeout = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	while ((inb(opl4->fm_port) & OPL4_STATUS_BUSY) && --timeout > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 		;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) void snd_opl4_write(struct snd_opl4 *opl4, u8 reg, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	snd_opl4_wait(opl4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	outb(reg, opl4->pcm_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	snd_opl4_wait(opl4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	outb(value, opl4->pcm_port + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) EXPORT_SYMBOL(snd_opl4_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) u8 snd_opl4_read(struct snd_opl4 *opl4, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	snd_opl4_wait(opl4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	outb(reg, opl4->pcm_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	snd_opl4_wait(opl4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	return inb(opl4->pcm_port + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) EXPORT_SYMBOL(snd_opl4_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) void snd_opl4_read_memory(struct snd_opl4 *opl4, char *buf, int offset, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	u8 memcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	spin_lock_irqsave(&opl4->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	memcfg = snd_opl4_read(opl4, OPL4_REG_MEMORY_CONFIGURATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	snd_opl4_write(opl4, OPL4_REG_MEMORY_CONFIGURATION, memcfg | OPL4_MODE_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	snd_opl4_write(opl4, OPL4_REG_MEMORY_ADDRESS_HIGH, offset >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	snd_opl4_write(opl4, OPL4_REG_MEMORY_ADDRESS_MID, offset >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	snd_opl4_write(opl4, OPL4_REG_MEMORY_ADDRESS_LOW, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	snd_opl4_wait(opl4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	outb(OPL4_REG_MEMORY_DATA, opl4->pcm_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	snd_opl4_wait(opl4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	insb(opl4->pcm_port + 1, buf, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	snd_opl4_write(opl4, OPL4_REG_MEMORY_CONFIGURATION, memcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	spin_unlock_irqrestore(&opl4->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) EXPORT_SYMBOL(snd_opl4_read_memory);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) void snd_opl4_write_memory(struct snd_opl4 *opl4, const char *buf, int offset, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	u8 memcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	spin_lock_irqsave(&opl4->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	memcfg = snd_opl4_read(opl4, OPL4_REG_MEMORY_CONFIGURATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	snd_opl4_write(opl4, OPL4_REG_MEMORY_CONFIGURATION, memcfg | OPL4_MODE_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	snd_opl4_write(opl4, OPL4_REG_MEMORY_ADDRESS_HIGH, offset >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	snd_opl4_write(opl4, OPL4_REG_MEMORY_ADDRESS_MID, offset >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	snd_opl4_write(opl4, OPL4_REG_MEMORY_ADDRESS_LOW, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	snd_opl4_wait(opl4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	outb(OPL4_REG_MEMORY_DATA, opl4->pcm_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	snd_opl4_wait(opl4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	outsb(opl4->pcm_port + 1, buf, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	snd_opl4_write(opl4, OPL4_REG_MEMORY_CONFIGURATION, memcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	spin_unlock_irqrestore(&opl4->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) EXPORT_SYMBOL(snd_opl4_write_memory);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static void snd_opl4_enable_opl4(struct snd_opl4 *opl4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	outb(OPL3_REG_MODE, opl4->fm_port + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	inb(opl4->fm_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	inb(opl4->fm_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	outb(OPL3_OPL3_ENABLE | OPL3_OPL4_ENABLE, opl4->fm_port + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	inb(opl4->fm_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	inb(opl4->fm_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int snd_opl4_detect(struct snd_opl4 *opl4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	u8 id1, id2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	snd_opl4_enable_opl4(opl4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	id1 = snd_opl4_read(opl4, OPL4_REG_MEMORY_CONFIGURATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	snd_printdd("OPL4[02]=%02x\n", id1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	switch (id1 & OPL4_DEVICE_ID_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	case 0x20:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		opl4->hardware = OPL3_HW_OPL4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	case 0x40:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		opl4->hardware = OPL3_HW_OPL4_ML;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	snd_opl4_write(opl4, OPL4_REG_MIX_CONTROL_FM, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	snd_opl4_write(opl4, OPL4_REG_MIX_CONTROL_PCM, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	id1 = snd_opl4_read(opl4, OPL4_REG_MIX_CONTROL_FM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	id2 = snd_opl4_read(opl4, OPL4_REG_MIX_CONTROL_PCM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	snd_printdd("OPL4 id1=%02x id2=%02x\n", id1, id2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)        	if (id1 != 0x00 || id2 != 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	snd_opl4_write(opl4, OPL4_REG_MIX_CONTROL_FM, 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	snd_opl4_write(opl4, OPL4_REG_MIX_CONTROL_PCM, 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	snd_opl4_write(opl4, OPL4_REG_MEMORY_CONFIGURATION, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #if IS_ENABLED(CONFIG_SND_SEQUENCER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static void snd_opl4_seq_dev_free(struct snd_seq_device *seq_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	struct snd_opl4 *opl4 = seq_dev->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	opl4->seq_dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int snd_opl4_create_seq_dev(struct snd_opl4 *opl4, int seq_device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	opl4->seq_dev_num = seq_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	if (snd_seq_device_new(opl4->card, seq_device, SNDRV_SEQ_DEV_ID_OPL4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 			       sizeof(struct snd_opl4 *), &opl4->seq_dev) >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		strcpy(opl4->seq_dev->name, "OPL4 Wavetable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		*(struct snd_opl4 **)SNDRV_SEQ_DEVICE_ARGPTR(opl4->seq_dev) = opl4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		opl4->seq_dev->private_data = opl4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		opl4->seq_dev->private_free = snd_opl4_seq_dev_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static void snd_opl4_free(struct snd_opl4 *opl4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	snd_opl4_free_proc(opl4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	release_and_free_resource(opl4->res_fm_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	release_and_free_resource(opl4->res_pcm_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	kfree(opl4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int snd_opl4_dev_free(struct snd_device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	struct snd_opl4 *opl4 = device->device_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	snd_opl4_free(opl4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int snd_opl4_create(struct snd_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		    unsigned long fm_port, unsigned long pcm_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		    int seq_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		    struct snd_opl3 **ropl3, struct snd_opl4 **ropl4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	struct snd_opl4 *opl4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	struct snd_opl3 *opl3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	static const struct snd_device_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		.dev_free = snd_opl4_dev_free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	if (ropl3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		*ropl3 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	if (ropl4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		*ropl4 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	opl4 = kzalloc(sizeof(*opl4), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	if (!opl4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	opl4->res_fm_port = request_region(fm_port, 8, "OPL4 FM");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	opl4->res_pcm_port = request_region(pcm_port, 8, "OPL4 PCM/MIX");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	if (!opl4->res_fm_port || !opl4->res_pcm_port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		snd_printk(KERN_ERR "opl4: can't grab ports 0x%lx, 0x%lx\n", fm_port, pcm_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		snd_opl4_free(opl4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	opl4->card = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	opl4->fm_port = fm_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	opl4->pcm_port = pcm_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	spin_lock_init(&opl4->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	mutex_init(&opl4->access_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	err = snd_opl4_detect(opl4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		snd_opl4_free(opl4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		snd_printd("OPL4 chip not detected at %#lx/%#lx\n", fm_port, pcm_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	err = snd_device_new(card, SNDRV_DEV_CODEC, opl4, &ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		snd_opl4_free(opl4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	err = snd_opl3_create(card, fm_port, fm_port + 2, opl4->hardware, 1, &opl3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		snd_device_free(card, opl4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	/* opl3 initialization disabled opl4, so reenable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	snd_opl4_enable_opl4(opl4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	snd_opl4_create_mixer(opl4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	snd_opl4_create_proc(opl4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #if IS_ENABLED(CONFIG_SND_SEQUENCER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	opl4->seq_client = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	if (opl4->hardware < OPL3_HW_OPL4_ML)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		snd_opl4_create_seq_dev(opl4, seq_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	if (ropl3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		*ropl3 = opl3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	if (ropl4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		*ropl4 = opl4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) EXPORT_SYMBOL(snd_opl4_create);