Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *                   Hannu Savolainen 1993-1996,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *                   Rob Hooft
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *                   
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *  Routines for control of AdLib FM cards (OPL2/OPL3/OPL4 chips)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *  Most if code is ported from OSS/Lite.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <sound/opl3.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <sound/minors.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include "opl3_voice.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>, Hannu Savolainen 1993-1996, Rob Hooft");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) MODULE_DESCRIPTION("Routines for control of AdLib FM cards (OPL2/OPL3/OPL4 chips)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) static void snd_opl2_command(struct snd_opl3 * opl3, unsigned short cmd, unsigned char val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	unsigned long port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	 * The original 2-OP synth requires a quite long delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	 * after writing to a register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	port = (cmd & OPL3_RIGHT) ? opl3->r_port : opl3->l_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	spin_lock_irqsave(&opl3->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	outb((unsigned char) cmd, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	outb((unsigned char) val, port + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	udelay(30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	spin_unlock_irqrestore(&opl3->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) static void snd_opl3_command(struct snd_opl3 * opl3, unsigned short cmd, unsigned char val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	unsigned long port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	 * The OPL-3 survives with just two INBs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	 * after writing to a register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	port = (cmd & OPL3_RIGHT) ? opl3->r_port : opl3->l_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	spin_lock_irqsave(&opl3->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	outb((unsigned char) cmd, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	inb(opl3->l_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	inb(opl3->l_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	outb((unsigned char) val, port + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	inb(opl3->l_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	inb(opl3->l_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	spin_unlock_irqrestore(&opl3->reg_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static int snd_opl3_detect(struct snd_opl3 * opl3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	 * This function returns 1 if the FM chip is present at the given I/O port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	 * The detection algorithm plays with the timer built in the FM chip and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	 * looks for a change in the status register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	 * Note! The timers of the FM chip are not connected to AdLib (and compatible)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	 * boards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	 * Note2! The chip is initialized if detected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	unsigned char stat1, stat2, signature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	/* Reset timers 1 and 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER_CONTROL, OPL3_TIMER1_MASK | OPL3_TIMER2_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	/* Reset the IRQ of the FM chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER_CONTROL, OPL3_IRQ_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	signature = stat1 = inb(opl3->l_port);	/* Status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	if ((stat1 & 0xe0) != 0x00) {	/* Should be 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		snd_printd("OPL3: stat1 = 0x%x\n", stat1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	/* Set timer1 to 0xff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER1, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	/* Unmask and start timer 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER_CONTROL, OPL3_TIMER2_MASK | OPL3_TIMER1_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	/* Now we have to delay at least 80us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	udelay(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	/* Read status after timers have expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	stat2 = inb(opl3->l_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	/* Stop the timers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER_CONTROL, OPL3_TIMER1_MASK | OPL3_TIMER2_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	/* Reset the IRQ of the FM chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER_CONTROL, OPL3_IRQ_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	if ((stat2 & 0xe0) != 0xc0) {	/* There is no YM3812 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		snd_printd("OPL3: stat2 = 0x%x\n", stat2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	/* If the toplevel code knows exactly the type of chip, don't try
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	   to detect it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	if (opl3->hardware != OPL3_HW_AUTO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	/* There is a FM chip on this address. Detect the type (OPL2 to OPL4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	if (signature == 0x06) {	/* OPL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		opl3->hardware = OPL3_HW_OPL2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		 * If we had an OPL4 chip, opl3->hardware would have been set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		 * by the OPL4 driver; so we can assume OPL3 here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		if (snd_BUG_ON(!opl3->r_port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		opl3->hardware = OPL3_HW_OPL3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)  *  AdLib timers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)  *  Timer 1 - 80us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int snd_opl3_timer1_start(struct snd_timer * timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	unsigned char tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	unsigned int ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	struct snd_opl3 *opl3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	opl3 = snd_timer_chip(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	spin_lock_irqsave(&opl3->timer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	ticks = timer->sticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	tmp = (opl3->timer_enable | OPL3_TIMER1_START) & ~OPL3_TIMER1_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	opl3->timer_enable = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER1, 256 - ticks);	/* timer 1 count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER_CONTROL, tmp);	/* enable timer 1 IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	spin_unlock_irqrestore(&opl3->timer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static int snd_opl3_timer1_stop(struct snd_timer * timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	unsigned char tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	struct snd_opl3 *opl3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	opl3 = snd_timer_chip(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	spin_lock_irqsave(&opl3->timer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	tmp = (opl3->timer_enable | OPL3_TIMER1_MASK) & ~OPL3_TIMER1_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	opl3->timer_enable = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER_CONTROL, tmp);	/* disable timer #1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	spin_unlock_irqrestore(&opl3->timer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)  *  Timer 2 - 320us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static int snd_opl3_timer2_start(struct snd_timer * timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	unsigned char tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	unsigned int ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	struct snd_opl3 *opl3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	opl3 = snd_timer_chip(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	spin_lock_irqsave(&opl3->timer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	ticks = timer->sticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	tmp = (opl3->timer_enable | OPL3_TIMER2_START) & ~OPL3_TIMER2_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	opl3->timer_enable = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER2, 256 - ticks);	/* timer 1 count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER_CONTROL, tmp);	/* enable timer 1 IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	spin_unlock_irqrestore(&opl3->timer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static int snd_opl3_timer2_stop(struct snd_timer * timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	unsigned char tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	struct snd_opl3 *opl3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	opl3 = snd_timer_chip(timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	spin_lock_irqsave(&opl3->timer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	tmp = (opl3->timer_enable | OPL3_TIMER2_MASK) & ~OPL3_TIMER2_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	opl3->timer_enable = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	opl3->command(opl3, OPL3_LEFT | OPL3_REG_TIMER_CONTROL, tmp);	/* disable timer #1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	spin_unlock_irqrestore(&opl3->timer_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static const struct snd_timer_hardware snd_opl3_timer1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	.flags =	SNDRV_TIMER_HW_STOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	.resolution =	80000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	.ticks =	256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	.start =	snd_opl3_timer1_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	.stop =		snd_opl3_timer1_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static const struct snd_timer_hardware snd_opl3_timer2 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	.flags =	SNDRV_TIMER_HW_STOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	.resolution =	320000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	.ticks =	256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	.start =	snd_opl3_timer2_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	.stop =		snd_opl3_timer2_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static int snd_opl3_timer1_init(struct snd_opl3 * opl3, int timer_no)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	struct snd_timer *timer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	struct snd_timer_id tid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	tid.dev_class = SNDRV_TIMER_CLASS_CARD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	tid.card = opl3->card->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	tid.device = timer_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	tid.subdevice = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	if ((err = snd_timer_new(opl3->card, "AdLib timer #1", &tid, &timer)) >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		strcpy(timer->name, "AdLib timer #1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		timer->private_data = opl3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		timer->hw = snd_opl3_timer1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	opl3->timer1 = timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static int snd_opl3_timer2_init(struct snd_opl3 * opl3, int timer_no)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	struct snd_timer *timer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	struct snd_timer_id tid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	tid.dev_class = SNDRV_TIMER_CLASS_CARD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	tid.card = opl3->card->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	tid.device = timer_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	tid.subdevice = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	if ((err = snd_timer_new(opl3->card, "AdLib timer #2", &tid, &timer)) >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		strcpy(timer->name, "AdLib timer #2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		timer->private_data = opl3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		timer->hw = snd_opl3_timer2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	opl3->timer2 = timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) void snd_opl3_interrupt(struct snd_hwdep * hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	unsigned char status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	struct snd_opl3 *opl3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	struct snd_timer *timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	if (hw == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	opl3 = hw->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	status = inb(opl3->l_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	snd_printk(KERN_DEBUG "AdLib IRQ status = 0x%x\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	if (!(status & 0x80))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	if (status & 0x40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		timer = opl3->timer1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		snd_timer_interrupt(timer, timer->sticks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	if (status & 0x20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		timer = opl3->timer2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		snd_timer_interrupt(timer, timer->sticks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) EXPORT_SYMBOL(snd_opl3_interrupt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static int snd_opl3_free(struct snd_opl3 *opl3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	if (snd_BUG_ON(!opl3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	if (opl3->private_free)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		opl3->private_free(opl3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	snd_opl3_clear_patches(opl3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	release_and_free_resource(opl3->res_l_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	release_and_free_resource(opl3->res_r_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	kfree(opl3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static int snd_opl3_dev_free(struct snd_device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	struct snd_opl3 *opl3 = device->device_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	return snd_opl3_free(opl3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) int snd_opl3_new(struct snd_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		 unsigned short hardware,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		 struct snd_opl3 **ropl3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	static const struct snd_device_ops ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		.dev_free = snd_opl3_dev_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	struct snd_opl3 *opl3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	*ropl3 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	opl3 = kzalloc(sizeof(*opl3), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	if (!opl3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	opl3->card = card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	opl3->hardware = hardware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	spin_lock_init(&opl3->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	spin_lock_init(&opl3->timer_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	if ((err = snd_device_new(card, SNDRV_DEV_CODEC, opl3, &ops)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		snd_opl3_free(opl3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	*ropl3 = opl3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) EXPORT_SYMBOL(snd_opl3_new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) int snd_opl3_init(struct snd_opl3 *opl3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	if (! opl3->command) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		printk(KERN_ERR "snd_opl3_init: command not defined!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	opl3->command(opl3, OPL3_LEFT | OPL3_REG_TEST, OPL3_ENABLE_WAVE_SELECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	/* Melodic mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	opl3->command(opl3, OPL3_LEFT | OPL3_REG_PERCUSSION, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	switch (opl3->hardware & OPL3_HW_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	case OPL3_HW_OPL2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		opl3->max_voices = MAX_OPL2_VOICES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	case OPL3_HW_OPL3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	case OPL3_HW_OPL4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		opl3->max_voices = MAX_OPL3_VOICES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		/* Enter OPL3 mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		opl3->command(opl3, OPL3_RIGHT | OPL3_REG_MODE, OPL3_OPL3_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) EXPORT_SYMBOL(snd_opl3_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) int snd_opl3_create(struct snd_card *card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		    unsigned long l_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		    unsigned long r_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		    unsigned short hardware,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 		    int integrated,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		    struct snd_opl3 ** ropl3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	struct snd_opl3 *opl3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	*ropl3 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	if ((err = snd_opl3_new(card, hardware, &opl3)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	if (! integrated) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 		if ((opl3->res_l_port = request_region(l_port, 2, "OPL2/3 (left)")) == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 			snd_printk(KERN_ERR "opl3: can't grab left port 0x%lx\n", l_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 			snd_device_free(card, opl3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 			return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		if (r_port != 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 		    (opl3->res_r_port = request_region(r_port, 2, "OPL2/3 (right)")) == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 			snd_printk(KERN_ERR "opl3: can't grab right port 0x%lx\n", r_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 			snd_device_free(card, opl3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 			return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	opl3->l_port = l_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	opl3->r_port = r_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	switch (opl3->hardware) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	/* some hardware doesn't support timers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	case OPL3_HW_OPL3_SV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	case OPL3_HW_OPL3_CS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	case OPL3_HW_OPL3_FM801:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 		opl3->command = &snd_opl3_command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 		opl3->command = &snd_opl2_command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 		if ((err = snd_opl3_detect(opl3)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 			snd_printd("OPL2/3 chip not detected at 0x%lx/0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 				   opl3->l_port, opl3->r_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 			snd_device_free(card, opl3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 		/* detect routine returns correct hardware type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 		switch (opl3->hardware & OPL3_HW_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 		case OPL3_HW_OPL3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 		case OPL3_HW_OPL4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 			opl3->command = &snd_opl3_command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	snd_opl3_init(opl3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	*ropl3 = opl3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) EXPORT_SYMBOL(snd_opl3_create);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) int snd_opl3_timer_new(struct snd_opl3 * opl3, int timer1_dev, int timer2_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	if (timer1_dev >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 		if ((err = snd_opl3_timer1_init(opl3, timer1_dev)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	if (timer2_dev >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 		if ((err = snd_opl3_timer2_init(opl3, timer2_dev)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 			snd_device_free(opl3->card, opl3->timer1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 			opl3->timer1 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) EXPORT_SYMBOL(snd_opl3_timer_new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) int snd_opl3_hwdep_new(struct snd_opl3 * opl3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 		       int device, int seq_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 		       struct snd_hwdep ** rhwdep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	struct snd_hwdep *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	struct snd_card *card = opl3->card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	if (rhwdep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 		*rhwdep = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	/* create hardware dependent device (direct FM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	if ((err = snd_hwdep_new(card, "OPL2/OPL3", device, &hw)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 		snd_device_free(card, opl3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	hw->private_data = opl3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	hw->exclusive = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #ifdef CONFIG_SND_OSSEMUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	if (device == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 		hw->oss_type = SNDRV_OSS_DEVICE_TYPE_DMFM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	strcpy(hw->name, hw->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	switch (opl3->hardware & OPL3_HW_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	case OPL3_HW_OPL2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 		strcpy(hw->name, "OPL2 FM");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 		hw->iface = SNDRV_HWDEP_IFACE_OPL2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	case OPL3_HW_OPL3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 		strcpy(hw->name, "OPL3 FM");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 		hw->iface = SNDRV_HWDEP_IFACE_OPL3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	case OPL3_HW_OPL4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 		strcpy(hw->name, "OPL4 FM");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 		hw->iface = SNDRV_HWDEP_IFACE_OPL4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	/* operators - only ioctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	hw->ops.open = snd_opl3_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	hw->ops.ioctl = snd_opl3_ioctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	hw->ops.write = snd_opl3_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	hw->ops.release = snd_opl3_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 	opl3->hwdep = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	opl3->seq_dev_num = seq_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #if IS_ENABLED(CONFIG_SND_SEQUENCER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	if (snd_seq_device_new(card, seq_device, SNDRV_SEQ_DEV_ID_OPL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 			       sizeof(struct snd_opl3 *), &opl3->seq_dev) >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 		strcpy(opl3->seq_dev->name, hw->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 		*(struct snd_opl3 **)SNDRV_SEQ_DEVICE_ARGPTR(opl3->seq_dev) = opl3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 	if (rhwdep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 		*rhwdep = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) EXPORT_SYMBOL(snd_opl3_hwdep_new);